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authorKukjin Kim <kgene.kim@samsung.com>2010-01-28 20:17:20 -0500
committerBen Dooks <ben-linux@fluff.org>2010-02-23 20:52:16 -0500
commitd9f18a981bd0a724c87d04db1d61d91261a2feb4 (patch)
tree042add1409bb9f1ac19f429a2ed2a1768e52fa52 /arch/arm/plat-s5p/include
parentb6f837575edc5213e00903afea240f0119ee5ec9 (diff)
ARM: S5P6442: Add IRQ support
This patch adds IRQ support for S5P6442. This patch adds interrupt register definitions, IRQ definitions for various interrupt sources and new VIC base for VIC2 in plat-s5p common irq code. Signed-off-by: Adityapratap Sharma <aditya.ps@samsung.com> Signed-off-by: Atul Dahiya <atul.dahiya@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s5p/include')
-rw-r--r--arch/arm/plat-s5p/include/plat/irqs.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h
index 101038d49944..9daad19ccd0d 100644
--- a/arch/arm/plat-s5p/include/plat/irqs.h
+++ b/arch/arm/plat-s5p/include/plat/irqs.h
@@ -28,11 +28,13 @@
28 28
29#define S5P_VIC0_BASE S5P_IRQ(0) 29#define S5P_VIC0_BASE S5P_IRQ(0)
30#define S5P_VIC1_BASE S5P_IRQ(32) 30#define S5P_VIC1_BASE S5P_IRQ(32)
31#define S5P_VIC2_BASE S5P_IRQ(64)
31 32
32#define VIC_BASE(x) (S5P_VIC0_BASE + ((x)*32)) 33#define VIC_BASE(x) (S5P_VIC0_BASE + ((x)*32))
33 34
34#define IRQ_VIC0_BASE S5P_VIC0_BASE 35#define IRQ_VIC0_BASE S5P_VIC0_BASE
35#define IRQ_VIC1_BASE S5P_VIC1_BASE 36#define IRQ_VIC1_BASE S5P_VIC1_BASE
37#define IRQ_VIC2_BASE S5P_VIC2_BASE
36 38
37/* UART interrupts, each UART has 4 intterupts per channel so 39/* UART interrupts, each UART has 4 intterupts per channel so
38 * use the space between the ISA and S3C main interrupts. Note, these 40 * use the space between the ISA and S3C main interrupts. Note, these
@@ -73,6 +75,7 @@
73 75
74#define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x)) 76#define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x))
75#define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x)) 77#define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x))
78#define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x))
76 79
77#define S5P_TIMER_IRQ(x) S5P_IRQ(11 + (x)) 80#define S5P_TIMER_IRQ(x) S5P_IRQ(11 + (x))
78 81