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authorLinus Torvalds <torvalds@linux-foundation.org>2011-11-01 23:25:36 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-11-01 23:25:36 -0400
commitf906fb1d70e016726fccfb0d978c5d425503db9d (patch)
treeb2bac5fbe7d2eb81dd7fe6cc88e27dddd0189c84 /arch/arm/plat-s5p/cpu.c
parent510597e26e2a072e2d46ea5bc57feaf385e37f70 (diff)
parenta7fadac10ffbfd16cc7ccf951eab1ecf85e1abdf (diff)
Merge branch 'next/board' of git://git.linaro.org/people/arnd/arm-soc
* 'next/board' of git://git.linaro.org/people/arnd/arm-soc: (34 commits) ep93xx: add support Vision EP9307 SoM ARM: mxs: Add initial support for DENX MX28 ARM: EXYNOS4: Add support SMDK4412 Board ARM: EXYNOS4: Add MCT support for EXYNOS4412 ARM: EXYNOS4: Add functions for gic interrupt handling ARM: EXYNOS4: Add support clock for EXYNOS4412 ARM: EXYNOS4: Add support new EXYNOS4412 SoC ARM: EXYNOS4: Add support MCT PPI for EXYNOS4212 ARM: EXYNOS4: Add support PPI in external GIC ARM: EXYNOS4: convert boot_params to atag_offset ixp4xx: support omicron ixp425 based boards ARM: EXYNOS4: Add support SMDK4212 Board ARM: EXYNOS4: Add support PM for EXYNOS4212 ARM: EXYNOS4: Add support clock for EXYNOS4212 ARM: EXYNOS4: Add support new EXYNOS4212 SoC at91: USB-A9G20 C01 & C11 board support at91: merge board USB-A9260 and USB-A9263 together at91: add support for RSIs EWS board ARM: SAMSUNG: Fix mask value for S5P64X0 CPU IDs ARM: SAMSUNG: Fix mask for S3C64xx CPU IDs ...
Diffstat (limited to 'arch/arm/plat-s5p/cpu.c')
-rw-r--r--arch/arm/plat-s5p/cpu.c46
1 files changed, 32 insertions, 14 deletions
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index bbc2aa7449ca..7b0a28f73a68 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -33,48 +33,66 @@ static const char name_s5p6450[] = "S5P6450";
33static const char name_s5pc100[] = "S5PC100"; 33static const char name_s5pc100[] = "S5PC100";
34static const char name_s5pv210[] = "S5PV210/S5PC110"; 34static const char name_s5pv210[] = "S5PV210/S5PC110";
35static const char name_exynos4210[] = "EXYNOS4210"; 35static const char name_exynos4210[] = "EXYNOS4210";
36static const char name_exynos4212[] = "EXYNOS4212";
37static const char name_exynos4412[] = "EXYNOS4412";
36 38
37static struct cpu_table cpu_ids[] __initdata = { 39static struct cpu_table cpu_ids[] __initdata = {
38 { 40 {
39 .idcode = 0x56440100, 41 .idcode = S5P6440_CPU_ID,
40 .idmask = 0xfffff000, 42 .idmask = S5P64XX_CPU_MASK,
41 .map_io = s5p6440_map_io, 43 .map_io = s5p6440_map_io,
42 .init_clocks = s5p6440_init_clocks, 44 .init_clocks = s5p6440_init_clocks,
43 .init_uarts = s5p6440_init_uarts, 45 .init_uarts = s5p6440_init_uarts,
44 .init = s5p64x0_init, 46 .init = s5p64x0_init,
45 .name = name_s5p6440, 47 .name = name_s5p6440,
46 }, { 48 }, {
47 .idcode = 0x36450000, 49 .idcode = S5P6450_CPU_ID,
48 .idmask = 0xfffff000, 50 .idmask = S5P64XX_CPU_MASK,
49 .map_io = s5p6450_map_io, 51 .map_io = s5p6450_map_io,
50 .init_clocks = s5p6450_init_clocks, 52 .init_clocks = s5p6450_init_clocks,
51 .init_uarts = s5p6450_init_uarts, 53 .init_uarts = s5p6450_init_uarts,
52 .init = s5p64x0_init, 54 .init = s5p64x0_init,
53 .name = name_s5p6450, 55 .name = name_s5p6450,
54 }, { 56 }, {
55 .idcode = 0x43100000, 57 .idcode = S5PC100_CPU_ID,
56 .idmask = 0xfffff000, 58 .idmask = S5PC100_CPU_MASK,
57 .map_io = s5pc100_map_io, 59 .map_io = s5pc100_map_io,
58 .init_clocks = s5pc100_init_clocks, 60 .init_clocks = s5pc100_init_clocks,
59 .init_uarts = s5pc100_init_uarts, 61 .init_uarts = s5pc100_init_uarts,
60 .init = s5pc100_init, 62 .init = s5pc100_init,
61 .name = name_s5pc100, 63 .name = name_s5pc100,
62 }, { 64 }, {
63 .idcode = 0x43110000, 65 .idcode = S5PV210_CPU_ID,
64 .idmask = 0xfffff000, 66 .idmask = S5PV210_CPU_MASK,
65 .map_io = s5pv210_map_io, 67 .map_io = s5pv210_map_io,
66 .init_clocks = s5pv210_init_clocks, 68 .init_clocks = s5pv210_init_clocks,
67 .init_uarts = s5pv210_init_uarts, 69 .init_uarts = s5pv210_init_uarts,
68 .init = s5pv210_init, 70 .init = s5pv210_init,
69 .name = name_s5pv210, 71 .name = name_s5pv210,
70 }, { 72 }, {
71 .idcode = 0x43210000, 73 .idcode = EXYNOS4210_CPU_ID,
72 .idmask = 0xfffe0000, 74 .idmask = EXYNOS4_CPU_MASK,
73 .map_io = exynos4_map_io, 75 .map_io = exynos4_map_io,
74 .init_clocks = exynos4_init_clocks, 76 .init_clocks = exynos4_init_clocks,
75 .init_uarts = exynos4_init_uarts, 77 .init_uarts = exynos4_init_uarts,
76 .init = exynos4_init, 78 .init = exynos4_init,
77 .name = name_exynos4210, 79 .name = name_exynos4210,
80 }, {
81 .idcode = EXYNOS4212_CPU_ID,
82 .idmask = EXYNOS4_CPU_MASK,
83 .map_io = exynos4_map_io,
84 .init_clocks = exynos4_init_clocks,
85 .init_uarts = exynos4_init_uarts,
86 .init = exynos4_init,
87 .name = name_exynos4212,
88 }, {
89 .idcode = EXYNOS4412_CPU_ID,
90 .idmask = EXYNOS4_CPU_MASK,
91 .map_io = exynos4_map_io,
92 .init_clocks = exynos4_init_clocks,
93 .init_uarts = exynos4_init_uarts,
94 .init = exynos4_init,
95 .name = name_exynos4412,
78 }, 96 },
79}; 97};
80 98
@@ -114,13 +132,13 @@ static struct map_desc s5p_iodesc[] __initdata = {
114void __init s5p_init_io(struct map_desc *mach_desc, 132void __init s5p_init_io(struct map_desc *mach_desc,
115 int size, void __iomem *cpuid_addr) 133 int size, void __iomem *cpuid_addr)
116{ 134{
117 unsigned long idcode;
118
119 /* initialize the io descriptors we need for initialization */ 135 /* initialize the io descriptors we need for initialization */
120 iotable_init(s5p_iodesc, ARRAY_SIZE(s5p_iodesc)); 136 iotable_init(s5p_iodesc, ARRAY_SIZE(s5p_iodesc));
121 if (mach_desc) 137 if (mach_desc)
122 iotable_init(mach_desc, size); 138 iotable_init(mach_desc, size);
123 139
124 idcode = __raw_readl(cpuid_addr); 140 /* detect cpu id and rev. */
125 s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); 141 s5p_init_cpu(cpuid_addr);
142
143 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
126} 144}