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authorBen Dooks <ben-linux@fluff.org>2009-12-23 13:43:48 -0500
committerBen Dooks <ben-linux@fluff.org>2010-01-15 03:10:11 -0500
commit2c2f69b15d5420291a941ace10149e76f0af7ab0 (patch)
treed2e8725f81cc0b877658dd828a7f40d45f88df01 /arch/arm/plat-s3c
parent682e2b7d45878586ce84f6993da0b8a2981a399d (diff)
ARM: SAMSUNG: Move clock.c to arch/arm/plat-samsung
This is the core implementation of the clock code for all Samsung based SoCs, so move it to arch/arm/plat-samsung (the clock.h file has already been moved). Since the file is built for every Samsung SoC, no changes are needed to the Kconfig system. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c')
-rw-r--r--arch/arm/plat-s3c/Makefile3
-rw-r--r--arch/arm/plat-s3c/clock.c369
2 files changed, 1 insertions, 371 deletions
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile
index 50444da98425..99f91ad1d555 100644
--- a/arch/arm/plat-s3c/Makefile
+++ b/arch/arm/plat-s3c/Makefile
@@ -11,9 +11,8 @@ obj- :=
11 11
12# Core support for all Samsung SoCs 12# Core support for all Samsung SoCs
13 13
14obj-y += init.o 14obj-y += init.o
15obj-y += time.o 15obj-y += time.o
16obj-y += clock.o
17obj-y += pwm-clock.o 16obj-y += pwm-clock.o
18obj-y += gpio.o 17obj-y += gpio.o
19obj-y += gpio-config.o 18obj-y += gpio-config.o
diff --git a/arch/arm/plat-s3c/clock.c b/arch/arm/plat-s3c/clock.c
deleted file mode 100644
index fa91125c7e0e..000000000000
--- a/arch/arm/plat-s3c/clock.c
+++ /dev/null
@@ -1,369 +0,0 @@
1/* linux/arch/arm/plat-s3c24xx/clock.c
2 *
3 * Copyright 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C24XX Core clock control support
7 *
8 * Based on, and code from linux/arch/arm/mach-versatile/clock.c
9 **
10 ** Copyright (C) 2004 ARM Limited.
11 ** Written by Deep Blue Solutions Limited.
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27*/
28
29#include <linux/init.h>
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/list.h>
33#include <linux/errno.h>
34#include <linux/err.h>
35#include <linux/platform_device.h>
36#include <linux/sysdev.h>
37#include <linux/interrupt.h>
38#include <linux/ioport.h>
39#include <linux/clk.h>
40#include <linux/spinlock.h>
41#include <linux/io.h>
42
43#include <mach/hardware.h>
44#include <asm/irq.h>
45
46#include <plat/cpu-freq.h>
47
48#include <plat/clock.h>
49#include <plat/cpu.h>
50
51/* clock information */
52
53static LIST_HEAD(clocks);
54
55/* We originally used an mutex here, but some contexts (see resume)
56 * are calling functions such as clk_set_parent() with IRQs disabled
57 * causing an BUG to be triggered.
58 */
59DEFINE_SPINLOCK(clocks_lock);
60
61/* enable and disable calls for use with the clk struct */
62
63static int clk_null_enable(struct clk *clk, int enable)
64{
65 return 0;
66}
67
68/* Clock API calls */
69
70struct clk *clk_get(struct device *dev, const char *id)
71{
72 struct clk *p;
73 struct clk *clk = ERR_PTR(-ENOENT);
74 int idno;
75
76 if (dev == NULL || dev->bus != &platform_bus_type)
77 idno = -1;
78 else
79 idno = to_platform_device(dev)->id;
80
81 spin_lock(&clocks_lock);
82
83 list_for_each_entry(p, &clocks, list) {
84 if (p->id == idno &&
85 strcmp(id, p->name) == 0 &&
86 try_module_get(p->owner)) {
87 clk = p;
88 break;
89 }
90 }
91
92 /* check for the case where a device was supplied, but the
93 * clock that was being searched for is not device specific */
94
95 if (IS_ERR(clk)) {
96 list_for_each_entry(p, &clocks, list) {
97 if (p->id == -1 && strcmp(id, p->name) == 0 &&
98 try_module_get(p->owner)) {
99 clk = p;
100 break;
101 }
102 }
103 }
104
105 spin_unlock(&clocks_lock);
106 return clk;
107}
108
109void clk_put(struct clk *clk)
110{
111 module_put(clk->owner);
112}
113
114int clk_enable(struct clk *clk)
115{
116 if (IS_ERR(clk) || clk == NULL)
117 return -EINVAL;
118
119 clk_enable(clk->parent);
120
121 spin_lock(&clocks_lock);
122
123 if ((clk->usage++) == 0)
124 (clk->enable)(clk, 1);
125
126 spin_unlock(&clocks_lock);
127 return 0;
128}
129
130void clk_disable(struct clk *clk)
131{
132 if (IS_ERR(clk) || clk == NULL)
133 return;
134
135 spin_lock(&clocks_lock);
136
137 if ((--clk->usage) == 0)
138 (clk->enable)(clk, 0);
139
140 spin_unlock(&clocks_lock);
141 clk_disable(clk->parent);
142}
143
144
145unsigned long clk_get_rate(struct clk *clk)
146{
147 if (IS_ERR(clk))
148 return 0;
149
150 if (clk->rate != 0)
151 return clk->rate;
152
153 if (clk->ops != NULL && clk->ops->get_rate != NULL)
154 return (clk->ops->get_rate)(clk);
155
156 if (clk->parent != NULL)
157 return clk_get_rate(clk->parent);
158
159 return clk->rate;
160}
161
162long clk_round_rate(struct clk *clk, unsigned long rate)
163{
164 if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate)
165 return (clk->ops->round_rate)(clk, rate);
166
167 return rate;
168}
169
170int clk_set_rate(struct clk *clk, unsigned long rate)
171{
172 int ret;
173
174 if (IS_ERR(clk))
175 return -EINVAL;
176
177 /* We do not default just do a clk->rate = rate as
178 * the clock may have been made this way by choice.
179 */
180
181 WARN_ON(clk->ops == NULL);
182 WARN_ON(clk->ops && clk->ops->set_rate == NULL);
183
184 if (clk->ops == NULL || clk->ops->set_rate == NULL)
185 return -EINVAL;
186
187 spin_lock(&clocks_lock);
188 ret = (clk->ops->set_rate)(clk, rate);
189 spin_unlock(&clocks_lock);
190
191 return ret;
192}
193
194struct clk *clk_get_parent(struct clk *clk)
195{
196 return clk->parent;
197}
198
199int clk_set_parent(struct clk *clk, struct clk *parent)
200{
201 int ret = 0;
202
203 if (IS_ERR(clk))
204 return -EINVAL;
205
206 spin_lock(&clocks_lock);
207
208 if (clk->ops && clk->ops->set_parent)
209 ret = (clk->ops->set_parent)(clk, parent);
210
211 spin_unlock(&clocks_lock);
212
213 return ret;
214}
215
216EXPORT_SYMBOL(clk_get);
217EXPORT_SYMBOL(clk_put);
218EXPORT_SYMBOL(clk_enable);
219EXPORT_SYMBOL(clk_disable);
220EXPORT_SYMBOL(clk_get_rate);
221EXPORT_SYMBOL(clk_round_rate);
222EXPORT_SYMBOL(clk_set_rate);
223EXPORT_SYMBOL(clk_get_parent);
224EXPORT_SYMBOL(clk_set_parent);
225
226/* base clocks */
227
228static int clk_default_setrate(struct clk *clk, unsigned long rate)
229{
230 clk->rate = rate;
231 return 0;
232}
233
234static struct clk_ops clk_ops_def_setrate = {
235 .set_rate = clk_default_setrate,
236};
237
238struct clk clk_xtal = {
239 .name = "xtal",
240 .id = -1,
241 .rate = 0,
242 .parent = NULL,
243 .ctrlbit = 0,
244};
245
246struct clk clk_ext = {
247 .name = "ext",
248 .id = -1,
249};
250
251struct clk clk_epll = {
252 .name = "epll",
253 .id = -1,
254};
255
256struct clk clk_mpll = {
257 .name = "mpll",
258 .id = -1,
259 .ops = &clk_ops_def_setrate,
260};
261
262struct clk clk_upll = {
263 .name = "upll",
264 .id = -1,
265 .parent = NULL,
266 .ctrlbit = 0,
267};
268
269struct clk clk_f = {
270 .name = "fclk",
271 .id = -1,
272 .rate = 0,
273 .parent = &clk_mpll,
274 .ctrlbit = 0,
275};
276
277struct clk clk_h = {
278 .name = "hclk",
279 .id = -1,
280 .rate = 0,
281 .parent = NULL,
282 .ctrlbit = 0,
283 .ops = &clk_ops_def_setrate,
284};
285
286struct clk clk_p = {
287 .name = "pclk",
288 .id = -1,
289 .rate = 0,
290 .parent = NULL,
291 .ctrlbit = 0,
292 .ops = &clk_ops_def_setrate,
293};
294
295struct clk clk_usb_bus = {
296 .name = "usb-bus",
297 .id = -1,
298 .rate = 0,
299 .parent = &clk_upll,
300};
301
302
303struct clk s3c24xx_uclk = {
304 .name = "uclk",
305 .id = -1,
306};
307
308/* initialise the clock system */
309
310int s3c24xx_register_clock(struct clk *clk)
311{
312 if (clk->enable == NULL)
313 clk->enable = clk_null_enable;
314
315 /* add to the list of available clocks */
316
317 /* Quick check to see if this clock has already been registered. */
318 BUG_ON(clk->list.prev != clk->list.next);
319
320 spin_lock(&clocks_lock);
321 list_add(&clk->list, &clocks);
322 spin_unlock(&clocks_lock);
323
324 return 0;
325}
326
327int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
328{
329 int fails = 0;
330
331 for (; nr_clks > 0; nr_clks--, clks++) {
332 if (s3c24xx_register_clock(*clks) < 0)
333 fails++;
334 }
335
336 return fails;
337}
338
339/* initalise all the clocks */
340
341int __init s3c24xx_register_baseclocks(unsigned long xtal)
342{
343 printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n");
344
345 clk_xtal.rate = xtal;
346
347 /* register our clocks */
348
349 if (s3c24xx_register_clock(&clk_xtal) < 0)
350 printk(KERN_ERR "failed to register master xtal\n");
351
352 if (s3c24xx_register_clock(&clk_mpll) < 0)
353 printk(KERN_ERR "failed to register mpll clock\n");
354
355 if (s3c24xx_register_clock(&clk_upll) < 0)
356 printk(KERN_ERR "failed to register upll clock\n");
357
358 if (s3c24xx_register_clock(&clk_f) < 0)
359 printk(KERN_ERR "failed to register cpu fclk\n");
360
361 if (s3c24xx_register_clock(&clk_h) < 0)
362 printk(KERN_ERR "failed to register cpu hclk\n");
363
364 if (s3c24xx_register_clock(&clk_p) < 0)
365 printk(KERN_ERR "failed to register cpu pclk\n");
366
367 return 0;
368}
369
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