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authorBen Dooks <ben-linux@fluff.org>2010-01-05 20:14:51 -0500
committerBen Dooks <ben-linux@fluff.org>2010-01-15 03:10:13 -0500
commit7162ba03729e0a47aaab44448ce2453f07a9664d (patch)
tree7f1d852cd36db6c39b2224411d986a4b9fec8390 /arch/arm/plat-s3c64xx
parent4f830db9629e413e7c5523085ab009b0de5ae6d0 (diff)
ARM: SAMSUNG: Move IRQ VIC timer handling out to common header files
Move the VIC based timer interrupt handling out of plat-s3c64xx and into plat-samsung to be re-used for other systems. This also reduces the code size as we now have a common init routine and use the irq_desc to store the interrupt number of the timer. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c64xx')
-rw-r--r--arch/arm/plat-s3c64xx/Kconfig1
-rw-r--r--arch/arm/plat-s3c64xx/irq.c90
2 files changed, 8 insertions, 83 deletions
diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig
index bec12242706b..02d716fb157a 100644
--- a/arch/arm/plat-s3c64xx/Kconfig
+++ b/arch/arm/plat-s3c64xx/Kconfig
@@ -14,6 +14,7 @@ config PLAT_S3C64XX
14 select NO_IOPORT 14 select NO_IOPORT
15 select ARCH_REQUIRE_GPIOLIB 15 select ARCH_REQUIRE_GPIOLIB
16 select SAMSUNG_CLKSRC 16 select SAMSUNG_CLKSRC
17 select SAMSUNG_IRQ_VIC_TIMER
17 select S3C_GPIO_TRACK 18 select S3C_GPIO_TRACK
18 select S3C_GPIO_PULL_UPDOWN 19 select S3C_GPIO_PULL_UPDOWN
19 select S3C_GPIO_CFG_S3C24XX 20 select S3C_GPIO_CFG_S3C24XX
diff --git a/arch/arm/plat-s3c64xx/irq.c b/arch/arm/plat-s3c64xx/irq.c
index 8dc5b6da9789..8b69bca05876 100644
--- a/arch/arm/plat-s3c64xx/irq.c
+++ b/arch/arm/plat-s3c64xx/irq.c
@@ -21,78 +21,10 @@
21#include <asm/hardware/vic.h> 21#include <asm/hardware/vic.h>
22 22
23#include <mach/map.h> 23#include <mach/map.h>
24#include <plat/irq-vic-timer.h>
24#include <plat/regs-serial.h> 25#include <plat/regs-serial.h>
25#include <plat/regs-timer.h>
26#include <plat/cpu.h> 26#include <plat/cpu.h>
27 27
28/* Timer interrupt handling */
29
30static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq)
31{
32 generic_handle_irq(sub_irq);
33}
34
35static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc)
36{
37 s3c_irq_demux_timer(irq, IRQ_TIMER0);
38}
39
40static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc)
41{
42 s3c_irq_demux_timer(irq, IRQ_TIMER1);
43}
44
45static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc)
46{
47 s3c_irq_demux_timer(irq, IRQ_TIMER2);
48}
49
50static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc)
51{
52 s3c_irq_demux_timer(irq, IRQ_TIMER3);
53}
54
55static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc)
56{
57 s3c_irq_demux_timer(irq, IRQ_TIMER4);
58}
59
60/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
61
62static void s3c_irq_timer_mask(unsigned int irq)
63{
64 u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
65
66 reg &= 0x1f; /* mask out pending interrupts */
67 reg &= ~(1 << (irq - IRQ_TIMER0));
68 __raw_writel(reg, S3C64XX_TINT_CSTAT);
69}
70
71static void s3c_irq_timer_unmask(unsigned int irq)
72{
73 u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
74
75 reg &= 0x1f; /* mask out pending interrupts */
76 reg |= 1 << (irq - IRQ_TIMER0);
77 __raw_writel(reg, S3C64XX_TINT_CSTAT);
78}
79
80static void s3c_irq_timer_ack(unsigned int irq)
81{
82 u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
83
84 reg &= 0x1f;
85 reg |= (1 << 5) << (irq - IRQ_TIMER0);
86 __raw_writel(reg, S3C64XX_TINT_CSTAT);
87}
88
89static struct irq_chip s3c_irq_timer = {
90 .name = "s3c-timer",
91 .mask = s3c_irq_timer_mask,
92 .unmask = s3c_irq_timer_unmask,
93 .ack = s3c_irq_timer_ack,
94};
95
96struct uart_irq { 28struct uart_irq {
97 void __iomem *regs; 29 void __iomem *regs;
98 unsigned int base_irq; 30 unsigned int base_irq;
@@ -227,7 +159,7 @@ static void __init s3c64xx_uart_irq(struct uart_irq *uirq)
227 159
228void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) 160void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
229{ 161{
230 int uart, irq; 162 int uart;
231 163
232 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); 164 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
233 165
@@ -237,20 +169,12 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
237 169
238 /* add the timer sub-irqs */ 170 /* add the timer sub-irqs */
239 171
240 set_irq_chained_handler(IRQ_TIMER0_VIC, s3c_irq_demux_timer0); 172 s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
241 set_irq_chained_handler(IRQ_TIMER1_VIC, s3c_irq_demux_timer1); 173 s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
242 set_irq_chained_handler(IRQ_TIMER2_VIC, s3c_irq_demux_timer2); 174 s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
243 set_irq_chained_handler(IRQ_TIMER3_VIC, s3c_irq_demux_timer3); 175 s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
244 set_irq_chained_handler(IRQ_TIMER4_VIC, s3c_irq_demux_timer4); 176 s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
245
246 for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) {
247 set_irq_chip(irq, &s3c_irq_timer);
248 set_irq_handler(irq, handle_level_irq);
249 set_irq_flags(irq, IRQF_VALID);
250 }
251 177
252 for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++) 178 for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++)
253 s3c64xx_uart_irq(&uart_irqs[uart]); 179 s3c64xx_uart_irq(&uart_irqs[uart]);
254} 180}
255
256