diff options
author | Ben Dooks <ben-linux@fluff.org> | 2008-10-31 12:14:50 -0400 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2008-12-15 18:41:50 -0500 |
commit | 26da1bfc567e10ca20cf2ffa97dcdcbd5112275b (patch) | |
tree | a03559884369312a9f5ede9ecd8fb615238e4af8 /arch/arm/plat-s3c64xx | |
parent | 4162d7e36334541e9cf5262cb6e1ba4f827eb700 (diff) |
[ARM] S3C64XX: GPIO definitions for BANKS N,O,P,Q
GPIO register and configuration definitions for GPIO
banks N, O, P and Q.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c64xx')
-rw-r--r-- | arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h | 54 | ||||
-rw-r--r-- | arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h | 70 | ||||
-rw-r--r-- | arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h | 69 | ||||
-rw-r--r-- | arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h | 46 |
4 files changed, 239 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h new file mode 100644 index 000000000000..569e76120881 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h | |||
@@ -0,0 +1,54 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * GPIO Bank N register and configuration definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00) | ||
16 | #define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04) | ||
17 | #define S3C64XX_GPNPUD (S3C64XX_GPN_BASE + 0x08) | ||
18 | |||
19 | #define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) | ||
20 | #define S3C64XX_GPN_INPUT(__gpio) (0x0 << ((__gpio) * 2)) | ||
21 | #define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) | ||
22 | |||
23 | #define S3C64XX_GPN0_EINT0 (0x02 << 0) | ||
24 | #define S3C64XX_GPN0_KP_ROW0 (0x03 << 0) | ||
25 | |||
26 | #define S3C64XX_GPN1_EINT1 (0x02 << 2) | ||
27 | #define S3C64XX_GPN1_KP_ROW1 (0x03 << 2) | ||
28 | |||
29 | #define S3C64XX_GPN2_EINT2 (0x02 << 4) | ||
30 | #define S3C64XX_GPN2_KP_ROW2 (0x03 << 4) | ||
31 | |||
32 | #define S3C64XX_GPN3_EINT3 (0x02 << 6) | ||
33 | #define S3C64XX_GPN3_KP_ROW3 (0x03 << 6) | ||
34 | |||
35 | #define S3C64XX_GPN4_EINT4 (0x02 << 8) | ||
36 | #define S3C64XX_GPN4_KP_ROW4 (0x03 << 8) | ||
37 | |||
38 | #define S3C64XX_GPN5_EINT5 (0x02 << 10) | ||
39 | #define S3C64XX_GPN5_KP_ROW5 (0x03 << 10) | ||
40 | |||
41 | #define S3C64XX_GPN6_EINT6 (0x02 << 12) | ||
42 | #define S3C64XX_GPN6_KP_ROW6 (0x03 << 12) | ||
43 | |||
44 | #define S3C64XX_GPN7_EINT7 (0x02 << 14) | ||
45 | #define S3C64XX_GPN7_KP_ROW7 (0x03 << 14) | ||
46 | |||
47 | #define S3C64XX_GPN8_EINT8 (0x02 << 16) | ||
48 | #define S3C64XX_GPN9_EINT9 (0x02 << 18) | ||
49 | #define S3C64XX_GPN10_EINT10 (0x02 << 20) | ||
50 | #define S3C64XX_GPN11_EINT11 (0x02 << 22) | ||
51 | #define S3C64XX_GPN12_EINT12 (0x02 << 24) | ||
52 | #define S3C64XX_GPN13_EINT13 (0x02 << 26) | ||
53 | #define S3C64XX_GPN14_EINT14 (0x02 << 28) | ||
54 | #define S3C64XX_GPN15_EINT15 (0x02 << 30) | ||
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h new file mode 100644 index 000000000000..b09e12954b57 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h | |||
@@ -0,0 +1,70 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * GPIO Bank O register and configuration definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define S3C64XX_GPOCON (S3C64XX_GPO_BASE + 0x00) | ||
16 | #define S3C64XX_GPODAT (S3C64XX_GPO_BASE + 0x04) | ||
17 | #define S3C64XX_GPOPUD (S3C64XX_GPO_BASE + 0x08) | ||
18 | #define S3C64XX_GPOCONSLP (S3C64XX_GPO_BASE + 0x0c) | ||
19 | #define S3C64XX_GPOPUDSLP (S3C64XX_GPO_BASE + 0x10) | ||
20 | |||
21 | #define S3C64XX_GPO_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) | ||
22 | #define S3C64XX_GPO_INPUT(__gpio) (0x0 << ((__gpio) * 2)) | ||
23 | #define S3C64XX_GPO_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) | ||
24 | |||
25 | #define S3C64XX_GPO0_MEM0_nCS2 (0x02 << 0) | ||
26 | #define S3C64XX_GPO0_EINT_G7_0 (0x03 << 0) | ||
27 | |||
28 | #define S3C64XX_GPO1_MEM0_nCS3 (0x02 << 2) | ||
29 | #define S3C64XX_GPO1_EINT_G7_1 (0x03 << 2) | ||
30 | |||
31 | #define S3C64XX_GPO2_MEM0_nCS4 (0x02 << 4) | ||
32 | #define S3C64XX_GPO2_EINT_G7_2 (0x03 << 4) | ||
33 | |||
34 | #define S3C64XX_GPO3_MEM0_nCS5 (0x02 << 6) | ||
35 | #define S3C64XX_GPO3_EINT_G7_3 (0x03 << 6) | ||
36 | |||
37 | #define S3C64XX_GPO4_EINT_G7_4 (0x03 << 8) | ||
38 | |||
39 | #define S3C64XX_GPO5_EINT_G7_5 (0x03 << 10) | ||
40 | |||
41 | #define S3C64XX_GPO6_MEM0_ADDR6 (0x02 << 12) | ||
42 | #define S3C64XX_GPO6_EINT_G7_6 (0x03 << 12) | ||
43 | |||
44 | #define S3C64XX_GPO7_MEM0_ADDR7 (0x02 << 14) | ||
45 | #define S3C64XX_GPO7_EINT_G7_7 (0x03 << 14) | ||
46 | |||
47 | #define S3C64XX_GPO8_MEM0_ADDR8 (0x02 << 16) | ||
48 | #define S3C64XX_GPO8_EINT_G7_8 (0x03 << 16) | ||
49 | |||
50 | #define S3C64XX_GPO9_MEM0_ADDR9 (0x02 << 18) | ||
51 | #define S3C64XX_GPO9_EINT_G7_9 (0x03 << 18) | ||
52 | |||
53 | #define S3C64XX_GPO10_MEM0_ADDR10 (0x02 << 20) | ||
54 | #define S3C64XX_GPO10_EINT_G7_10 (0x03 << 20) | ||
55 | |||
56 | #define S3C64XX_GPO11_MEM0_ADDR11 (0x02 << 22) | ||
57 | #define S3C64XX_GPO11_EINT_G7_11 (0x03 << 22) | ||
58 | |||
59 | #define S3C64XX_GPO12_MEM0_ADDR12 (0x02 << 24) | ||
60 | #define S3C64XX_GPO12_EINT_G7_12 (0x03 << 24) | ||
61 | |||
62 | #define S3C64XX_GPO13_MEM0_ADDR13 (0x02 << 26) | ||
63 | #define S3C64XX_GPO13_EINT_G7_13 (0x03 << 26) | ||
64 | |||
65 | #define S3C64XX_GPO14_MEM0_ADDR14 (0x02 << 28) | ||
66 | #define S3C64XX_GPO14_EINT_G7_14 (0x03 << 28) | ||
67 | |||
68 | #define S3C64XX_GPO15_MEM0_ADDR15 (0x02 << 30) | ||
69 | #define S3C64XX_GPO15_EINT_G7_15 (0x03 << 30) | ||
70 | |||
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h new file mode 100644 index 000000000000..92f00517926b --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h | |||
@@ -0,0 +1,69 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * GPIO Bank P register and configuration definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define S3C64XX_GPPCON (S3C64XX_GPP_BASE + 0x00) | ||
16 | #define S3C64XX_GPPDAT (S3C64XX_GPP_BASE + 0x04) | ||
17 | #define S3C64XX_GPPPUD (S3C64XX_GPP_BASE + 0x08) | ||
18 | #define S3C64XX_GPPCONSLP (S3C64XX_GPP_BASE + 0x0c) | ||
19 | #define S3C64XX_GPPPUDSLP (S3C64XX_GPP_BASE + 0x10) | ||
20 | |||
21 | #define S3C64XX_GPP_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) | ||
22 | #define S3C64XX_GPP_INPUT(__gpio) (0x0 << ((__gpio) * 2)) | ||
23 | #define S3C64XX_GPP_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) | ||
24 | |||
25 | #define S3C64XX_GPP0_MEM0_ADDRV (0x02 << 0) | ||
26 | #define S3C64XX_GPP0_EINT_G8_0 (0x03 << 0) | ||
27 | |||
28 | #define S3C64XX_GPP1_MEM0_SMCLK (0x02 << 2) | ||
29 | #define S3C64XX_GPP1_EINT_G8_1 (0x03 << 2) | ||
30 | |||
31 | #define S3C64XX_GPP2_MEM0_nWAIT (0x02 << 4) | ||
32 | #define S3C64XX_GPP2_EINT_G8_2 (0x03 << 4) | ||
33 | |||
34 | #define S3C64XX_GPP3_MEM0_RDY0_ALE (0x02 << 6) | ||
35 | #define S3C64XX_GPP3_EINT_G8_3 (0x03 << 6) | ||
36 | |||
37 | #define S3C64XX_GPP4_MEM0_RDY1_CLE (0x02 << 8) | ||
38 | #define S3C64XX_GPP4_EINT_G8_4 (0x03 << 8) | ||
39 | |||
40 | #define S3C64XX_GPP5_MEM0_INTsm0_FWE (0x02 << 10) | ||
41 | #define S3C64XX_GPP5_EINT_G8_5 (0x03 << 10) | ||
42 | |||
43 | #define S3C64XX_GPP6_MEM0_(null) (0x02 << 12) | ||
44 | #define S3C64XX_GPP6_EINT_G8_6 (0x03 << 12) | ||
45 | |||
46 | #define S3C64XX_GPP7_MEM0_INTsm1_FRE (0x02 << 14) | ||
47 | #define S3C64XX_GPP7_EINT_G8_7 (0x03 << 14) | ||
48 | |||
49 | #define S3C64XX_GPP8_MEM0_RPn_RnB (0x02 << 16) | ||
50 | #define S3C64XX_GPP8_EINT_G8_8 (0x03 << 16) | ||
51 | |||
52 | #define S3C64XX_GPP9_MEM0_ATA_RESET (0x02 << 18) | ||
53 | #define S3C64XX_GPP9_EINT_G8_9 (0x03 << 18) | ||
54 | |||
55 | #define S3C64XX_GPP10_MEM0_ATA_INPACK (0x02 << 20) | ||
56 | #define S3C64XX_GPP10_EINT_G8_10 (0x03 << 20) | ||
57 | |||
58 | #define S3C64XX_GPP11_MEM0_ATA_REG (0x02 << 22) | ||
59 | #define S3C64XX_GPP11_EINT_G8_11 (0x03 << 22) | ||
60 | |||
61 | #define S3C64XX_GPP12_MEM0_ATA_WE (0x02 << 24) | ||
62 | #define S3C64XX_GPP12_EINT_G8_12 (0x03 << 24) | ||
63 | |||
64 | #define S3C64XX_GPP13_MEM0_ATA_OE (0x02 << 26) | ||
65 | #define S3C64XX_GPP13_EINT_G8_13 (0x03 << 26) | ||
66 | |||
67 | #define S3C64XX_GPP14_MEM0_ATA_CD (0x02 << 28) | ||
68 | #define S3C64XX_GPP14_EINT_G8_14 (0x03 << 28) | ||
69 | |||
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h new file mode 100644 index 000000000000..565e60aaee47 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h | |||
@@ -0,0 +1,46 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * GPIO Bank Q register and configuration definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define S3C64XX_GPQCON (S3C64XX_GPQ_BASE + 0x00) | ||
16 | #define S3C64XX_GPQDAT (S3C64XX_GPQ_BASE + 0x04) | ||
17 | #define S3C64XX_GPQPUD (S3C64XX_GPQ_BASE + 0x08) | ||
18 | #define S3C64XX_GPQCONSLP (S3C64XX_GPQ_BASE + 0x0c) | ||
19 | #define S3C64XX_GPQPUDSLP (S3C64XX_GPQ_BASE + 0x10) | ||
20 | |||
21 | #define S3C64XX_GPQ_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) | ||
22 | #define S3C64XX_GPQ_INPUT(__gpio) (0x0 << ((__gpio) * 2)) | ||
23 | #define S3C64XX_GPQ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) | ||
24 | |||
25 | #define S3C64XX_GPQ0_MEM0_ADDR18_RAS (0x02 << 0) | ||
26 | #define S3C64XX_GPQ0_EINT_G9_0 (0x03 << 0) | ||
27 | |||
28 | #define S3C64XX_GPQ1_MEM0_ADDR19_CAS (0x02 << 2) | ||
29 | #define S3C64XX_GPQ1_EINT_G9_1 (0x03 << 2) | ||
30 | |||
31 | #define S3C64XX_GPQ2_EINT_G9_2 (0x03 << 4) | ||
32 | |||
33 | #define S3C64XX_GPQ3_EINT_G9_3 (0x03 << 6) | ||
34 | |||
35 | #define S3C64XX_GPQ4_EINT_G9_4 (0x03 << 8) | ||
36 | |||
37 | #define S3C64XX_GPQ5_EINT_G9_5 (0x03 << 10) | ||
38 | |||
39 | #define S3C64XX_GPQ6_EINT_G9_6 (0x03 << 12) | ||
40 | |||
41 | #define S3C64XX_GPQ7_MEM0_ADDR17_WENDMC (0x02 << 14) | ||
42 | #define S3C64XX_GPQ7_EINT_G9_7 (0x03 << 14) | ||
43 | |||
44 | #define S3C64XX_GPQ8_MEM0_ADDR16_APDMC (0x02 << 16) | ||
45 | #define S3C64XX_GPQ8_EINT_G9_8 (0x03 << 16) | ||
46 | |||