aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-s3c64xx/s3c6400-clock.c
diff options
context:
space:
mode:
authorBen Dooks <ben-linux@fluff.org>2009-11-29 20:31:32 -0500
committerBen Dooks <ben-linux@fluff.org>2010-01-15 03:10:08 -0500
commit8360493c4ae4c116339cd1cf4da100c3547f23af (patch)
tree69a53f5ab7e360f7528905cb88bcf563d33bfcce /arch/arm/plat-s3c64xx/s3c6400-clock.c
parentf9c4f1e4ddf40103dcf85e23d00230ab8ece2a89 (diff)
ARM: S3C64XX: Compress s3c6400-clock.c code
The individually named clocks are all static to the code and thus can be compressed into a single array and then the array can be referenced. This removes the need for a seperate array of pointers to clocks. Fix a minor problem of re-initialising the pointers in s3c6400_set_clksrc() as this is also called by the cpufreq code. Move these initialisations to the code that does the registration. Based on Harald Welte's original clock changes patch. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c64xx/s3c6400-clock.c')
-rw-r--r--arch/arm/plat-s3c64xx/s3c6400-clock.c334
1 files changed, 154 insertions, 180 deletions
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index aba08c7d312f..6fde910e414c 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -255,7 +255,6 @@ static struct clk_sources clkset_uhost = {
255 .nr_sources = ARRAY_SIZE(clkset_uhost_list), 255 .nr_sources = ARRAY_SIZE(clkset_uhost_list),
256}; 256};
257 257
258
259/* The peripheral clocks are all controlled via clocksource followed 258/* The peripheral clocks are all controlled via clocksource followed
260 * by an optional divider and gate stage. We currently roll this into 259 * by an optional divider and gate stage. We currently roll this into
261 * one clock which hides the intermediate clock from the mux. 260 * one clock which hides the intermediate clock from the mux.
@@ -354,105 +353,7 @@ static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk,
354 return rate; 353 return rate;
355} 354}
356 355
357static struct clksrc_clk clk_mmc0 = { 356/* clocks that feed other parts of the clock source tree */
358 .clk = {
359 .name = "mmc_bus",
360 .id = 0,
361 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
362 .enable = s3c64xx_sclk_ctrl,
363 },
364 .shift = S3C6400_CLKSRC_MMC0_SHIFT,
365 .mask = S3C6400_CLKSRC_MMC0_MASK,
366 .sources = &clkset_spi_mmc,
367 .divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT,
368 .reg_divider = S3C_CLK_DIV1,
369};
370
371static struct clksrc_clk clk_mmc1 = {
372 .clk = {
373 .name = "mmc_bus",
374 .id = 1,
375 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
376 .enable = s3c64xx_sclk_ctrl,
377 },
378 .shift = S3C6400_CLKSRC_MMC1_SHIFT,
379 .mask = S3C6400_CLKSRC_MMC1_MASK,
380 .sources = &clkset_spi_mmc,
381 .divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT,
382 .reg_divider = S3C_CLK_DIV1,
383};
384
385static struct clksrc_clk clk_mmc2 = {
386 .clk = {
387 .name = "mmc_bus",
388 .id = 2,
389 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
390 .enable = s3c64xx_sclk_ctrl,
391 },
392 .shift = S3C6400_CLKSRC_MMC2_SHIFT,
393 .mask = S3C6400_CLKSRC_MMC2_MASK,
394 .sources = &clkset_spi_mmc,
395 .divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT,
396 .reg_divider = S3C_CLK_DIV1,
397};
398
399static struct clksrc_clk clk_usbhost = {
400 .clk = {
401 .name = "usb-bus-host",
402 .id = -1,
403 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
404 .enable = s3c64xx_sclk_ctrl,
405 },
406 .shift = S3C6400_CLKSRC_UHOST_SHIFT,
407 .mask = S3C6400_CLKSRC_UHOST_MASK,
408 .sources = &clkset_uhost,
409 .divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT,
410 .reg_divider = S3C_CLK_DIV1,
411};
412
413static struct clksrc_clk clk_uart_uclk1 = {
414 .clk = {
415 .name = "uclk1",
416 .id = -1,
417 .ctrlbit = S3C_CLKCON_SCLK_UART,
418 .enable = s3c64xx_sclk_ctrl,
419 },
420 .shift = S3C6400_CLKSRC_UART_SHIFT,
421 .mask = S3C6400_CLKSRC_UART_MASK,
422 .sources = &clkset_uart,
423 .divider_shift = S3C6400_CLKDIV2_UART_SHIFT,
424 .reg_divider = S3C_CLK_DIV2,
425};
426
427/* Where does UCLK0 come from? */
428
429static struct clksrc_clk clk_spi0 = {
430 .clk = {
431 .name = "spi-bus",
432 .id = 0,
433 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
434 .enable = s3c64xx_sclk_ctrl,
435 },
436 .shift = S3C6400_CLKSRC_SPI0_SHIFT,
437 .mask = S3C6400_CLKSRC_SPI0_MASK,
438 .sources = &clkset_spi_mmc,
439 .divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT,
440 .reg_divider = S3C_CLK_DIV2,
441};
442
443static struct clksrc_clk clk_spi1 = {
444 .clk = {
445 .name = "spi-bus",
446 .id = 1,
447 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
448 .enable = s3c64xx_sclk_ctrl,
449 },
450 .shift = S3C6400_CLKSRC_SPI1_SHIFT,
451 .mask = S3C6400_CLKSRC_SPI1_MASK,
452 .sources = &clkset_spi_mmc,
453 .divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT,
454 .reg_divider = S3C_CLK_DIV2,
455};
456 357
457static struct clk clk_iis_cd0 = { 358static struct clk clk_iis_cd0 = {
458 .name = "iis_cdclk0", 359 .name = "iis_cdclk0",
@@ -482,20 +383,6 @@ static struct clk_sources clkset_audio0 = {
482 .nr_sources = ARRAY_SIZE(clkset_audio0_list), 383 .nr_sources = ARRAY_SIZE(clkset_audio0_list),
483}; 384};
484 385
485static struct clksrc_clk clk_audio0 = {
486 .clk = {
487 .name = "audio-bus",
488 .id = 0,
489 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
490 .enable = s3c64xx_sclk_ctrl,
491 },
492 .shift = S3C6400_CLKSRC_AUDIO0_SHIFT,
493 .mask = S3C6400_CLKSRC_AUDIO0_MASK,
494 .sources = &clkset_audio0,
495 .divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT,
496 .reg_divider = S3C_CLK_DIV2,
497};
498
499static struct clk *clkset_audio1_list[] = { 386static struct clk *clkset_audio1_list[] = {
500 [0] = &clk_mout_epll.clk, 387 [0] = &clk_mout_epll.clk,
501 [1] = &clk_dout_mpll, 388 [1] = &clk_dout_mpll,
@@ -509,34 +396,6 @@ static struct clk_sources clkset_audio1 = {
509 .nr_sources = ARRAY_SIZE(clkset_audio1_list), 396 .nr_sources = ARRAY_SIZE(clkset_audio1_list),
510}; 397};
511 398
512static struct clksrc_clk clk_audio1 = {
513 .clk = {
514 .name = "audio-bus",
515 .id = 1,
516 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
517 .enable = s3c64xx_sclk_ctrl,
518 },
519 .shift = S3C6400_CLKSRC_AUDIO1_SHIFT,
520 .mask = S3C6400_CLKSRC_AUDIO1_MASK,
521 .sources = &clkset_audio1,
522 .divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT,
523 .reg_divider = S3C_CLK_DIV2,
524};
525
526static struct clksrc_clk clk_irda = {
527 .clk = {
528 .name = "irda-bus",
529 .id = 0,
530 .ctrlbit = S3C_CLKCON_SCLK_IRDA,
531 .enable = s3c64xx_sclk_ctrl,
532 },
533 .shift = S3C6400_CLKSRC_IRDA_SHIFT,
534 .mask = S3C6400_CLKSRC_IRDA_MASK,
535 .sources = &clkset_irda,
536 .divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT,
537 .reg_divider = S3C_CLK_DIV2,
538};
539
540static struct clk *clkset_camif_list[] = { 399static struct clk *clkset_camif_list[] = {
541 &clk_h2, 400 &clk_h2,
542}; 401};
@@ -546,18 +405,141 @@ static struct clk_sources clkset_camif = {
546 .nr_sources = ARRAY_SIZE(clkset_camif_list), 405 .nr_sources = ARRAY_SIZE(clkset_camif_list),
547}; 406};
548 407
549static struct clksrc_clk clk_camif = { 408static struct clksrc_clk clksrcs[] = {
550 .clk = { 409 {
551 .name = "camera", 410 .clk = {
552 .id = -1, 411 .name = "mmc_bus",
553 .ctrlbit = S3C_CLKCON_SCLK_CAM, 412 .id = 0,
554 .enable = s3c64xx_sclk_ctrl, 413 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
414 .enable = s3c64xx_sclk_ctrl,
415 },
416 .shift = S3C6400_CLKSRC_MMC0_SHIFT,
417 .mask = S3C6400_CLKSRC_MMC0_MASK,
418 .sources = &clkset_spi_mmc,
419 .divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT,
420 .reg_divider = S3C_CLK_DIV1,
421 }, {
422 .clk = {
423 .name = "mmc_bus",
424 .id = 1,
425 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
426 .enable = s3c64xx_sclk_ctrl,
427 },
428 .shift = S3C6400_CLKSRC_MMC1_SHIFT,
429 .mask = S3C6400_CLKSRC_MMC1_MASK,
430 .sources = &clkset_spi_mmc,
431 .divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT,
432 .reg_divider = S3C_CLK_DIV1,
433 }, {
434 .clk = {
435 .name = "mmc_bus",
436 .id = 2,
437 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
438 .enable = s3c64xx_sclk_ctrl,
439 },
440 .shift = S3C6400_CLKSRC_MMC2_SHIFT,
441 .mask = S3C6400_CLKSRC_MMC2_MASK,
442 .sources = &clkset_spi_mmc,
443 .divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT,
444 .reg_divider = S3C_CLK_DIV1,
445 }, {
446 .clk = {
447 .name = "usb-bus-host",
448 .id = -1,
449 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
450 .enable = s3c64xx_sclk_ctrl,
451 },
452 .shift = S3C6400_CLKSRC_UHOST_SHIFT,
453 .mask = S3C6400_CLKSRC_UHOST_MASK,
454 .sources = &clkset_uhost,
455 .divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT,
456 .reg_divider = S3C_CLK_DIV1,
457 }, {
458 .clk = {
459 .name = "uclk1",
460 .id = -1,
461 .ctrlbit = S3C_CLKCON_SCLK_UART,
462 .enable = s3c64xx_sclk_ctrl,
463 },
464 .shift = S3C6400_CLKSRC_UART_SHIFT,
465 .mask = S3C6400_CLKSRC_UART_MASK,
466 .sources = &clkset_uart,
467 .divider_shift = S3C6400_CLKDIV2_UART_SHIFT,
468 .reg_divider = S3C_CLK_DIV2,
469 }, {
470/* Where does UCLK0 come from? */
471 .clk = {
472 .name = "spi-bus",
473 .id = 0,
474 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
475 .enable = s3c64xx_sclk_ctrl,
476 },
477 .shift = S3C6400_CLKSRC_SPI0_SHIFT,
478 .mask = S3C6400_CLKSRC_SPI0_MASK,
479 .sources = &clkset_spi_mmc,
480 .divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT,
481 .reg_divider = S3C_CLK_DIV2,
482 }, {
483 .clk = {
484 .name = "spi-bus",
485 .id = 1,
486 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
487 .enable = s3c64xx_sclk_ctrl,
488 },
489 .shift = S3C6400_CLKSRC_SPI1_SHIFT,
490 .mask = S3C6400_CLKSRC_SPI1_MASK,
491 .sources = &clkset_spi_mmc,
492 .divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT,
493 .reg_divider = S3C_CLK_DIV2,
494 }, {
495 .clk = {
496 .name = "audio-bus",
497 .id = 0,
498 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
499 .enable = s3c64xx_sclk_ctrl,
500 },
501 .shift = S3C6400_CLKSRC_AUDIO0_SHIFT,
502 .mask = S3C6400_CLKSRC_AUDIO0_MASK,
503 .sources = &clkset_audio0,
504 .divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT,
505 .reg_divider = S3C_CLK_DIV2,
506 }, {
507 .clk = {
508 .name = "audio-bus",
509 .id = 1,
510 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
511 .enable = s3c64xx_sclk_ctrl,
512 },
513 .shift = S3C6400_CLKSRC_AUDIO1_SHIFT,
514 .mask = S3C6400_CLKSRC_AUDIO1_MASK,
515 .sources = &clkset_audio1,
516 .divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT,
517 .reg_divider = S3C_CLK_DIV2,
518 }, {
519 .clk = {
520 .name = "irda-bus",
521 .id = 0,
522 .ctrlbit = S3C_CLKCON_SCLK_IRDA,
523 .enable = s3c64xx_sclk_ctrl,
524 },
525 .shift = S3C6400_CLKSRC_IRDA_SHIFT,
526 .mask = S3C6400_CLKSRC_IRDA_MASK,
527 .sources = &clkset_irda,
528 .divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT,
529 .reg_divider = S3C_CLK_DIV2,
530 }, {
531 .clk = {
532 .name = "camera",
533 .id = -1,
534 .ctrlbit = S3C_CLKCON_SCLK_CAM,
535 .enable = s3c64xx_sclk_ctrl,
536 },
537 .shift = 0,
538 .mask = 0,
539 .sources = &clkset_camif,
540 .divider_shift = S3C6400_CLKDIV0_CAM_SHIFT,
541 .reg_divider = S3C_CLK_DIV0,
555 }, 542 },
556 .shift = 0,
557 .mask = 0,
558 .sources = &clkset_camif,
559 .divider_shift = S3C6400_CLKDIV0_CAM_SHIFT,
560 .reg_divider = S3C_CLK_DIV0,
561}; 543};
562 544
563/* Clock initialisation code */ 545/* Clock initialisation code */
@@ -566,17 +548,6 @@ static struct clksrc_clk *init_parents[] = {
566 &clk_mout_apll, 548 &clk_mout_apll,
567 &clk_mout_epll, 549 &clk_mout_epll,
568 &clk_mout_mpll, 550 &clk_mout_mpll,
569 &clk_mmc0,
570 &clk_mmc1,
571 &clk_mmc2,
572 &clk_usbhost,
573 &clk_uart_uclk1,
574 &clk_spi0,
575 &clk_spi1,
576 &clk_audio0,
577 &clk_audio1,
578 &clk_irda,
579 &clk_camif,
580}; 551};
581 552
582static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk) 553static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
@@ -593,11 +564,6 @@ static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
593 return; 564 return;
594 } 565 }
595 566
596 clk->clk.get_rate = s3c64xx_getrate_clksrc;
597 clk->clk.set_rate = s3c64xx_setrate_clksrc;
598 clk->clk.set_parent = s3c64xx_setparent_clksrc;
599 clk->clk.round_rate = s3c64xx_roundrate_clksrc;
600
601 clk->clk.parent = srcs->sources[clksrc]; 567 clk->clk.parent = srcs->sources[clksrc];
602 568
603 printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", 569 printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
@@ -664,6 +630,9 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
664 630
665 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) 631 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
666 s3c6400_set_clksrc(init_parents[ptr]); 632 s3c6400_set_clksrc(init_parents[ptr]);
633
634 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
635 s3c6400_set_clksrc(&clksrcs[ptr]);
667} 636}
668 637
669static struct clk *clks[] __initdata = { 638static struct clk *clks[] __initdata = {
@@ -674,17 +643,6 @@ static struct clk *clks[] __initdata = {
674 &clk_mout_epll.clk, 643 &clk_mout_epll.clk,
675 &clk_mout_mpll.clk, 644 &clk_mout_mpll.clk,
676 &clk_dout_mpll, 645 &clk_dout_mpll,
677 &clk_mmc0.clk,
678 &clk_mmc1.clk,
679 &clk_mmc2.clk,
680 &clk_usbhost.clk,
681 &clk_uart_uclk1.clk,
682 &clk_spi0.clk,
683 &clk_spi1.clk,
684 &clk_audio0.clk,
685 &clk_audio1.clk,
686 &clk_irda.clk,
687 &clk_camif.clk,
688 &clk_arm, 646 &clk_arm,
689}; 647};
690 648
@@ -716,4 +674,20 @@ void __init s3c6400_register_clocks(unsigned armclk_divlimit)
716 clkp->name, ret); 674 clkp->name, ret);
717 } 675 }
718 } 676 }
677
678 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) {
679 clkp = &clksrcs[ptr].clk;
680
681 /* all clksrc clocks have these */
682 clkp->get_rate = s3c64xx_getrate_clksrc;
683 clkp->set_rate = s3c64xx_setrate_clksrc;
684 clkp->set_parent = s3c64xx_setparent_clksrc;
685 clkp->round_rate = s3c64xx_roundrate_clksrc;
686
687 ret = s3c24xx_register_clock(clkp);
688 if (ret < 0) {
689 printk(KERN_ERR "Failed to register clock %s (%d)\n",
690 clkp->name, ret);
691 }
692 }
719} 693}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-11 11:00:40 -0500