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authorBen Dooks <ben-linux@fluff.org>2010-01-05 21:18:44 -0500
committerBen Dooks <ben-linux@fluff.org>2010-01-15 03:10:14 -0500
commit51022cf6591ae2945960d034788bdeffa28cde13 (patch)
tree30f85bb15cdd66384018c31cb42c4ba986a68da4 /arch/arm/plat-s3c64xx/irq.c
parent7162ba03729e0a47aaab44448ce2453f07a9664d (diff)
ARM: SAMSUNG: Move IRQ UART handling for newer devices to plat-samsung
Move the handling for the UART interrupts out of the s3c64xx specific code and into plat-samsung so that it can be used by all implementations that need it. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c64xx/irq.c')
-rw-r--r--arch/arm/plat-s3c64xx/irq.c117
1 files changed, 3 insertions, 114 deletions
diff --git a/arch/arm/plat-s3c64xx/irq.c b/arch/arm/plat-s3c64xx/irq.c
index 8b69bca05876..b98451e8ee24 100644
--- a/arch/arm/plat-s3c64xx/irq.c
+++ b/arch/arm/plat-s3c64xx/irq.c
@@ -22,19 +22,10 @@
22 22
23#include <mach/map.h> 23#include <mach/map.h>
24#include <plat/irq-vic-timer.h> 24#include <plat/irq-vic-timer.h>
25#include <plat/regs-serial.h> 25#include <plat/irq-uart.h>
26#include <plat/cpu.h> 26#include <plat/cpu.h>
27 27
28struct uart_irq { 28static struct s3c_uart_irq uart_irqs[] = {
29 void __iomem *regs;
30 unsigned int base_irq;
31 unsigned int parent_irq;
32};
33
34/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
35 * are consecutive when looking up the interrupt in the demux routines.
36 */
37static struct uart_irq uart_irqs[] = {
38 [0] = { 29 [0] = {
39 .regs = S3C_VA_UART0, 30 .regs = S3C_VA_UART0,
40 .base_irq = IRQ_S3CUART_BASE0, 31 .base_irq = IRQ_S3CUART_BASE0,
@@ -57,110 +48,9 @@ static struct uart_irq uart_irqs[] = {
57 }, 48 },
58}; 49};
59 50
60static inline void __iomem *s3c_irq_uart_base(unsigned int irq)
61{
62 struct uart_irq *uirq = get_irq_chip_data(irq);
63 return uirq->regs;
64}
65
66static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
67{
68 return irq & 3;
69}
70
71/* UART interrupt registers, not worth adding to seperate include header */
72
73static void s3c_irq_uart_mask(unsigned int irq)
74{
75 void __iomem *regs = s3c_irq_uart_base(irq);
76 unsigned int bit = s3c_irq_uart_bit(irq);
77 u32 reg;
78
79 reg = __raw_readl(regs + S3C64XX_UINTM);
80 reg |= (1 << bit);
81 __raw_writel(reg, regs + S3C64XX_UINTM);
82}
83
84static void s3c_irq_uart_maskack(unsigned int irq)
85{
86 void __iomem *regs = s3c_irq_uart_base(irq);
87 unsigned int bit = s3c_irq_uart_bit(irq);
88 u32 reg;
89
90 reg = __raw_readl(regs + S3C64XX_UINTM);
91 reg |= (1 << bit);
92 __raw_writel(reg, regs + S3C64XX_UINTM);
93 __raw_writel(1 << bit, regs + S3C64XX_UINTP);
94}
95
96static void s3c_irq_uart_unmask(unsigned int irq)
97{
98 void __iomem *regs = s3c_irq_uart_base(irq);
99 unsigned int bit = s3c_irq_uart_bit(irq);
100 u32 reg;
101
102 reg = __raw_readl(regs + S3C64XX_UINTM);
103 reg &= ~(1 << bit);
104 __raw_writel(reg, regs + S3C64XX_UINTM);
105}
106
107static void s3c_irq_uart_ack(unsigned int irq)
108{
109 void __iomem *regs = s3c_irq_uart_base(irq);
110 unsigned int bit = s3c_irq_uart_bit(irq);
111
112 __raw_writel(1 << bit, regs + S3C64XX_UINTP);
113}
114
115static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
116{
117 struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0];
118 u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
119 int base = uirq->base_irq;
120
121 if (pend & (1 << 0))
122 generic_handle_irq(base);
123 if (pend & (1 << 1))
124 generic_handle_irq(base + 1);
125 if (pend & (1 << 2))
126 generic_handle_irq(base + 2);
127 if (pend & (1 << 3))
128 generic_handle_irq(base + 3);
129}
130
131static struct irq_chip s3c_irq_uart = {
132 .name = "s3c-uart",
133 .mask = s3c_irq_uart_mask,
134 .unmask = s3c_irq_uart_unmask,
135 .mask_ack = s3c_irq_uart_maskack,
136 .ack = s3c_irq_uart_ack,
137};
138
139static void __init s3c64xx_uart_irq(struct uart_irq *uirq)
140{
141 void __iomem *reg_base = uirq->regs;
142 unsigned int irq;
143 int offs;
144
145 /* mask all interrupts at the start. */
146 __raw_writel(0xf, reg_base + S3C64XX_UINTM);
147
148 for (offs = 0; offs < 3; offs++) {
149 irq = uirq->base_irq + offs;
150
151 set_irq_chip(irq, &s3c_irq_uart);
152 set_irq_chip_data(irq, uirq);
153 set_irq_handler(irq, handle_level_irq);
154 set_irq_flags(irq, IRQF_VALID);
155 }
156
157 set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
158}
159 51
160void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) 52void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
161{ 53{
162 int uart;
163
164 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); 54 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
165 55
166 /* initialise the pair of VICs */ 56 /* initialise the pair of VICs */
@@ -175,6 +65,5 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
175 s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3); 65 s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
176 s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4); 66 s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
177 67
178 for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++) 68 s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
179 s3c64xx_uart_irq(&uart_irqs[uart]);
180} 69}