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authorBen Dooks <ben-linux@fluff.org>2008-10-21 09:07:08 -0400
committerBen Dooks <ben-linux@fluff.org>2008-12-15 18:15:46 -0500
commit80789e79150b34e45a630e2f4f1b04d82c449c19 (patch)
tree2fa0a12db09eafd00568e9c940933d58815c4721 /arch/arm/plat-s3c64xx/irq-eint.c
parent94df868b884d673c294e39a11acdfebf2bfcd67b (diff)
[ARM] S3C64XX: Add IRQ_EINT support
Add the necessary code to support IRQ_EINT(x) on the S3C64XX series of CPUs. Note, since there is no GPIO configuration support in the kernel, the irq set_type method does not configure the relevant pin to interrupt. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c64xx/irq-eint.c')
-rw-r--r--arch/arm/plat-s3c64xx/irq-eint.c202
1 files changed, 202 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c
new file mode 100644
index 000000000000..8c01f9cd94b6
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/irq-eint.c
@@ -0,0 +1,202 @@
1/* arch/arm/plat-s3c64xx/irq-eint.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX - Interrupt handling for IRQ_EINT(x)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <linux/io.h>
19
20#include <asm/hardware/vic.h>
21
22#include <plat/regs-irqtype.h>
23
24#include <mach/map.h>
25#include <plat/cpu.h>
26
27/* GPIO is 0x7F008xxx, */
28#define S3C64XX_GPIOREG(x) (S3C64XX_VA_GPIO + (x))
29
30#define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900)
31#define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904)
32#define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910)
33#define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914)
34#define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918)
35#define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C)
36
37#define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920)
38#define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924)
39
40
41#define eint_offset(irq) ((irq) - IRQ_EINT(0))
42#define eint_irq_to_bit(irq) (1 << eint_offset(irq))
43
44static inline void s3c_irq_eint_mask(unsigned int irq)
45{
46 u32 mask;
47
48 mask = __raw_readl(S3C64XX_EINT0MASK);
49 mask |= eint_irq_to_bit(irq);
50 __raw_writel(mask, S3C64XX_EINT0MASK);
51}
52
53static void s3c_irq_eint_unmask(unsigned int irq)
54{
55 u32 mask;
56
57 mask = __raw_readl(S3C64XX_EINT0MASK);
58 mask |= eint_irq_to_bit(irq);
59 __raw_writel(mask, S3C64XX_EINT0MASK);
60}
61
62static inline void s3c_irq_eint_ack(unsigned int irq)
63{
64 __raw_writel(eint_irq_to_bit(irq), S3C64XX_EINT0PEND);
65}
66
67static void s3c_irq_eint_maskack(unsigned int irq)
68{
69 /* compiler should in-line these */
70 s3c_irq_eint_mask(irq);
71 s3c_irq_eint_ack(irq);
72}
73
74static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
75{
76 int offs = eint_offset(irq);
77 int shift;
78 u32 ctrl, mask;
79 u32 newvalue = 0;
80 void __iomem *reg;
81
82 if (offs > 27)
83 return -EINVAL;
84
85 if (offs > 15)
86 reg = S3C64XX_EINT0CON0;
87 else
88 reg = S3C64XX_EINT0CON1;
89
90 switch (type) {
91 case IRQ_TYPE_NONE:
92 printk(KERN_WARNING "No edge setting!\n");
93 break;
94
95 case IRQ_TYPE_EDGE_RISING:
96 newvalue = S3C2410_EXTINT_RISEEDGE;
97 break;
98
99 case IRQ_TYPE_EDGE_FALLING:
100 newvalue = S3C2410_EXTINT_FALLEDGE;
101 break;
102
103 case IRQ_TYPE_EDGE_BOTH:
104 newvalue = S3C2410_EXTINT_BOTHEDGE;
105 break;
106
107 case IRQ_TYPE_LEVEL_LOW:
108 newvalue = S3C2410_EXTINT_LOWLEV;
109 break;
110
111 case IRQ_TYPE_LEVEL_HIGH:
112 newvalue = S3C2410_EXTINT_HILEV;
113 break;
114
115 default:
116 printk(KERN_ERR "No such irq type %d", type);
117 return -1;
118 }
119
120 shift = (offs / 2) * 4;
121 mask = 0x7 << shift;
122
123 ctrl = __raw_readl(reg);
124 ctrl &= ~mask;
125 ctrl |= newvalue << shift;
126 __raw_writel(ctrl, reg);
127
128 return 0;
129}
130
131static struct irq_chip s3c_irq_eint = {
132 .name = "s3c-eint",
133 .mask = s3c_irq_eint_mask,
134 .unmask = s3c_irq_eint_unmask,
135 .mask_ack = s3c_irq_eint_maskack,
136 .ack = s3c_irq_eint_ack,
137 .set_type = s3c_irq_eint_set_type,
138};
139
140/* s3c_irq_demux_eint
141 *
142 * This function demuxes the IRQ from the group0 external interrupts,
143 * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
144 * the specific handlers s3c_irq_demux_eintX_Y.
145 */
146static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
147{
148 u32 status = __raw_readl(S3C64XX_EINT0PEND);
149 u32 mask = __raw_readl(S3C64XX_EINT0MASK);
150 unsigned int irq;
151
152 status &= ~mask;
153 status >>= start;
154 status &= (1 << (end - start + 1)) - 1;
155
156 for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
157 if (status & 1)
158 generic_handle_irq(irq);
159
160 status >>= 1;
161 }
162}
163
164static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
165{
166 s3c_irq_demux_eint(0, 3);
167}
168
169static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
170{
171 s3c_irq_demux_eint(4, 11);
172}
173
174static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
175{
176 s3c_irq_demux_eint(12, 19);
177}
178
179static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
180{
181 s3c_irq_demux_eint(20, 27);
182}
183
184int __init s3c64xx_init_irq_eint(void)
185{
186 int irq;
187
188 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
189 set_irq_chip(irq, &s3c_irq_eint);
190 set_irq_handler(irq, handle_level_irq);
191 set_irq_flags(irq, IRQF_VALID);
192 }
193
194 set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
195 set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
196 set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
197 set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
198
199 return 0;
200}
201
202arch_initcall(s3c64xx_init_irq_eint);