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authorBen Dooks <ben-linux@fluff.org>2008-12-11 19:24:15 -0500
committerBen Dooks <ben-linux@fluff.org>2009-03-10 12:29:11 -0400
commit333053733f52fa8c8e44c621b7b17fe5df215d4a (patch)
tree71bd5a2608f6139322614e50124a4cfbcea89825 /arch/arm/plat-s3c64xx/irq-eint.c
parent5b3d515fcfe93d012107b9bd4895e2d913cbe8c3 (diff)
[ARM] S3C64XX: Add EINT group regs and move IRQ_EINT to regs-gpio.h
Add definitions for the EINT group registers and move the EINT IRQ register definitions out of arch/arm/plat-s3c64xx/irq-eint.c so that they are available for re-use with PM and the other code. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c64xx/irq-eint.c')
-rw-r--r--arch/arm/plat-s3c64xx/irq-eint.c14
1 files changed, 0 insertions, 14 deletions
diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c
index cf524826c93a..47e5155bb13e 100644
--- a/arch/arm/plat-s3c64xx/irq-eint.c
+++ b/arch/arm/plat-s3c64xx/irq-eint.c
@@ -27,20 +27,6 @@
27#include <mach/map.h> 27#include <mach/map.h>
28#include <plat/cpu.h> 28#include <plat/cpu.h>
29 29
30/* GPIO is 0x7F008xxx, */
31#define S3C64XX_GPIOREG(x) (S3C64XX_VA_GPIO + (x))
32
33#define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900)
34#define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904)
35#define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910)
36#define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914)
37#define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918)
38#define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C)
39
40#define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920)
41#define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924)
42
43
44#define eint_offset(irq) ((irq) - IRQ_EINT(0)) 30#define eint_offset(irq) ((irq) - IRQ_EINT(0))
45#define eint_irq_to_bit(irq) (1 << eint_offset(irq)) 31#define eint_irq_to_bit(irq) (1 << eint_offset(irq))
46 32