Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (417 commits)
  MAINTAINERS: EB110ATX is not ebsa110
  MAINTAINERS: update Eric Miao's email address and status
  fb: add support of LCD display controller on pxa168/910 (base layer)
  [ARM] 5552/1: ep93xx get_uart_rate(): use EP93XX_SYSCON_PWRCNT and EP93XX_SYSCON_PWRCN
  [ARM] pxa/sharpsl_pm: zaurus needs generic pxa suspend/resume routines
  [ARM] 5544/1: Trust PrimeCell resource sizes
  [ARM] pxa/sharpsl_pm: cleanup of gpio-related code.
  [ARM] pxa/sharpsl_pm: drop set_irq_type calls
  [ARM] pxa/sharpsl_pm: merge pxa-specific code into generic one
  [ARM] pxa/sharpsl_pm: merge the two sharpsl_pm.c since it's now pxa specific
  [ARM] sa1100: remove unused collie_pm.c
  [ARM] pxa: fix the conflicting non-static declarations of global_gpios[]
  [ARM] 5550/1: Add default configure file for w90p910 platform
  [ARM] 5549/1: Add clock api for w90p910 platform.
  [ARM] 5548/1: Add gpio api for w90p910 platform
  [ARM] 5551/1: Add multi-function pin api for w90p910 platform.
  [ARM] Make ARM_VIC_NR depend on ARM_VIC
  [ARM] 5546/1: ARM PL022 SSP/SPI driver v3
  ARM: OMAP4: SMP: Update defconfig for OMAP4430
  ARM: OMAP4: SMP: Enable SMP support for OMAP4430
  ...

1 files changed, 19 insertions, 0 deletions

diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c
index ad1b9682c9c3..0bc2fa1dfc40 100644
--- a/arch/arm/plat-s3c64xx/clock.c
+++ b/arch/arm/plat-s3c64xx/clock.c
@@ -27,6 +27,12 @@
 #include <plat/devs.h>
 #include <plat/clock.h>
 
+struct clk clk_h2 = {
+        .name           = "hclk2",
+        .id             = -1,
+        .rate           = 0,
+};
+
 struct clk clk_27m = {
         .name           = "clk_27m",
         .id             = -1,
@@ -152,6 +158,18 @@ static struct clk init_clocks_disable[] = {
                 .parent         = &clk_48m,
                 .enable         = s3c64xx_sclk_ctrl,
                 .ctrlbit        = S3C_CLKCON_SCLK_MMC2_48,
+        }, {
+                .name           = "dma0",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_DMA0,
+        }, {
+                .name           = "dma1",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_DMA1,
         },
 };
 
@@ -246,6 +264,7 @@ static struct clk *clks[] __initdata = {
         &clk_epll,
         &clk_27m,
         &clk_48m,
+        &clk_h2,
 };
 
 void __init s3c64xx_register_clocks(void)