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authorBen Dooks <ben-linux@fluff.org>2009-08-14 10:23:45 -0400
committerBen Dooks <ben-linux@fluff.org>2009-08-14 10:23:45 -0400
commit215ed3236a17b748cf75a2c23f50028c95302a42 (patch)
treea1fa16573704a4a1bb646365f5d4c6cd3bb321f9 /arch/arm/plat-s3c24xx
parent0fbdd270078a3e3ce537a2fb6ffc8a9b2427500c (diff)
parente6d197a6954c8a9ff85727c31ca61fc1da78628a (diff)
Merge branch 'next-s3c24xx-cpufreq' into next-s3c
Diffstat (limited to 'arch/arm/plat-s3c24xx')
-rw-r--r--arch/arm/plat-s3c24xx/Kconfig59
-rw-r--r--arch/arm/plat-s3c24xx/Makefile10
-rw-r--r--arch/arm/plat-s3c24xx/cpu-freq-debugfs.c199
-rw-r--r--arch/arm/plat-s3c24xx/cpu-freq.c716
-rw-r--r--arch/arm/plat-s3c24xx/cpu.c2
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h282
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/s3c2410.h1
-rw-r--r--arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c64
-rw-r--r--arch/arm/plat-s3c24xx/s3c2410-iotiming.c477
-rw-r--r--arch/arm/plat-s3c24xx/s3c2412-iotiming.c285
-rw-r--r--arch/arm/plat-s3c24xx/s3c2440-cpufreq.c311
-rw-r--r--arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c97
-rw-r--r--arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c127
13 files changed, 2629 insertions, 1 deletions
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index aaae456018b5..2f9145683596 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -34,6 +34,40 @@ config CPU_S3C244X
34 help 34 help
35 Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems. 35 Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems.
36 36
37config S3C2440_CPUFREQ
38 bool "S3C2440/S3C2442 CPU Frequency scaling support"
39 depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442)
40 select S3C2410_CPUFREQ_UTILS
41 default y
42 help
43 CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs.
44
45config S3C2440_XTAL_12000000
46 bool
47 help
48 Indicate that the build needs to support 12MHz system
49 crystal.
50
51config S3C2440_XTAL_16934400
52 bool
53 help
54 Indicate that the build needs to support 16.9344MHz system
55 crystal.
56
57config S3C2440_PLL_12000000
58 bool
59 depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000
60 default y if CPU_FREQ_S3C24XX_PLL
61 help
62 PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals.
63
64config S3C2440_PLL_16934400
65 bool
66 depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400
67 default y if CPU_FREQ_S3C24XX_PLL
68 help
69 PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals.
70
37config S3C24XX_PWM 71config S3C24XX_PWM
38 bool "PWM device support" 72 bool "PWM device support"
39 select HAVE_PWM 73 select HAVE_PWM
@@ -113,6 +147,31 @@ config S3C24XX_SPI_BUS1_GPD8_GPD9_GPD10
113 147
114# common code for s3c24xx based machines, such as the SMDKs. 148# common code for s3c24xx based machines, such as the SMDKs.
115 149
150# cpu frequency items common between s3c2410 and s3c2440/s3c2442
151
152config S3C2410_IOTIMING
153 bool
154 depends on CPU_FREQ_S3C24XX
155 help
156 Internal node to select io timing code that is common to the s3c2410
157 and s3c2440/s3c2442 cpu frequency support.
158
159config S3C2410_CPUFREQ_UTILS
160 bool
161 depends on CPU_FREQ_S3C24XX
162 help
163 Internal node to select timing code that is common to the s3c2410
164 and s3c2440/s3c244 cpu frequency support.
165
166# cpu frequency support common to s3c2412, s3c2413 and s3c2442
167
168config S3C2412_IOTIMING
169 bool
170 depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443)
171 help
172 Intel node to select io timing code that is common to the s3c2412
173 and the s3c2443.
174
116config MACH_SMDK 175config MACH_SMDK
117 bool 176 bool
118 help 177 help
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index 59416796fb1d..651315c95ec4 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -20,11 +20,18 @@ obj-y += gpiolib.o
20obj-y += clock.o 20obj-y += clock.o
21obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o 21obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o
22 22
23obj-$(CONFIG_CPU_FREQ_S3C24XX) += cpu-freq.o
24obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpu-freq-debugfs.o
25
23# Architecture dependant builds 26# Architecture dependant builds
24 27
25obj-$(CONFIG_CPU_S3C244X) += s3c244x.o 28obj-$(CONFIG_CPU_S3C244X) += s3c244x.o
26obj-$(CONFIG_CPU_S3C244X) += s3c244x-irq.o 29obj-$(CONFIG_CPU_S3C244X) += s3c244x-irq.o
27obj-$(CONFIG_CPU_S3C244X) += s3c244x-clock.o 30obj-$(CONFIG_CPU_S3C244X) += s3c244x-clock.o
31obj-$(CONFIG_S3C2440_CPUFREQ) += s3c2440-cpufreq.o
32obj-$(CONFIG_S3C2440_PLL_12000000) += s3c2440-pll-12000000.o
33obj-$(CONFIG_S3C2440_PLL_16934400) += s3c2440-pll-16934400.o
34
28obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o 35obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
29obj-$(CONFIG_PM) += pm.o 36obj-$(CONFIG_PM) += pm.o
30obj-$(CONFIG_PM) += irq-pm.o 37obj-$(CONFIG_PM) += irq-pm.o
@@ -33,6 +40,9 @@ obj-$(CONFIG_S3C24XX_PWM) += pwm.o
33obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o 40obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o
34obj-$(CONFIG_S3C2410_DMA) += dma.o 41obj-$(CONFIG_S3C2410_DMA) += dma.o
35obj-$(CONFIG_S3C24XX_ADC) += adc.o 42obj-$(CONFIG_S3C24XX_ADC) += adc.o
43obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o
44obj-$(CONFIG_S3C2412_IOTIMING) += s3c2412-iotiming.o
45obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o
36 46
37# device specific setup and/or initialisation 47# device specific setup and/or initialisation
38obj-$(CONFIG_ARCH_S3C2410) += setup-i2c.o 48obj-$(CONFIG_ARCH_S3C2410) += setup-i2c.o
diff --git a/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c b/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c
new file mode 100644
index 000000000000..a9276667c2fb
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c
@@ -0,0 +1,199 @@
1/* linux/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c
2 *
3 * Copyright (c) 2009 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C24XX CPU Frequency scaling - debugfs status support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/ioport.h>
18#include <linux/cpufreq.h>
19#include <linux/debugfs.h>
20#include <linux/seq_file.h>
21#include <linux/err.h>
22
23#include <plat/cpu-freq-core.h>
24
25static struct dentry *dbgfs_root;
26static struct dentry *dbgfs_file_io;
27static struct dentry *dbgfs_file_info;
28static struct dentry *dbgfs_file_board;
29
30#define print_ns(x) ((x) / 10), ((x) % 10)
31
32static void show_max(struct seq_file *seq, struct s3c_freq *f)
33{
34 seq_printf(seq, "MAX: F=%lu, H=%lu, P=%lu, A=%lu\n",
35 f->fclk, f->hclk, f->pclk, f->armclk);
36}
37
38static int board_show(struct seq_file *seq, void *p)
39{
40 struct s3c_cpufreq_config *cfg;
41 struct s3c_cpufreq_board *brd;
42
43 cfg = s3c_cpufreq_getconfig();
44 if (!cfg) {
45 seq_printf(seq, "no configuration registered\n");
46 return 0;
47 }
48
49 brd = cfg->board;
50 if (!brd) {
51 seq_printf(seq, "no board definition set?\n");
52 return 0;
53 }
54
55 seq_printf(seq, "SDRAM refresh %u ns\n", brd->refresh);
56 seq_printf(seq, "auto_io=%u\n", brd->auto_io);
57 seq_printf(seq, "need_io=%u\n", brd->need_io);
58
59 show_max(seq, &brd->max);
60
61
62 return 0;
63}
64
65static int fops_board_open(struct inode *inode, struct file *file)
66{
67 return single_open(file, board_show, NULL);
68}
69
70static const struct file_operations fops_board = {
71 .open = fops_board_open,
72 .read = seq_read,
73 .llseek = seq_lseek,
74 .release = single_release,
75 .owner = THIS_MODULE,
76};
77
78static int info_show(struct seq_file *seq, void *p)
79{
80 struct s3c_cpufreq_config *cfg;
81
82 cfg = s3c_cpufreq_getconfig();
83 if (!cfg) {
84 seq_printf(seq, "no configuration registered\n");
85 return 0;
86 }
87
88 seq_printf(seq, " FCLK %ld Hz\n", cfg->freq.fclk);
89 seq_printf(seq, " HCLK %ld Hz (%lu.%lu ns)\n",
90 cfg->freq.hclk, print_ns(cfg->freq.hclk_tns));
91 seq_printf(seq, " PCLK %ld Hz\n", cfg->freq.hclk);
92 seq_printf(seq, "ARMCLK %ld Hz\n", cfg->freq.armclk);
93 seq_printf(seq, "\n");
94
95 show_max(seq, &cfg->max);
96
97 seq_printf(seq, "Divisors: P=%d, H=%d, A=%d, dvs=%s\n",
98 cfg->divs.h_divisor, cfg->divs.p_divisor,
99 cfg->divs.arm_divisor, cfg->divs.dvs ? "on" : "off");
100 seq_printf(seq, "\n");
101
102 seq_printf(seq, "lock_pll=%u\n", cfg->lock_pll);
103
104 return 0;
105}
106
107static int fops_info_open(struct inode *inode, struct file *file)
108{
109 return single_open(file, info_show, NULL);
110}
111
112static const struct file_operations fops_info = {
113 .open = fops_info_open,
114 .read = seq_read,
115 .llseek = seq_lseek,
116 .release = single_release,
117 .owner = THIS_MODULE,
118};
119
120static int io_show(struct seq_file *seq, void *p)
121{
122 void (*show_bank)(struct seq_file *, struct s3c_cpufreq_config *, union s3c_iobank *);
123 struct s3c_cpufreq_config *cfg;
124 struct s3c_iotimings *iot;
125 union s3c_iobank *iob;
126 int bank;
127
128 cfg = s3c_cpufreq_getconfig();
129 if (!cfg) {
130 seq_printf(seq, "no configuration registered\n");
131 return 0;
132 }
133
134 show_bank = cfg->info->debug_io_show;
135 if (!show_bank) {
136 seq_printf(seq, "no code to show bank timing\n");
137 return 0;
138 }
139
140 iot = s3c_cpufreq_getiotimings();
141 if (!iot) {
142 seq_printf(seq, "no io timings registered\n");
143 return 0;
144 }
145
146 seq_printf(seq, "hclk period is %lu.%lu ns\n", print_ns(cfg->freq.hclk_tns));
147
148 for (bank = 0; bank < MAX_BANKS; bank++) {
149 iob = &iot->bank[bank];
150
151 seq_printf(seq, "bank %d: ", bank);
152
153 if (!iob->io_2410) {
154 seq_printf(seq, "nothing set\n");
155 continue;
156 }
157
158 show_bank(seq, cfg, iob);
159 }
160
161 return 0;
162}
163
164static int fops_io_open(struct inode *inode, struct file *file)
165{
166 return single_open(file, io_show, NULL);
167}
168
169static const struct file_operations fops_io = {
170 .open = fops_io_open,
171 .read = seq_read,
172 .llseek = seq_lseek,
173 .release = single_release,
174 .owner = THIS_MODULE,
175};
176
177
178static int __init s3c_freq_debugfs_init(void)
179{
180 dbgfs_root = debugfs_create_dir("s3c-cpufreq", NULL);
181 if (IS_ERR(dbgfs_root)) {
182 printk(KERN_ERR "%s: error creating debugfs root\n", __func__);
183 return PTR_ERR(dbgfs_root);
184 }
185
186 dbgfs_file_io = debugfs_create_file("io-timing", S_IRUGO, dbgfs_root,
187 NULL, &fops_io);
188
189 dbgfs_file_info = debugfs_create_file("info", S_IRUGO, dbgfs_root,
190 NULL, &fops_info);
191
192 dbgfs_file_board = debugfs_create_file("board", S_IRUGO, dbgfs_root,
193 NULL, &fops_board);
194
195 return 0;
196}
197
198late_initcall(s3c_freq_debugfs_init);
199
diff --git a/arch/arm/plat-s3c24xx/cpu-freq.c b/arch/arm/plat-s3c24xx/cpu-freq.c
new file mode 100644
index 000000000000..4f1b789a1173
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/cpu-freq.c
@@ -0,0 +1,716 @@
1/* linux/arch/arm/plat-s3c24xx/cpu-freq.c
2 *
3 * Copyright (c) 2006,2007,2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C24XX CPU Frequency scaling
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/ioport.h>
18#include <linux/cpufreq.h>
19#include <linux/cpu.h>
20#include <linux/clk.h>
21#include <linux/err.h>
22#include <linux/io.h>
23#include <linux/sysdev.h>
24#include <linux/kobject.h>
25#include <linux/sysfs.h>
26
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29
30#include <plat/cpu.h>
31#include <plat/clock.h>
32#include <plat/cpu-freq-core.h>
33
34#include <mach/regs-clock.h>
35
36/* note, cpufreq support deals in kHz, no Hz */
37
38static struct cpufreq_driver s3c24xx_driver;
39static struct s3c_cpufreq_config cpu_cur;
40static struct s3c_iotimings s3c24xx_iotiming;
41static struct cpufreq_frequency_table *pll_reg;
42static unsigned int last_target = ~0;
43static unsigned int ftab_size;
44static struct cpufreq_frequency_table *ftab;
45
46static struct clk *_clk_mpll;
47static struct clk *_clk_xtal;
48static struct clk *clk_fclk;
49static struct clk *clk_hclk;
50static struct clk *clk_pclk;
51static struct clk *clk_arm;
52
53#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS
54struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void)
55{
56 return &cpu_cur;
57}
58
59struct s3c_iotimings *s3c_cpufreq_getiotimings(void)
60{
61 return &s3c24xx_iotiming;
62}
63#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUGFS */
64
65static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg)
66{
67 unsigned long fclk, pclk, hclk, armclk;
68
69 cfg->freq.fclk = fclk = clk_get_rate(clk_fclk);
70 cfg->freq.hclk = hclk = clk_get_rate(clk_hclk);
71 cfg->freq.pclk = pclk = clk_get_rate(clk_pclk);
72 cfg->freq.armclk = armclk = clk_get_rate(clk_arm);
73
74 cfg->pll.index = __raw_readl(S3C2410_MPLLCON);
75 cfg->pll.frequency = fclk;
76
77 cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
78
79 cfg->divs.h_divisor = fclk / hclk;
80 cfg->divs.p_divisor = fclk / pclk;
81}
82
83static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config *cfg)
84{
85 unsigned long pll = cfg->pll.frequency;
86
87 cfg->freq.fclk = pll;
88 cfg->freq.hclk = pll / cfg->divs.h_divisor;
89 cfg->freq.pclk = pll / cfg->divs.p_divisor;
90
91 /* convert hclk into 10ths of nanoseconds for io calcs */
92 cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
93}
94
95static inline int closer(unsigned int target, unsigned int n, unsigned int c)
96{
97 int diff_cur = abs(target - c);
98 int diff_new = abs(target - n);
99
100 return (diff_new < diff_cur);
101}
102
103static void s3c_cpufreq_show(const char *pfx,
104 struct s3c_cpufreq_config *cfg)
105{
106 s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n",
107 pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk,
108 cfg->freq.hclk, cfg->divs.h_divisor,
109 cfg->freq.pclk, cfg->divs.p_divisor);
110}
111
112/* functions to wrapper the driver info calls to do the cpu specific work */
113
114static void s3c_cpufreq_setio(struct s3c_cpufreq_config *cfg)
115{
116 if (cfg->info->set_iotiming)
117 (cfg->info->set_iotiming)(cfg, &s3c24xx_iotiming);
118}
119
120static int s3c_cpufreq_calcio(struct s3c_cpufreq_config *cfg)
121{
122 if (cfg->info->calc_iotiming)
123 return (cfg->info->calc_iotiming)(cfg, &s3c24xx_iotiming);
124
125 return 0;
126}
127
128static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
129{
130 (cfg->info->set_refresh)(cfg);
131}
132
133static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
134{
135 (cfg->info->set_divs)(cfg);
136}
137
138static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
139{
140 return (cfg->info->calc_divs)(cfg);
141}
142
143static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg)
144{
145 (cfg->info->set_fvco)(cfg);
146}
147
148static inline void s3c_cpufreq_resume_clocks(void)
149{
150 cpu_cur.info->resume_clocks();
151}
152
153static inline void s3c_cpufreq_updateclk(struct clk *clk,
154 unsigned int freq)
155{
156 clk_set_rate(clk, freq);
157}
158
159static int s3c_cpufreq_settarget(struct cpufreq_policy *policy,
160 unsigned int target_freq,
161 struct cpufreq_frequency_table *pll)
162{
163 struct s3c_cpufreq_freqs freqs;
164 struct s3c_cpufreq_config cpu_new;
165 unsigned long flags;
166
167 cpu_new = cpu_cur; /* copy new from current */
168
169 s3c_cpufreq_show("cur", &cpu_cur);
170
171 /* TODO - check for DMA currently outstanding */
172
173 cpu_new.pll = pll ? *pll : cpu_cur.pll;
174
175 if (pll)
176 freqs.pll_changing = 1;
177
178 /* update our frequencies */
179
180 cpu_new.freq.armclk = target_freq;
181 cpu_new.freq.fclk = cpu_new.pll.frequency;
182
183 if (s3c_cpufreq_calcdivs(&cpu_new) < 0) {
184 printk(KERN_ERR "no divisors for %d\n", target_freq);
185 goto err_notpossible;
186 }
187
188 s3c_freq_dbg("%s: got divs\n", __func__);
189
190 s3c_cpufreq_calc(&cpu_new);
191
192 s3c_freq_dbg("%s: calculated frequencies for new\n", __func__);
193
194 if (cpu_new.freq.hclk != cpu_cur.freq.hclk) {
195 if (s3c_cpufreq_calcio(&cpu_new) < 0) {
196 printk(KERN_ERR "%s: no IO timings\n", __func__);
197 goto err_notpossible;
198 }
199 }
200
201 s3c_cpufreq_show("new", &cpu_new);
202
203 /* setup our cpufreq parameters */
204
205 freqs.old = cpu_cur.freq;
206 freqs.new = cpu_new.freq;
207
208 freqs.freqs.cpu = 0;
209 freqs.freqs.old = cpu_cur.freq.armclk / 1000;
210 freqs.freqs.new = cpu_new.freq.armclk / 1000;
211
212 /* update f/h/p clock settings before we issue the change
213 * notification, so that drivers do not need to do anything
214 * special if they want to recalculate on CPUFREQ_PRECHANGE. */
215
216 s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency);
217 s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk);
218 s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk);
219 s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk);
220
221 /* start the frequency change */
222
223 if (policy)
224 cpufreq_notify_transition(&freqs.freqs, CPUFREQ_PRECHANGE);
225
226 /* If hclk is staying the same, then we do not need to
227 * re-write the IO or the refresh timings whilst we are changing
228 * speed. */
229
230 local_irq_save(flags);
231
232 /* is our memory clock slowing down? */
233 if (cpu_new.freq.hclk < cpu_cur.freq.hclk) {
234 s3c_cpufreq_setrefresh(&cpu_new);
235 s3c_cpufreq_setio(&cpu_new);
236 }
237
238 if (cpu_new.freq.fclk == cpu_cur.freq.fclk) {
239 /* not changing PLL, just set the divisors */
240
241 s3c_cpufreq_setdivs(&cpu_new);
242 } else {
243 if (cpu_new.freq.fclk < cpu_cur.freq.fclk) {
244 /* slow the cpu down, then set divisors */
245
246 s3c_cpufreq_setfvco(&cpu_new);
247 s3c_cpufreq_setdivs(&cpu_new);
248 } else {
249 /* set the divisors, then speed up */
250
251 s3c_cpufreq_setdivs(&cpu_new);
252 s3c_cpufreq_setfvco(&cpu_new);
253 }
254 }
255
256 /* did our memory clock speed up */
257 if (cpu_new.freq.hclk > cpu_cur.freq.hclk) {
258 s3c_cpufreq_setrefresh(&cpu_new);
259 s3c_cpufreq_setio(&cpu_new);
260 }
261
262 /* update our current settings */
263 cpu_cur = cpu_new;
264
265 local_irq_restore(flags);
266
267 /* notify everyone we've done this */
268 if (policy)
269 cpufreq_notify_transition(&freqs.freqs, CPUFREQ_POSTCHANGE);
270
271 s3c_freq_dbg("%s: finished\n", __func__);
272 return 0;
273
274 err_notpossible:
275 printk(KERN_ERR "no compatible settings for %d\n", target_freq);
276 return -EINVAL;
277}
278
279/* s3c_cpufreq_target
280 *
281 * called by the cpufreq core to adjust the frequency that the CPU
282 * is currently running at.
283 */
284
285static int s3c_cpufreq_target(struct cpufreq_policy *policy,
286 unsigned int target_freq,
287 unsigned int relation)
288{
289 struct cpufreq_frequency_table *pll;
290 unsigned int index;
291
292 /* avoid repeated calls which cause a needless amout of duplicated
293 * logging output (and CPU time as the calculation process is
294 * done) */
295 if (target_freq == last_target)
296 return 0;
297
298 last_target = target_freq;
299
300 s3c_freq_dbg("%s: policy %p, target %u, relation %u\n",
301 __func__, policy, target_freq, relation);
302
303 if (ftab) {
304 if (cpufreq_frequency_table_target(policy, ftab,
305 target_freq, relation,
306 &index)) {
307 s3c_freq_dbg("%s: table failed\n", __func__);
308 return -EINVAL;
309 }
310
311 s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__,
312 target_freq, index, ftab[index].frequency);
313 target_freq = ftab[index].frequency;
314 }
315
316 target_freq *= 1000; /* convert target to Hz */
317
318 /* find the settings for our new frequency */
319
320 if (!pll_reg || cpu_cur.lock_pll) {
321 /* either we've not got any PLL values, or we've locked
322 * to the current one. */
323 pll = NULL;
324 } else {
325 struct cpufreq_policy tmp_policy;
326 int ret;
327
328 /* we keep the cpu pll table in Hz, to ensure we get an
329 * accurate value for the PLL output. */
330
331 tmp_policy.min = policy->min * 1000;
332 tmp_policy.max = policy->max * 1000;
333 tmp_policy.cpu = policy->cpu;
334
335 /* cpufreq_frequency_table_target uses a pointer to 'index'
336 * which is the number of the table entry, not the value of
337 * the table entry's index field. */
338
339 ret = cpufreq_frequency_table_target(&tmp_policy, pll_reg,
340 target_freq, relation,
341 &index);
342
343 if (ret < 0) {
344 printk(KERN_ERR "%s: no PLL available\n", __func__);
345 goto err_notpossible;
346 }
347
348 pll = pll_reg + index;
349
350 s3c_freq_dbg("%s: target %u => %u\n",
351 __func__, target_freq, pll->frequency);
352
353 target_freq = pll->frequency;
354 }
355
356 return s3c_cpufreq_settarget(policy, target_freq, pll);
357
358 err_notpossible:
359 printk(KERN_ERR "no compatible settings for %d\n", target_freq);
360 return -EINVAL;
361}
362
363static unsigned int s3c_cpufreq_get(unsigned int cpu)
364{
365 return clk_get_rate(clk_arm) / 1000;
366}
367
368struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name)
369{
370 struct clk *clk;
371
372 clk = clk_get(dev, name);
373 if (IS_ERR(clk))
374 printk(KERN_ERR "cpufreq: failed to get clock '%s'\n", name);
375
376 return clk;
377}
378
379static int s3c_cpufreq_init(struct cpufreq_policy *policy)
380{
381 printk(KERN_INFO "%s: initialising policy %p\n", __func__, policy);
382
383 if (policy->cpu != 0)
384 return -EINVAL;
385
386 policy->cur = s3c_cpufreq_get(0);
387 policy->min = policy->cpuinfo.min_freq = 0;
388 policy->max = policy->cpuinfo.max_freq = cpu_cur.info->max.fclk / 1000;
389 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
390
391 /* feed the latency information from the cpu driver */
392 policy->cpuinfo.transition_latency = cpu_cur.info->latency;
393
394 if (ftab)
395 cpufreq_frequency_table_cpuinfo(policy, ftab);
396
397 return 0;
398}
399
400static __init int s3c_cpufreq_initclks(void)
401{
402 _clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll");
403 _clk_xtal = s3c_cpufreq_clk_get(NULL, "xtal");
404 clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk");
405 clk_hclk = s3c_cpufreq_clk_get(NULL, "hclk");
406 clk_pclk = s3c_cpufreq_clk_get(NULL, "pclk");
407 clk_arm = s3c_cpufreq_clk_get(NULL, "armclk");
408
409 if (IS_ERR(clk_fclk) || IS_ERR(clk_hclk) || IS_ERR(clk_pclk) ||
410 IS_ERR(_clk_mpll) || IS_ERR(clk_arm) || IS_ERR(_clk_xtal)) {
411 printk(KERN_ERR "%s: could not get clock(s)\n", __func__);
412 return -ENOENT;
413 }
414
415 printk(KERN_INFO "%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n", __func__,
416 clk_get_rate(clk_fclk) / 1000,
417 clk_get_rate(clk_hclk) / 1000,
418 clk_get_rate(clk_pclk) / 1000,
419 clk_get_rate(clk_arm) / 1000);
420
421 return 0;
422}
423
424static int s3c_cpufreq_verify(struct cpufreq_policy *policy)
425{
426 if (policy->cpu != 0)
427 return -EINVAL;
428
429 return 0;
430}
431
432#ifdef CONFIG_PM
433static struct cpufreq_frequency_table suspend_pll;
434static unsigned int suspend_freq;
435
436static int s3c_cpufreq_suspend(struct cpufreq_policy *policy, pm_message_t pmsg)
437{
438 suspend_pll.frequency = clk_get_rate(_clk_mpll);
439 suspend_pll.index = __raw_readl(S3C2410_MPLLCON);
440 suspend_freq = s3c_cpufreq_get(0) * 1000;
441
442 return 0;
443}
444
445static int s3c_cpufreq_resume(struct cpufreq_policy *policy)
446{
447 int ret;
448
449 s3c_freq_dbg("%s: resuming with policy %p\n", __func__, policy);
450
451 last_target = ~0; /* invalidate last_target setting */
452
453 /* first, find out what speed we resumed at. */
454 s3c_cpufreq_resume_clocks();
455
456 /* whilst we will be called later on, we try and re-set the
457 * cpu frequencies as soon as possible so that we do not end
458 * up resuming devices and then immediatley having to re-set
459 * a number of settings once these devices have restarted.
460 *
461 * as a note, it is expected devices are not used until they
462 * have been un-suspended and at that time they should have
463 * used the updated clock settings.
464 */
465
466 ret = s3c_cpufreq_settarget(NULL, suspend_freq, &suspend_pll);
467 if (ret) {
468 printk(KERN_ERR "%s: failed to reset pll/freq\n", __func__);
469 return ret;
470 }
471
472 return 0;
473}
474#else
475#define s3c_cpufreq_resume NULL
476#define s3c_cpufreq_suspend NULL
477#endif
478
479static struct cpufreq_driver s3c24xx_driver = {
480 .flags = CPUFREQ_STICKY,
481 .verify = s3c_cpufreq_verify,
482 .target = s3c_cpufreq_target,
483 .get = s3c_cpufreq_get,
484 .init = s3c_cpufreq_init,
485 .suspend = s3c_cpufreq_suspend,
486 .resume = s3c_cpufreq_resume,
487 .name = "s3c24xx",
488};
489
490
491int __init s3c_cpufreq_register(struct s3c_cpufreq_info *info)
492{
493 if (!info || !info->name) {
494 printk(KERN_ERR "%s: failed to pass valid information\n",
495 __func__);
496 return -EINVAL;
497 }
498
499 printk(KERN_INFO "S3C24XX CPU Frequency driver, %s cpu support\n",
500 info->name);
501
502 /* check our driver info has valid data */
503
504 BUG_ON(info->set_refresh == NULL);
505 BUG_ON(info->set_divs == NULL);
506 BUG_ON(info->calc_divs == NULL);
507
508 /* info->set_fvco is optional, depending on whether there
509 * is a need to set the clock code. */
510
511 cpu_cur.info = info;
512
513 /* Note, driver registering should probably update locktime */
514
515 return 0;
516}
517
518int __init s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
519{
520 struct s3c_cpufreq_board *ours;
521
522 if (!board) {
523 printk(KERN_INFO "%s: no board data\n", __func__);
524 return -EINVAL;
525 }
526
527 /* Copy the board information so that each board can make this
528 * initdata. */
529
530 ours = kzalloc(sizeof(struct s3c_cpufreq_board), GFP_KERNEL);
531 if (ours == NULL) {
532 printk(KERN_ERR "%s: no memory\n", __func__);
533 return -ENOMEM;
534 }
535
536 *ours = *board;
537 cpu_cur.board = ours;
538
539 return 0;
540}
541
542int __init s3c_cpufreq_auto_io(void)
543{
544 int ret;
545
546 if (!cpu_cur.info->get_iotiming) {
547 printk(KERN_ERR "%s: get_iotiming undefined\n", __func__);
548 return -ENOENT;
549 }
550
551 printk(KERN_INFO "%s: working out IO settings\n", __func__);
552
553 ret = (cpu_cur.info->get_iotiming)(&cpu_cur, &s3c24xx_iotiming);
554 if (ret)
555 printk(KERN_ERR "%s: failed to get timings\n", __func__);
556
557 return ret;
558}
559
560/* if one or is zero, then return the other, otherwise return the min */
561#define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b))
562
563/**
564 * s3c_cpufreq_freq_min - find the minimum settings for the given freq.
565 * @dst: The destination structure
566 * @a: One argument.
567 * @b: The other argument.
568 *
569 * Create a minimum of each frequency entry in the 'struct s3c_freq',
570 * unless the entry is zero when it is ignored and the non-zero argument
571 * used.
572 */
573static void s3c_cpufreq_freq_min(struct s3c_freq *dst,
574 struct s3c_freq *a, struct s3c_freq *b)
575{
576 dst->fclk = do_min(a->fclk, b->fclk);
577 dst->hclk = do_min(a->hclk, b->hclk);
578 dst->pclk = do_min(a->pclk, b->pclk);
579 dst->armclk = do_min(a->armclk, b->armclk);
580}
581
582static inline u32 calc_locktime(u32 freq, u32 time_us)
583{
584 u32 result;
585
586 result = freq * time_us;
587 result = DIV_ROUND_UP(result, 1000 * 1000);
588
589 return result;
590}
591
592static void s3c_cpufreq_update_loctkime(void)
593{
594 unsigned int bits = cpu_cur.info->locktime_bits;
595 u32 rate = (u32)clk_get_rate(_clk_xtal);
596 u32 val;
597
598 if (bits == 0) {
599 WARN_ON(1);
600 return;
601 }
602
603 val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits;
604 val |= calc_locktime(rate, cpu_cur.info->locktime_m);
605
606 printk(KERN_INFO "%s: new locktime is 0x%08x\n", __func__, val);
607 __raw_writel(val, S3C2410_LOCKTIME);
608}
609
610static int s3c_cpufreq_build_freq(void)
611{
612 int size, ret;
613
614 if (!cpu_cur.info->calc_freqtable)
615 return -EINVAL;
616
617 kfree(ftab);
618 ftab = NULL;
619
620 size = cpu_cur.info->calc_freqtable(&cpu_cur, NULL, 0);
621 size++;
622
623 ftab = kmalloc(sizeof(struct cpufreq_frequency_table) * size, GFP_KERNEL);
624 if (!ftab) {
625 printk(KERN_ERR "%s: no memory for tables\n", __func__);
626 return -ENOMEM;
627 }
628
629 ftab_size = size;
630
631 ret = cpu_cur.info->calc_freqtable(&cpu_cur, ftab, size);
632 s3c_cpufreq_addfreq(ftab, ret, size, CPUFREQ_TABLE_END);
633
634 return 0;
635}
636
637static int __init s3c_cpufreq_initcall(void)
638{
639 int ret = 0;
640
641 if (cpu_cur.info && cpu_cur.board) {
642 ret = s3c_cpufreq_initclks();
643 if (ret)
644 goto out;
645
646 /* get current settings */
647 s3c_cpufreq_getcur(&cpu_cur);
648 s3c_cpufreq_show("cur", &cpu_cur);
649
650 if (cpu_cur.board->auto_io) {
651 ret = s3c_cpufreq_auto_io();
652 if (ret) {
653 printk(KERN_ERR "%s: failed to get io timing\n",
654 __func__);
655 goto out;
656 }
657 }
658
659 if (cpu_cur.board->need_io && !cpu_cur.info->set_iotiming) {
660 printk(KERN_ERR "%s: no IO support registered\n",
661 __func__);
662 ret = -EINVAL;
663 goto out;
664 }
665
666 if (!cpu_cur.info->need_pll)
667 cpu_cur.lock_pll = 1;
668
669 s3c_cpufreq_update_loctkime();
670
671 s3c_cpufreq_freq_min(&cpu_cur.max, &cpu_cur.board->max,
672 &cpu_cur.info->max);
673
674 if (cpu_cur.info->calc_freqtable)
675 s3c_cpufreq_build_freq();
676
677 ret = cpufreq_register_driver(&s3c24xx_driver);
678 }
679
680 out:
681 return ret;
682}
683
684late_initcall(s3c_cpufreq_initcall);
685
686/**
687 * s3c_plltab_register - register CPU PLL table.
688 * @plls: The list of PLL entries.
689 * @plls_no: The size of the PLL entries @plls.
690 *
691 * Register the given set of PLLs with the system.
692 */
693int __init s3c_plltab_register(struct cpufreq_frequency_table *plls,
694 unsigned int plls_no)
695{
696 struct cpufreq_frequency_table *vals;
697 unsigned int size;
698
699 size = sizeof(struct cpufreq_frequency_table) * (plls_no + 1);
700
701 vals = kmalloc(size, GFP_KERNEL);
702 if (vals) {
703 memcpy(vals, plls, size);
704 pll_reg = vals;
705
706 /* write a terminating entry, we don't store it in the
707 * table that is stored in the kernel */
708 vals += plls_no;
709 vals->frequency = CPUFREQ_TABLE_END;
710
711 printk(KERN_INFO "cpufreq: %d PLL entries\n", plls_no);
712 } else
713 printk(KERN_ERR "cpufreq: no memory for PLL tables\n");
714
715 return vals ? 0 : -ENOMEM;
716}
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 1932b7e0da15..5447e60f3936 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -81,7 +81,7 @@ static struct cpu_table cpu_ids[] __initdata = {
81 .map_io = s3c2410_map_io, 81 .map_io = s3c2410_map_io,
82 .init_clocks = s3c2410_init_clocks, 82 .init_clocks = s3c2410_init_clocks,
83 .init_uarts = s3c2410_init_uarts, 83 .init_uarts = s3c2410_init_uarts,
84 .init = s3c2410_init, 84 .init = s3c2410a_init,
85 .name = name_s3c2410a 85 .name = name_s3c2410a
86 }, 86 },
87 { 87 {
diff --git a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h
new file mode 100644
index 000000000000..efeb025affc7
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h
@@ -0,0 +1,282 @@
1/* arch/arm/plat-s3c/include/plat/cpu-freq.h
2 *
3 * Copyright (c) 2006,2007,2009 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C CPU frequency scaling support - core support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <plat/cpu-freq.h>
15
16struct seq_file;
17
18#define MAX_BANKS (8)
19#define S3C2412_MAX_IO (8)
20
21/**
22 * struct s3c2410_iobank_timing - IO bank timings for S3C2410 style timings
23 * @bankcon: The cached version of settings in this structure.
24 * @tacp:
25 * @tacs: Time from address valid to nCS asserted.
26 * @tcos: Time from nCS asserted to nOE or nWE asserted.
27 * @tacc: Time that nOE or nWE is asserted.
28 * @tcoh: Time nCS is held after nOE or nWE are released.
29 * @tcah: Time address is held for after
30 * @nwait_en: Whether nWAIT is enabled for this bank.
31 *
32 * This structure represents the IO timings for a S3C2410 style IO bank
33 * used by the CPU frequency support if it needs to change the settings
34 * of the IO.
35 */
36struct s3c2410_iobank_timing {
37 unsigned long bankcon;
38 unsigned int tacp;
39 unsigned int tacs;
40 unsigned int tcos;
41 unsigned int tacc;
42 unsigned int tcoh; /* nCS hold afrer nOE/nWE */
43 unsigned int tcah; /* Address hold after nCS */
44 unsigned char nwait_en; /* nWait enabled for bank. */
45};
46
47/**
48 * struct s3c2412_iobank_timing - io timings for PL092 (S3C2412) style IO
49 * @idcy: The idle cycle time between transactions.
50 * @wstrd: nCS release to end of read cycle.
51 * @wstwr: nCS release to end of write cycle.
52 * @wstoen: nCS assertion to nOE assertion time.
53 * @wstwen: nCS assertion to nWE assertion time.
54 * @wstbrd: Burst ready delay.
55 * @smbidcyr: Register cache for smbidcyr value.
56 * @smbwstrd: Register cache for smbwstrd value.
57 * @smbwstwr: Register cache for smbwstwr value.
58 * @smbwstoen: Register cache for smbwstoen value.
59 * @smbwstwen: Register cache for smbwstwen value.
60 * @smbwstbrd: Register cache for smbwstbrd value.
61 *
62 * Timing information for a IO bank on an S3C2412 or similar system which
63 * uses a PL093 block.
64 */
65struct s3c2412_iobank_timing {
66 unsigned int idcy;
67 unsigned int wstrd;
68 unsigned int wstwr;
69 unsigned int wstoen;
70 unsigned int wstwen;
71 unsigned int wstbrd;
72
73 /* register cache */
74 unsigned char smbidcyr;
75 unsigned char smbwstrd;
76 unsigned char smbwstwr;
77 unsigned char smbwstoen;
78 unsigned char smbwstwen;
79 unsigned char smbwstbrd;
80};
81
82union s3c_iobank {
83 struct s3c2410_iobank_timing *io_2410;
84 struct s3c2412_iobank_timing *io_2412;
85};
86
87/**
88 * struct s3c_iotimings - Chip IO timings holder
89 * @bank: The timings for each IO bank.
90 */
91struct s3c_iotimings {
92 union s3c_iobank bank[MAX_BANKS];
93};
94
95/**
96 * struct s3c_plltab - PLL table information.
97 * @vals: List of PLL values.
98 * @size: Size of the PLL table @vals.
99 */
100struct s3c_plltab {
101 struct s3c_pllval *vals;
102 int size;
103};
104
105/**
106 * struct s3c_cpufreq_config - current cpu frequency configuration
107 * @freq: The current settings for the core clocks.
108 * @max: Maxium settings, derived from core, board and user settings.
109 * @pll: The PLL table entry for the current PLL settings.
110 * @divs: The divisor settings for the core clocks.
111 * @info: The current core driver information.
112 * @board: The information for the board we are running on.
113 * @lock_pll: Set if the PLL settings cannot be changed.
114 *
115 * This is for the core drivers that need to know information about
116 * the current settings and values. It should not be needed by any
117 * device drivers.
118*/
119struct s3c_cpufreq_config {
120 struct s3c_freq freq;
121 struct s3c_freq max;
122 struct cpufreq_frequency_table pll;
123 struct s3c_clkdivs divs;
124 struct s3c_cpufreq_info *info; /* for core, not drivers */
125 struct s3c_cpufreq_board *board;
126
127 unsigned int lock_pll:1;
128};
129
130/**
131 * struct s3c_cpufreq_info - Information for the CPU frequency driver.
132 * @name: The name of this implementation.
133 * @max: The maximum frequencies for the system.
134 * @latency: Transition latency to give to cpufreq.
135 * @locktime_m: The lock-time in uS for the MPLL.
136 * @locktime_u: The lock-time in uS for the UPLL.
137 * @locttime_bits: The number of bits each LOCKTIME field.
138 * @need_pll: Set if this driver needs to change the PLL values to acheive
139 * any frequency changes. This is really only need by devices like the
140 * S3C2410 where there is no or limited divider between the PLL and the
141 * ARMCLK.
142 * @resume_clocks: Update the clocks on resume.
143 * @get_iotiming: Get the current IO timing data, mainly for use at start.
144 * @set_iotiming: Update the IO timings from the cached copies calculated
145 * from the @calc_iotiming entry when changing the frequency.
146 * @calc_iotiming: Calculate and update the cached copies of the IO timings
147 * from the newly calculated frequencies.
148 * @calc_freqtable: Calculate (fill in) the given frequency table from the
149 * current frequency configuration. If the table passed in is NULL,
150 * then the return is the number of elements to be filled for allocation
151 * of the table.
152 * @set_refresh: Set the memory refresh configuration.
153 * @set_fvco: Set the PLL frequencies.
154 * @set_divs: Update the clock divisors.
155 * @calc_divs: Calculate the clock divisors.
156 */
157struct s3c_cpufreq_info {
158 const char *name;
159 struct s3c_freq max;
160
161 unsigned int latency;
162
163 unsigned int locktime_m;
164 unsigned int locktime_u;
165 unsigned char locktime_bits;
166
167 unsigned int need_pll:1;
168
169 /* driver routines */
170
171 void (*resume_clocks)(void);
172
173 int (*get_iotiming)(struct s3c_cpufreq_config *cfg,
174 struct s3c_iotimings *timings);
175
176 void (*set_iotiming)(struct s3c_cpufreq_config *cfg,
177 struct s3c_iotimings *timings);
178
179 int (*calc_iotiming)(struct s3c_cpufreq_config *cfg,
180 struct s3c_iotimings *timings);
181
182 int (*calc_freqtable)(struct s3c_cpufreq_config *cfg,
183 struct cpufreq_frequency_table *t,
184 size_t table_size);
185
186 void (*debug_io_show)(struct seq_file *seq,
187 struct s3c_cpufreq_config *cfg,
188 union s3c_iobank *iob);
189
190 void (*set_refresh)(struct s3c_cpufreq_config *cfg);
191 void (*set_fvco)(struct s3c_cpufreq_config *cfg);
192 void (*set_divs)(struct s3c_cpufreq_config *cfg);
193 int (*calc_divs)(struct s3c_cpufreq_config *cfg);
194};
195
196extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info);
197
198extern int s3c_plltab_register(struct cpufreq_frequency_table *plls, unsigned int plls_no);
199
200/* exports and utilities for debugfs */
201extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void);
202extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void);
203
204extern void s3c2410_iotiming_debugfs(struct seq_file *seq,
205 struct s3c_cpufreq_config *cfg,
206 union s3c_iobank *iob);
207
208extern void s3c2412_iotiming_debugfs(struct seq_file *seq,
209 struct s3c_cpufreq_config *cfg,
210 union s3c_iobank *iob);
211
212#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS
213#define s3c_cpufreq_debugfs_call(x) x
214#else
215#define s3c_cpufreq_debugfs_call(x) NULL
216#endif
217
218/* Useful utility functions. */
219
220extern struct clk *s3c_cpufreq_clk_get(struct device *, const char *);
221
222/* S3C2410 and compatible exported functions */
223
224extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg);
225
226extern int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
227 struct s3c_iotimings *iot);
228
229extern int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
230 struct s3c_iotimings *timings);
231
232extern void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
233 struct s3c_iotimings *iot);
234
235extern void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg);
236
237/* S3C2412 compatible routines */
238
239extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
240 struct s3c_iotimings *timings);
241
242extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
243 struct s3c_iotimings *timings);
244
245extern int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg,
246 struct s3c_iotimings *iot);
247
248extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
249 struct s3c_iotimings *iot);
250
251#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUG
252#define s3c_freq_dbg(x...) printk(KERN_INFO x)
253#else
254#define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0)
255#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUG */
256
257#ifdef CONFIG_CPU_FREQ_S3C24XX_IODEBUG
258#define s3c_freq_iodbg(x...) printk(KERN_INFO x)
259#else
260#define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0)
261#endif /* CONFIG_CPU_FREQ_S3C24XX_IODEBUG */
262
263static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table,
264 int index, size_t table_size,
265 unsigned int freq)
266{
267 if (index < 0)
268 return index;
269
270 if (table) {
271 if (index >= table_size)
272 return -ENOMEM;
273
274 s3c_freq_dbg("%s: { %d = %u kHz }\n",
275 __func__, index, freq);
276
277 table[index].index = index;
278 table[index].frequency = freq;
279 }
280
281 return index + 1;
282}
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
index a9ac9e29759e..b6deeef8f663 100644
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
@@ -14,6 +14,7 @@
14#ifdef CONFIG_CPU_S3C2410 14#ifdef CONFIG_CPU_S3C2410
15 15
16extern int s3c2410_init(void); 16extern int s3c2410_init(void);
17extern int s3c2410a_init(void);
17 18
18extern void s3c2410_map_io(void); 19extern void s3c2410_map_io(void);
19 20
diff --git a/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c b/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c
new file mode 100644
index 000000000000..43ea80190d87
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c
@@ -0,0 +1,64 @@
1/* linux/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c
2 *
3 * Copyright (c) 2009 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C24XX CPU Frequency scaling - utils for S3C2410/S3C2440/S3C2442
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/errno.h>
16#include <linux/cpufreq.h>
17#include <linux/io.h>
18
19#include <mach/map.h>
20#include <mach/regs-mem.h>
21#include <mach/regs-clock.h>
22
23#include <plat/cpu-freq-core.h>
24
25/**
26 * s3c2410_cpufreq_setrefresh - set SDRAM refresh value
27 * @cfg: The frequency configuration
28 *
29 * Set the SDRAM refresh value appropriately for the configured
30 * frequency.
31 */
32void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
33{
34 struct s3c_cpufreq_board *board = cfg->board;
35 unsigned long refresh;
36 unsigned long refval;
37
38 /* Reduce both the refresh time (in ns) and the frequency (in MHz)
39 * down to ensure that we do not overflow 32 bit numbers.
40 *
41 * This should work for HCLK up to 133MHz and refresh period up
42 * to 30usec.
43 */
44
45 refresh = (cfg->freq.hclk / 100) * (board->refresh / 10);
46 refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */
47 refresh = (1 << 11) + 1 - refresh;
48
49 s3c_freq_dbg("%s: refresh value %lu\n", __func__, refresh);
50
51 refval = __raw_readl(S3C2410_REFRESH);
52 refval &= ~((1 << 12) - 1);
53 refval |= refresh;
54 __raw_writel(refval, S3C2410_REFRESH);
55}
56
57/**
58 * s3c2410_set_fvco - set the PLL value
59 * @cfg: The frequency configuration
60 */
61void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
62{
63 __raw_writel(cfg->pll.index, S3C2410_MPLLCON);
64}
diff --git a/arch/arm/plat-s3c24xx/s3c2410-iotiming.c b/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
new file mode 100644
index 000000000000..d0a3a145cd4d
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
@@ -0,0 +1,477 @@
1/* linux/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
2 *
3 * Copyright (c) 2006,2008,2009 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C24XX CPU Frequency scaling - IO timing for S3C2410/S3C2440/S3C2442
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/errno.h>
17#include <linux/cpufreq.h>
18#include <linux/seq_file.h>
19#include <linux/io.h>
20
21#include <mach/map.h>
22#include <mach/regs-mem.h>
23#include <mach/regs-clock.h>
24
25#include <plat/cpu-freq-core.h>
26
27#define print_ns(x) ((x) / 10), ((x) % 10)
28
29/**
30 * s3c2410_print_timing - print bank timing data for debug purposes
31 * @pfx: The prefix to put on the output
32 * @timings: The timing inforamtion to print.
33*/
34static void s3c2410_print_timing(const char *pfx,
35 struct s3c_iotimings *timings)
36{
37 struct s3c2410_iobank_timing *bt;
38 int bank;
39
40 for (bank = 0; bank < MAX_BANKS; bank++) {
41 bt = timings->bank[bank].io_2410;
42 if (!bt)
43 continue;
44
45 printk(KERN_DEBUG "%s %d: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, "
46 "Tcoh=%d.%d, Tcah=%d.%d\n", pfx, bank,
47 print_ns(bt->tacs),
48 print_ns(bt->tcos),
49 print_ns(bt->tacc),
50 print_ns(bt->tcoh),
51 print_ns(bt->tcah));
52 }
53}
54
55/**
56 * bank_reg - convert bank number to pointer to the control register.
57 * @bank: The IO bank number.
58 */
59static inline void __iomem *bank_reg(unsigned int bank)
60{
61 return S3C2410_BANKCON0 + (bank << 2);
62}
63
64/**
65 * bank_is_io - test whether bank is used for IO
66 * @bankcon: The bank control register.
67 *
68 * This is a simplistic test to see if any BANKCON[x] is not an IO
69 * bank. It currently does not take into account whether BWSCON has
70 * an illegal width-setting in it, or if the pin connected to nCS[x]
71 * is actually being handled as a chip-select.
72 */
73static inline int bank_is_io(unsigned long bankcon)
74{
75 return !(bankcon & S3C2410_BANKCON_SDRAM);
76}
77
78/**
79 * to_div - convert cycle time to divisor
80 * @cyc: The cycle time, in 10ths of nanoseconds.
81 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
82 *
83 * Convert the given cycle time into the divisor to use to obtain it from
84 * HCLK.
85*/
86static inline unsigned int to_div(unsigned int cyc, unsigned int hclk_tns)
87{
88 if (cyc == 0)
89 return 0;
90
91 return DIV_ROUND_UP(cyc, hclk_tns);
92}
93
94/**
95 * calc_0124 - calculate divisor control for divisors that do /0, /1. /2 and /4
96 * @cyc: The cycle time, in 10ths of nanoseconds.
97 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
98 * @v: Pointer to register to alter.
99 * @shift: The shift to get to the control bits.
100 *
101 * Calculate the divisor, and turn it into the correct control bits to
102 * set in the result, @v.
103 */
104static unsigned int calc_0124(unsigned int cyc, unsigned long hclk_tns,
105 unsigned long *v, int shift)
106{
107 unsigned int div = to_div(cyc, hclk_tns);
108 unsigned long val;
109
110 s3c_freq_iodbg("%s: cyc=%d, hclk=%lu, shift=%d => div %d\n",
111 __func__, cyc, hclk_tns, shift, div);
112
113 switch (div) {
114 case 0:
115 val = 0;
116 break;
117 case 1:
118 val = 1;
119 break;
120 case 2:
121 val = 2;
122 break;
123 case 3:
124 case 4:
125 val = 3;
126 break;
127 default:
128 return -1;
129 }
130
131 *v |= val << shift;
132 return 0;
133}
134
135int calc_tacp(unsigned int cyc, unsigned long hclk, unsigned long *v)
136{
137 /* Currently no support for Tacp calculations. */
138 return 0;
139}
140
141/**
142 * calc_tacc - calculate divisor control for tacc.
143 * @cyc: The cycle time, in 10ths of nanoseconds.
144 * @nwait_en: IS nWAIT enabled for this bank.
145 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
146 * @v: Pointer to register to alter.
147 *
148 * Calculate the divisor control for tACC, taking into account whether
149 * the bank has nWAIT enabled. The result is used to modify the value
150 * pointed to by @v.
151*/
152static int calc_tacc(unsigned int cyc, int nwait_en,
153 unsigned long hclk_tns, unsigned long *v)
154{
155 unsigned int div = to_div(cyc, hclk_tns);
156 unsigned long val;
157
158 s3c_freq_iodbg("%s: cyc=%u, nwait=%d, hclk=%lu => div=%u\n",
159 __func__, cyc, nwait_en, hclk_tns, div);
160
161 /* if nWait enabled on an bank, Tacc must be at-least 4 cycles. */
162 if (nwait_en && div < 4)
163 div = 4;
164
165 switch (div) {
166 case 0:
167 val = 0;
168 break;
169
170 case 1:
171 case 2:
172 case 3:
173 case 4:
174 val = div - 1;
175 break;
176
177 case 5:
178 case 6:
179 val = 4;
180 break;
181
182 case 7:
183 case 8:
184 val = 5;
185 break;
186
187 case 9:
188 case 10:
189 val = 6;
190 break;
191
192 case 11:
193 case 12:
194 case 13:
195 case 14:
196 val = 7;
197 break;
198
199 default:
200 return -1;
201 }
202
203 *v |= val << 8;
204 return 0;
205}
206
207/**
208 * s3c2410_calc_bank - calculate bank timing infromation
209 * @cfg: The configuration we need to calculate for.
210 * @bt: The bank timing information.
211 *
212 * Given the cycle timine for a bank @bt, calculate the new BANKCON
213 * setting for the @cfg timing. This updates the timing information
214 * ready for the cpu frequency change.
215 */
216static int s3c2410_calc_bank(struct s3c_cpufreq_config *cfg,
217 struct s3c2410_iobank_timing *bt)
218{
219 unsigned long hclk = cfg->freq.hclk_tns;
220 unsigned long res;
221 int ret;
222
223 res = bt->bankcon;
224 res &= (S3C2410_BANKCON_SDRAM | S3C2410_BANKCON_PMC16);
225
226 /* tacp: 2,3,4,5 */
227 /* tcah: 0,1,2,4 */
228 /* tcoh: 0,1,2,4 */
229 /* tacc: 1,2,3,4,6,7,10,14 (>4 for nwait) */
230 /* tcos: 0,1,2,4 */
231 /* tacs: 0,1,2,4 */
232
233 ret = calc_0124(bt->tacs, hclk, &res, S3C2410_BANKCON_Tacs_SHIFT);
234 ret |= calc_0124(bt->tcos, hclk, &res, S3C2410_BANKCON_Tcos_SHIFT);
235 ret |= calc_0124(bt->tcah, hclk, &res, S3C2410_BANKCON_Tcah_SHIFT);
236 ret |= calc_0124(bt->tcoh, hclk, &res, S3C2410_BANKCON_Tcoh_SHIFT);
237
238 if (ret)
239 return -EINVAL;
240
241 ret |= calc_tacp(bt->tacp, hclk, &res);
242 ret |= calc_tacc(bt->tacc, bt->nwait_en, hclk, &res);
243
244 if (ret)
245 return -EINVAL;
246
247 bt->bankcon = res;
248 return 0;
249}
250
251static unsigned int tacc_tab[] = {
252 [0] = 1,
253 [1] = 2,
254 [2] = 3,
255 [3] = 4,
256 [4] = 6,
257 [5] = 9,
258 [6] = 10,
259 [7] = 14,
260};
261
262/**
263 * get_tacc - turn tACC value into cycle time
264 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
265 * @val: The bank timing register value, shifed down.
266 */
267static unsigned int get_tacc(unsigned long hclk_tns,
268 unsigned long val)
269{
270 val &= 7;
271 return hclk_tns * tacc_tab[val];
272}
273
274/**
275 * get_0124 - turn 0/1/2/4 divider into cycle time
276 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
277 * @val: The bank timing register value, shifed down.
278 */
279static unsigned int get_0124(unsigned long hclk_tns,
280 unsigned long val)
281{
282 val &= 3;
283 return hclk_tns * ((val == 3) ? 4 : val);
284}
285
286/**
287 * s3c2410_iotiming_getbank - turn BANKCON into cycle time information
288 * @cfg: The frequency configuration
289 * @bt: The bank timing to fill in (uses cached BANKCON)
290 *
291 * Given the BANKCON setting in @bt and the current frequency settings
292 * in @cfg, update the cycle timing information.
293 */
294void s3c2410_iotiming_getbank(struct s3c_cpufreq_config *cfg,
295 struct s3c2410_iobank_timing *bt)
296{
297 unsigned long bankcon = bt->bankcon;
298 unsigned long hclk = cfg->freq.hclk_tns;
299
300 bt->tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT);
301 bt->tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT);
302 bt->tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT);
303 bt->tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT);
304 bt->tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT);
305}
306
307/**
308 * s3c2410_iotiming_debugfs - debugfs show io bank timing information
309 * @seq: The seq_file to write output to using seq_printf().
310 * @cfg: The current configuration.
311 * @iob: The IO bank information to decode.
312 */
313void s3c2410_iotiming_debugfs(struct seq_file *seq,
314 struct s3c_cpufreq_config *cfg,
315 union s3c_iobank *iob)
316{
317 struct s3c2410_iobank_timing *bt = iob->io_2410;
318 unsigned long bankcon = bt->bankcon;
319 unsigned long hclk = cfg->freq.hclk_tns;
320 unsigned int tacs;
321 unsigned int tcos;
322 unsigned int tacc;
323 unsigned int tcoh;
324 unsigned int tcah;
325
326 seq_printf(seq, "BANKCON=0x%08lx\n", bankcon);
327
328 tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT);
329 tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT);
330 tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT);
331 tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT);
332 tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT);
333
334 seq_printf(seq,
335 "\tRead: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, Tcoh=%d.%d, Tcah=%d.%d\n",
336 print_ns(bt->tacs),
337 print_ns(bt->tcos),
338 print_ns(bt->tacc),
339 print_ns(bt->tcoh),
340 print_ns(bt->tcah));
341
342 seq_printf(seq,
343 "\t Set: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, Tcoh=%d.%d, Tcah=%d.%d\n",
344 print_ns(tacs),
345 print_ns(tcos),
346 print_ns(tacc),
347 print_ns(tcoh),
348 print_ns(tcah));
349}
350
351/**
352 * s3c2410_iotiming_calc - Calculate bank timing for frequency change.
353 * @cfg: The frequency configuration
354 * @iot: The IO timing information to fill out.
355 *
356 * Calculate the new values for the banks in @iot based on the new
357 * frequency information in @cfg. This is then used by s3c2410_iotiming_set()
358 * to update the timing when necessary.
359 */
360int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
361 struct s3c_iotimings *iot)
362{
363 struct s3c2410_iobank_timing *bt;
364 unsigned long bankcon;
365 int bank;
366 int ret;
367
368 for (bank = 0; bank < MAX_BANKS; bank++) {
369 bankcon = __raw_readl(bank_reg(bank));
370 bt = iot->bank[bank].io_2410;
371
372 if (!bt)
373 continue;
374
375 bt->bankcon = bankcon;
376
377 ret = s3c2410_calc_bank(cfg, bt);
378 if (ret) {
379 printk(KERN_ERR "%s: cannot calculate bank %d io\n",
380 __func__, bank);
381 goto err;
382 }
383
384 s3c_freq_iodbg("%s: bank %d: con=%08lx\n",
385 __func__, bank, bt->bankcon);
386 }
387
388 return 0;
389 err:
390 return ret;
391}
392
393/**
394 * s3c2410_iotiming_set - set the IO timings from the given setup.
395 * @cfg: The frequency configuration
396 * @iot: The IO timing information to use.
397 *
398 * Set all the currently used IO bank timing information generated
399 * by s3c2410_iotiming_calc() once the core has validated that all
400 * the new values are within permitted bounds.
401 */
402void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
403 struct s3c_iotimings *iot)
404{
405 struct s3c2410_iobank_timing *bt;
406 int bank;
407
408 /* set the io timings from the specifier */
409
410 for (bank = 0; bank < MAX_BANKS; bank++) {
411 bt = iot->bank[bank].io_2410;
412 if (!bt)
413 continue;
414
415 __raw_writel(bt->bankcon, bank_reg(bank));
416 }
417}
418
419/**
420 * s3c2410_iotiming_get - Get the timing information from current registers.
421 * @cfg: The frequency configuration
422 * @timings: The IO timing information to fill out.
423 *
424 * Calculate the @timings timing information from the current frequency
425 * information in @cfg, and the new frequency configur
426 * through all the IO banks, reading the state and then updating @iot
427 * as necessary.
428 *
429 * This is used at the moment on initialisation to get the current
430 * configuration so that boards do not have to carry their own setup
431 * if the timings are correct on initialisation.
432 */
433
434int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
435 struct s3c_iotimings *timings)
436{
437 struct s3c2410_iobank_timing *bt;
438 unsigned long bankcon;
439 unsigned long bwscon;
440 int bank;
441
442 bwscon = __raw_readl(S3C2410_BWSCON);
443
444 /* look through all banks to see what is currently set. */
445
446 for (bank = 0; bank < MAX_BANKS; bank++) {
447 bankcon = __raw_readl(bank_reg(bank));
448
449 if (!bank_is_io(bankcon))
450 continue;
451
452 s3c_freq_iodbg("%s: bank %d: con %08lx\n",
453 __func__, bank, bankcon);
454
455 bt = kzalloc(sizeof(struct s3c2410_iobank_timing), GFP_KERNEL);
456 if (!bt) {
457 printk(KERN_ERR "%s: no memory for bank\n", __func__);
458 return -ENOMEM;
459 }
460
461 /* find out in nWait is enabled for bank. */
462
463 if (bank != 0) {
464 unsigned long tmp = S3C2410_BWSCON_GET(bwscon, bank);
465 if (tmp & S3C2410_BWSCON_WS)
466 bt->nwait_en = 1;
467 }
468
469 timings->bank[bank].io_2410 = bt;
470 bt->bankcon = bankcon;
471
472 s3c2410_iotiming_getbank(cfg, bt);
473 }
474
475 s3c2410_print_timing("get", timings);
476 return 0;
477}
diff --git a/arch/arm/plat-s3c24xx/s3c2412-iotiming.c b/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
new file mode 100644
index 000000000000..fd45e47facbc
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
@@ -0,0 +1,285 @@
1/* linux/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
2 *
3 * Copyright (c) 2006,2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2412/S3C2443 (PL093 based) IO timing support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/ioport.h>
18#include <linux/cpufreq.h>
19#include <linux/seq_file.h>
20#include <linux/sysdev.h>
21#include <linux/delay.h>
22#include <linux/clk.h>
23#include <linux/err.h>
24
25#include <linux/amba/pl093.h>
26
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29
30#include <mach/regs-s3c2412-mem.h>
31
32#include <plat/cpu.h>
33#include <plat/cpu-freq-core.h>
34#include <plat/clock.h>
35
36#define print_ns(x) ((x) / 10), ((x) % 10)
37
38/**
39 * s3c2412_print_timing - print timing infromation via printk.
40 * @pfx: The prefix to print each line with.
41 * @iot: The IO timing information
42 */
43static void s3c2412_print_timing(const char *pfx, struct s3c_iotimings *iot)
44{
45 struct s3c2412_iobank_timing *bt;
46 unsigned int bank;
47
48 for (bank = 0; bank < MAX_BANKS; bank++) {
49 bt = iot->bank[bank].io_2412;
50 if (!bt)
51 continue;
52
53 printk(KERN_DEBUG "%s: %d: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d"
54 "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", pfx, bank,
55 print_ns(bt->idcy),
56 print_ns(bt->wstrd),
57 print_ns(bt->wstwr),
58 print_ns(bt->wstoen),
59 print_ns(bt->wstwen),
60 print_ns(bt->wstbrd));
61 }
62}
63
64/**
65 * to_div - turn a cycle length into a divisor setting.
66 * @cyc_tns: The cycle time in 10ths of nanoseconds.
67 * @clk_tns: The clock period in 10ths of nanoseconds.
68 */
69static inline unsigned int to_div(unsigned int cyc_tns, unsigned int clk_tns)
70{
71 return cyc_tns ? DIV_ROUND_UP(cyc_tns, clk_tns) : 0;
72}
73
74/**
75 * calc_timing - calculate timing divisor value and check in range.
76 * @hwtm: The hardware timing in 10ths of nanoseconds.
77 * @clk_tns: The clock period in 10ths of nanoseconds.
78 * @err: Pointer to err variable to update in event of failure.
79 */
80static unsigned int calc_timing(unsigned int hwtm, unsigned int clk_tns,
81 unsigned int *err)
82{
83 unsigned int ret = to_div(hwtm, clk_tns);
84
85 if (ret > 0xf)
86 *err = -EINVAL;
87
88 return ret;
89}
90
91/**
92 * s3c2412_calc_bank - calculate the bank divisor settings.
93 * @cfg: The current frequency configuration.
94 * @bt: The bank timing.
95 */
96static int s3c2412_calc_bank(struct s3c_cpufreq_config *cfg,
97 struct s3c2412_iobank_timing *bt)
98{
99 unsigned int hclk = cfg->freq.hclk_tns;
100 int err = 0;
101
102 bt->smbidcyr = calc_timing(bt->idcy, hclk, &err);
103 bt->smbwstrd = calc_timing(bt->wstrd, hclk, &err);
104 bt->smbwstwr = calc_timing(bt->wstwr, hclk, &err);
105 bt->smbwstoen = calc_timing(bt->wstoen, hclk, &err);
106 bt->smbwstwen = calc_timing(bt->wstwen, hclk, &err);
107 bt->smbwstbrd = calc_timing(bt->wstbrd, hclk, &err);
108
109 return err;
110}
111
112/**
113 * s3c2412_iotiming_debugfs - debugfs show io bank timing information
114 * @seq: The seq_file to write output to using seq_printf().
115 * @cfg: The current configuration.
116 * @iob: The IO bank information to decode.
117*/
118void s3c2412_iotiming_debugfs(struct seq_file *seq,
119 struct s3c_cpufreq_config *cfg,
120 union s3c_iobank *iob)
121{
122 struct s3c2412_iobank_timing *bt = iob->io_2412;
123
124 seq_printf(seq,
125 "\tRead: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d"
126 "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n",
127 print_ns(bt->idcy),
128 print_ns(bt->wstrd),
129 print_ns(bt->wstwr),
130 print_ns(bt->wstoen),
131 print_ns(bt->wstwen),
132 print_ns(bt->wstbrd));
133}
134
135/**
136 * s3c2412_iotiming_calc - calculate all the bank divisor settings.
137 * @cfg: The current frequency configuration.
138 * @iot: The bank timing information.
139 *
140 * Calculate the timing information for all the banks that are
141 * configured as IO, using s3c2412_calc_bank().
142 */
143int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg,
144 struct s3c_iotimings *iot)
145{
146 struct s3c2412_iobank_timing *bt;
147 int bank;
148 int ret;
149
150 for (bank = 0; bank < MAX_BANKS; bank++) {
151 bt = iot->bank[bank].io_2412;
152 if (!bt)
153 continue;
154
155 ret = s3c2412_calc_bank(cfg, bt);
156 if (ret) {
157 printk(KERN_ERR "%s: cannot calculate bank %d io\n",
158 __func__, bank);
159 goto err;
160 }
161 }
162
163 return 0;
164 err:
165 return ret;
166}
167
168/**
169 * s3c2412_iotiming_set - set the timing information
170 * @cfg: The current frequency configuration.
171 * @iot: The bank timing information.
172 *
173 * Set the IO bank information from the details calculated earlier from
174 * calling s3c2412_iotiming_calc().
175 */
176void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
177 struct s3c_iotimings *iot)
178{
179 struct s3c2412_iobank_timing *bt;
180 void __iomem *regs;
181 int bank;
182
183 /* set the io timings from the specifier */
184
185 for (bank = 0; bank < MAX_BANKS; bank++) {
186 bt = iot->bank[bank].io_2412;
187 if (!bt)
188 continue;
189
190 regs = S3C2412_SSMC_BANK(bank);
191
192 __raw_writel(bt->smbidcyr, regs + SMBIDCYR);
193 __raw_writel(bt->smbwstrd, regs + SMBWSTRDR);
194 __raw_writel(bt->smbwstwr, regs + SMBWSTWRR);
195 __raw_writel(bt->smbwstoen, regs + SMBWSTOENR);
196 __raw_writel(bt->smbwstwen, regs + SMBWSTWENR);
197 __raw_writel(bt->smbwstbrd, regs + SMBWSTBRDR);
198 }
199}
200
201static inline unsigned int s3c2412_decode_timing(unsigned int clock, u32 reg)
202{
203 return (reg & 0xf) * clock;
204}
205
206static void s3c2412_iotiming_getbank(struct s3c_cpufreq_config *cfg,
207 struct s3c2412_iobank_timing *bt,
208 unsigned int bank)
209{
210 unsigned long clk = cfg->freq.hclk_tns; /* ssmc clock??? */
211 void __iomem *regs = S3C2412_SSMC_BANK(bank);
212
213 bt->idcy = s3c2412_decode_timing(clk, __raw_readl(regs + SMBIDCYR));
214 bt->wstrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTRDR));
215 bt->wstoen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTOENR));
216 bt->wstwen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTWENR));
217 bt->wstbrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTBRDR));
218}
219
220/**
221 * bank_is_io - return true if bank is (possibly) IO.
222 * @bank: The bank number.
223 * @bankcfg: The value of S3C2412_EBI_BANKCFG.
224 */
225static inline bool bank_is_io(unsigned int bank, u32 bankcfg)
226{
227 if (bank < 2)
228 return true;
229
230 return !(bankcfg & (1 << bank));
231}
232
233int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
234 struct s3c_iotimings *timings)
235{
236 struct s3c2412_iobank_timing *bt;
237 u32 bankcfg = __raw_readl(S3C2412_EBI_BANKCFG);
238 unsigned int bank;
239
240 /* look through all banks to see what is currently set. */
241
242 for (bank = 0; bank < MAX_BANKS; bank++) {
243 if (!bank_is_io(bank, bankcfg))
244 continue;
245
246 bt = kzalloc(sizeof(struct s3c2412_iobank_timing), GFP_KERNEL);
247 if (!bt) {
248 printk(KERN_ERR "%s: no memory for bank\n", __func__);
249 return -ENOMEM;
250 }
251
252 timings->bank[bank].io_2412 = bt;
253 s3c2412_iotiming_getbank(cfg, bt, bank);
254 }
255
256 s3c2412_print_timing("get", timings);
257 return 0;
258}
259
260/* this is in here as it is so small, it doesn't currently warrant a file
261 * to itself. We expect that any s3c24xx needing this is going to also
262 * need the iotiming support.
263 */
264void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
265{
266 struct s3c_cpufreq_board *board = cfg->board;
267 u32 refresh;
268
269 WARN_ON(board == NULL);
270
271 /* Reduce both the refresh time (in ns) and the frequency (in MHz)
272 * down to ensure that we do not overflow 32 bit numbers.
273 *
274 * This should work for HCLK up to 133MHz and refresh period up
275 * to 30usec.
276 */
277
278 refresh = (cfg->freq.hclk / 100) * (board->refresh / 10);
279 refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */
280 refresh &= ((1 << 16) - 1);
281
282 s3c_freq_dbg("%s: refresh value %u\n", __func__, (unsigned int)refresh);
283
284 __raw_writel(refresh, S3C2412_REFRESH);
285}
diff --git a/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c b/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c
new file mode 100644
index 000000000000..ae2e6c604f27
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c
@@ -0,0 +1,311 @@
1/* linux/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c
2 *
3 * Copyright (c) 2006,2008,2009 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 * Vincent Sanders <vince@simtec.co.uk>
7 *
8 * S3C2440/S3C2442 CPU Frequency scaling
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/cpufreq.h>
20#include <linux/sysdev.h>
21#include <linux/delay.h>
22#include <linux/clk.h>
23#include <linux/err.h>
24#include <linux/io.h>
25
26#include <mach/hardware.h>
27
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30
31#include <mach/regs-clock.h>
32
33#include <plat/cpu.h>
34#include <plat/cpu-freq-core.h>
35#include <plat/clock.h>
36
37static struct clk *xtal;
38static struct clk *fclk;
39static struct clk *hclk;
40static struct clk *armclk;
41
42/* HDIV: 1, 2, 3, 4, 6, 8 */
43
44static inline int within_khz(unsigned long a, unsigned long b)
45{
46 long diff = a - b;
47
48 return (diff >= -1000 && diff <= 1000);
49}
50
51/**
52 * s3c2440_cpufreq_calcdivs - calculate divider settings
53 * @cfg: The cpu frequency settings.
54 *
55 * Calcualte the divider values for the given frequency settings
56 * specified in @cfg. The values are stored in @cfg for later use
57 * by the relevant set routine if the request settings can be reached.
58 */
59int s3c2440_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
60{
61 unsigned int hdiv, pdiv;
62 unsigned long hclk, fclk, armclk;
63 unsigned long hclk_max;
64
65 fclk = cfg->freq.fclk;
66 armclk = cfg->freq.armclk;
67 hclk_max = cfg->max.hclk;
68
69 s3c_freq_dbg("%s: fclk is %lu, armclk %lu, max hclk %lu\n",
70 __func__, fclk, armclk, hclk_max);
71
72 if (armclk > fclk) {
73 printk(KERN_WARNING "%s: armclk > fclk\n", __func__);
74 armclk = fclk;
75 }
76
77 /* if we are in DVS, we need HCLK to be <= ARMCLK */
78 if (armclk < fclk && armclk < hclk_max)
79 hclk_max = armclk;
80
81 for (hdiv = 1; hdiv < 9; hdiv++) {
82 if (hdiv == 5 || hdiv == 7)
83 hdiv++;
84
85 hclk = (fclk / hdiv);
86 if (hclk <= hclk_max || within_khz(hclk, hclk_max))
87 break;
88 }
89
90 s3c_freq_dbg("%s: hclk %lu, div %d\n", __func__, hclk, hdiv);
91
92 if (hdiv > 8)
93 goto invalid;
94
95 pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
96
97 if ((hclk / pdiv) > cfg->max.pclk)
98 pdiv++;
99
100 s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
101
102 if (pdiv > 2)
103 goto invalid;
104
105 pdiv *= hdiv;
106
107 /* calculate a valid armclk */
108
109 if (armclk < hclk)
110 armclk = hclk;
111
112 /* if we're running armclk lower than fclk, this really means
113 * that the system should go into dvs mode, which means that
114 * armclk is connected to hclk. */
115 if (armclk < fclk) {
116 cfg->divs.dvs = 1;
117 armclk = hclk;
118 } else
119 cfg->divs.dvs = 0;
120
121 cfg->freq.armclk = armclk;
122
123 /* store the result, and then return */
124
125 cfg->divs.h_divisor = hdiv;
126 cfg->divs.p_divisor = pdiv;
127
128 return 0;
129
130 invalid:
131 return -EINVAL;
132}
133
134#define CAMDIVN_HCLK_HALF (S3C2440_CAMDIVN_HCLK3_HALF | \
135 S3C2440_CAMDIVN_HCLK4_HALF)
136
137/**
138 * s3c2440_cpufreq_setdivs - set the cpu frequency divider settings
139 * @cfg: The cpu frequency settings.
140 *
141 * Set the divisors from the settings in @cfg, which where generated
142 * during the calculation phase by s3c2440_cpufreq_calcdivs().
143 */
144static void s3c2440_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
145{
146 unsigned long clkdiv, camdiv;
147
148 s3c_freq_dbg("%s: divsiors: h=%d, p=%d\n", __func__,
149 cfg->divs.h_divisor, cfg->divs.p_divisor);
150
151 clkdiv = __raw_readl(S3C2410_CLKDIVN);
152 camdiv = __raw_readl(S3C2440_CAMDIVN);
153
154 clkdiv &= ~(S3C2440_CLKDIVN_HDIVN_MASK | S3C2440_CLKDIVN_PDIVN);
155 camdiv &= ~CAMDIVN_HCLK_HALF;
156
157 switch (cfg->divs.h_divisor) {
158 case 1:
159 clkdiv |= S3C2440_CLKDIVN_HDIVN_1;
160 break;
161
162 case 2:
163 clkdiv |= S3C2440_CLKDIVN_HDIVN_2;
164 break;
165
166 case 6:
167 camdiv |= S3C2440_CAMDIVN_HCLK3_HALF;
168 case 3:
169 clkdiv |= S3C2440_CLKDIVN_HDIVN_3_6;
170 break;
171
172 case 8:
173 camdiv |= S3C2440_CAMDIVN_HCLK4_HALF;
174 case 4:
175 clkdiv |= S3C2440_CLKDIVN_HDIVN_4_8;
176 break;
177
178 default:
179 BUG(); /* we don't expect to get here. */
180 }
181
182 if (cfg->divs.p_divisor != cfg->divs.h_divisor)
183 clkdiv |= S3C2440_CLKDIVN_PDIVN;
184
185 /* todo - set pclk. */
186
187 /* Write the divisors first with hclk intentionally halved so that
188 * when we write clkdiv we will under-frequency instead of over. We
189 * then make a short delay and remove the hclk halving if necessary.
190 */
191
192 __raw_writel(camdiv | CAMDIVN_HCLK_HALF, S3C2440_CAMDIVN);
193 __raw_writel(clkdiv, S3C2410_CLKDIVN);
194
195 ndelay(20);
196 __raw_writel(camdiv, S3C2440_CAMDIVN);
197
198 clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
199}
200
201static int run_freq_for(unsigned long max_hclk, unsigned long fclk,
202 int *divs,
203 struct cpufreq_frequency_table *table,
204 size_t table_size)
205{
206 unsigned long freq;
207 int index = 0;
208 int div;
209
210 for (div = *divs; div > 0; div = *divs++) {
211 freq = fclk / div;
212
213 if (freq > max_hclk && div != 1)
214 continue;
215
216 freq /= 1000; /* table is in kHz */
217 index = s3c_cpufreq_addfreq(table, index, table_size, freq);
218 if (index < 0)
219 break;
220 }
221
222 return index;
223}
224
225static int hclk_divs[] = { 1, 2, 3, 4, 6, 8, -1 };
226
227static int s3c2440_cpufreq_calctable(struct s3c_cpufreq_config *cfg,
228 struct cpufreq_frequency_table *table,
229 size_t table_size)
230{
231 int ret;
232
233 WARN_ON(cfg->info == NULL);
234 WARN_ON(cfg->board == NULL);
235
236 ret = run_freq_for(cfg->info->max.hclk,
237 cfg->info->max.fclk,
238 hclk_divs,
239 table, table_size);
240
241 s3c_freq_dbg("%s: returning %d\n", __func__, ret);
242
243 return ret;
244}
245
246struct s3c_cpufreq_info s3c2440_cpufreq_info = {
247 .max = {
248 .fclk = 400000000,
249 .hclk = 133333333,
250 .pclk = 66666666,
251 },
252
253 .locktime_m = 300,
254 .locktime_u = 300,
255 .locktime_bits = 16,
256
257 .name = "s3c244x",
258 .calc_iotiming = s3c2410_iotiming_calc,
259 .set_iotiming = s3c2410_iotiming_set,
260 .get_iotiming = s3c2410_iotiming_get,
261 .set_fvco = s3c2410_set_fvco,
262
263 .set_refresh = s3c2410_cpufreq_setrefresh,
264 .set_divs = s3c2440_cpufreq_setdivs,
265 .calc_divs = s3c2440_cpufreq_calcdivs,
266 .calc_freqtable = s3c2440_cpufreq_calctable,
267
268 .resume_clocks = s3c244x_setup_clocks,
269
270 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
271};
272
273static int s3c2440_cpufreq_add(struct sys_device *sysdev)
274{
275 xtal = s3c_cpufreq_clk_get(NULL, "xtal");
276 hclk = s3c_cpufreq_clk_get(NULL, "hclk");
277 fclk = s3c_cpufreq_clk_get(NULL, "fclk");
278 armclk = s3c_cpufreq_clk_get(NULL, "armclk");
279
280 if (IS_ERR(xtal) || IS_ERR(hclk) || IS_ERR(fclk) || IS_ERR(armclk)) {
281 printk(KERN_ERR "%s: failed to get clocks\n", __func__);
282 return -ENOENT;
283 }
284
285 return s3c_cpufreq_register(&s3c2440_cpufreq_info);
286}
287
288static struct sysdev_driver s3c2440_cpufreq_driver = {
289 .add = s3c2440_cpufreq_add,
290};
291
292static int s3c2440_cpufreq_init(void)
293{
294 return sysdev_driver_register(&s3c2440_sysclass,
295 &s3c2440_cpufreq_driver);
296}
297
298/* arch_initcall adds the clocks we need, so use subsys_initcall. */
299subsys_initcall(s3c2440_cpufreq_init);
300
301static struct sysdev_driver s3c2442_cpufreq_driver = {
302 .add = s3c2440_cpufreq_add,
303};
304
305static int s3c2442_cpufreq_init(void)
306{
307 return sysdev_driver_register(&s3c2442_sysclass,
308 &s3c2442_cpufreq_driver);
309}
310
311subsys_initcall(s3c2442_cpufreq_init);
diff --git a/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c b/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
new file mode 100644
index 000000000000..ff9443b233aa
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
@@ -0,0 +1,97 @@
1/* arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
2 *
3 * Copyright (c) 2006,2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 * Vincent Sanders <vince@arm.linux.org.uk>
7 *
8 * S3C2440/S3C2442 CPU PLL tables (12MHz Crystal)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/types.h>
16#include <linux/kernel.h>
17#include <linux/sysdev.h>
18#include <linux/clk.h>
19#include <linux/err.h>
20
21#include <plat/cpu.h>
22#include <plat/cpu-freq-core.h>
23
24static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = {
25 { .frequency = 75000000, .index = PLLVAL(0x75, 3, 3), }, /* FVco 600.000000 */
26 { .frequency = 80000000, .index = PLLVAL(0x98, 4, 3), }, /* FVco 640.000000 */
27 { .frequency = 90000000, .index = PLLVAL(0x70, 2, 3), }, /* FVco 720.000000 */
28 { .frequency = 100000000, .index = PLLVAL(0x5c, 1, 3), }, /* FVco 800.000000 */
29 { .frequency = 110000000, .index = PLLVAL(0x66, 1, 3), }, /* FVco 880.000000 */
30 { .frequency = 120000000, .index = PLLVAL(0x70, 1, 3), }, /* FVco 960.000000 */
31 { .frequency = 150000000, .index = PLLVAL(0x75, 3, 2), }, /* FVco 600.000000 */
32 { .frequency = 160000000, .index = PLLVAL(0x98, 4, 2), }, /* FVco 640.000000 */
33 { .frequency = 170000000, .index = PLLVAL(0x4d, 1, 2), }, /* FVco 680.000000 */
34 { .frequency = 180000000, .index = PLLVAL(0x70, 2, 2), }, /* FVco 720.000000 */
35 { .frequency = 190000000, .index = PLLVAL(0x57, 1, 2), }, /* FVco 760.000000 */
36 { .frequency = 200000000, .index = PLLVAL(0x5c, 1, 2), }, /* FVco 800.000000 */
37 { .frequency = 210000000, .index = PLLVAL(0x84, 2, 2), }, /* FVco 840.000000 */
38 { .frequency = 220000000, .index = PLLVAL(0x66, 1, 2), }, /* FVco 880.000000 */
39 { .frequency = 230000000, .index = PLLVAL(0x6b, 1, 2), }, /* FVco 920.000000 */
40 { .frequency = 240000000, .index = PLLVAL(0x70, 1, 2), }, /* FVco 960.000000 */
41 { .frequency = 300000000, .index = PLLVAL(0x75, 3, 1), }, /* FVco 600.000000 */
42 { .frequency = 310000000, .index = PLLVAL(0x93, 4, 1), }, /* FVco 620.000000 */
43 { .frequency = 320000000, .index = PLLVAL(0x98, 4, 1), }, /* FVco 640.000000 */
44 { .frequency = 330000000, .index = PLLVAL(0x66, 2, 1), }, /* FVco 660.000000 */
45 { .frequency = 340000000, .index = PLLVAL(0x4d, 1, 1), }, /* FVco 680.000000 */
46 { .frequency = 350000000, .index = PLLVAL(0xa7, 4, 1), }, /* FVco 700.000000 */
47 { .frequency = 360000000, .index = PLLVAL(0x70, 2, 1), }, /* FVco 720.000000 */
48 { .frequency = 370000000, .index = PLLVAL(0xb1, 4, 1), }, /* FVco 740.000000 */
49 { .frequency = 380000000, .index = PLLVAL(0x57, 1, 1), }, /* FVco 760.000000 */
50 { .frequency = 390000000, .index = PLLVAL(0x7a, 2, 1), }, /* FVco 780.000000 */
51 { .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */
52};
53
54static int s3c2440_plls12_add(struct sys_device *dev)
55{
56 struct clk *xtal_clk;
57 unsigned long xtal;
58
59 xtal_clk = clk_get(NULL, "xtal");
60 if (IS_ERR(xtal_clk))
61 return PTR_ERR(xtal_clk);
62
63 xtal = clk_get_rate(xtal_clk);
64 clk_put(xtal_clk);
65
66 if (xtal == 12000000) {
67 printk(KERN_INFO "Using PLL table for 12MHz crystal\n");
68 return s3c_plltab_register(s3c2440_plls_12,
69 ARRAY_SIZE(s3c2440_plls_12));
70 }
71
72 return 0;
73}
74
75static struct sysdev_driver s3c2440_plls12_drv = {
76 .add = s3c2440_plls12_add,
77};
78
79static int __init s3c2440_pll_12mhz(void)
80{
81 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_plls12_drv);
82
83}
84
85arch_initcall(s3c2440_pll_12mhz);
86
87static struct sysdev_driver s3c2442_plls12_drv = {
88 .add = s3c2440_plls12_add,
89};
90
91static int __init s3c2442_pll_12mhz(void)
92{
93 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_plls12_drv);
94
95}
96
97arch_initcall(s3c2442_pll_12mhz);
diff --git a/arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c b/arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c
new file mode 100644
index 000000000000..7679af13a94d
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c
@@ -0,0 +1,127 @@
1/* arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c
2 *
3 * Copyright (c) 2006-2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 * Vincent Sanders <vince@arm.linux.org.uk>
7 *
8 * S3C2440/S3C2442 CPU PLL tables (16.93444MHz Crystal)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/types.h>
16#include <linux/kernel.h>
17#include <linux/sysdev.h>
18#include <linux/clk.h>
19#include <linux/err.h>
20
21#include <plat/cpu.h>
22#include <plat/cpu-freq-core.h>
23
24static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = {
25 { .frequency = 78019200, .index = PLLVAL(121, 5, 3), }, /* FVco 624.153600 */
26 { .frequency = 84067200, .index = PLLVAL(131, 5, 3), }, /* FVco 672.537600 */
27 { .frequency = 90115200, .index = PLLVAL(141, 5, 3), }, /* FVco 720.921600 */
28 { .frequency = 96163200, .index = PLLVAL(151, 5, 3), }, /* FVco 769.305600 */
29 { .frequency = 102135600, .index = PLLVAL(185, 6, 3), }, /* FVco 817.084800 */
30 { .frequency = 108259200, .index = PLLVAL(171, 5, 3), }, /* FVco 866.073600 */
31 { .frequency = 114307200, .index = PLLVAL(127, 3, 3), }, /* FVco 914.457600 */
32 { .frequency = 120234240, .index = PLLVAL(134, 3, 3), }, /* FVco 961.873920 */
33 { .frequency = 126161280, .index = PLLVAL(141, 3, 3), }, /* FVco 1009.290240 */
34 { .frequency = 132088320, .index = PLLVAL(148, 3, 3), }, /* FVco 1056.706560 */
35 { .frequency = 138015360, .index = PLLVAL(155, 3, 3), }, /* FVco 1104.122880 */
36 { .frequency = 144789120, .index = PLLVAL(163, 3, 3), }, /* FVco 1158.312960 */
37 { .frequency = 150100363, .index = PLLVAL(187, 9, 2), }, /* FVco 600.401454 */
38 { .frequency = 156038400, .index = PLLVAL(121, 5, 2), }, /* FVco 624.153600 */
39 { .frequency = 162086400, .index = PLLVAL(126, 5, 2), }, /* FVco 648.345600 */
40 { .frequency = 168134400, .index = PLLVAL(131, 5, 2), }, /* FVco 672.537600 */
41 { .frequency = 174048000, .index = PLLVAL(177, 7, 2), }, /* FVco 696.192000 */
42 { .frequency = 180230400, .index = PLLVAL(141, 5, 2), }, /* FVco 720.921600 */
43 { .frequency = 186278400, .index = PLLVAL(124, 4, 2), }, /* FVco 745.113600 */
44 { .frequency = 192326400, .index = PLLVAL(151, 5, 2), }, /* FVco 769.305600 */
45 { .frequency = 198132480, .index = PLLVAL(109, 3, 2), }, /* FVco 792.529920 */
46 { .frequency = 204271200, .index = PLLVAL(185, 6, 2), }, /* FVco 817.084800 */
47 { .frequency = 210268800, .index = PLLVAL(141, 4, 2), }, /* FVco 841.075200 */
48 { .frequency = 216518400, .index = PLLVAL(171, 5, 2), }, /* FVco 866.073600 */
49 { .frequency = 222264000, .index = PLLVAL(97, 2, 2), }, /* FVco 889.056000 */
50 { .frequency = 228614400, .index = PLLVAL(127, 3, 2), }, /* FVco 914.457600 */
51 { .frequency = 234259200, .index = PLLVAL(158, 4, 2), }, /* FVco 937.036800 */
52 { .frequency = 240468480, .index = PLLVAL(134, 3, 2), }, /* FVco 961.873920 */
53 { .frequency = 246960000, .index = PLLVAL(167, 4, 2), }, /* FVco 987.840000 */
54 { .frequency = 252322560, .index = PLLVAL(141, 3, 2), }, /* FVco 1009.290240 */
55 { .frequency = 258249600, .index = PLLVAL(114, 2, 2), }, /* FVco 1032.998400 */
56 { .frequency = 264176640, .index = PLLVAL(148, 3, 2), }, /* FVco 1056.706560 */
57 { .frequency = 270950400, .index = PLLVAL(120, 2, 2), }, /* FVco 1083.801600 */
58 { .frequency = 276030720, .index = PLLVAL(155, 3, 2), }, /* FVco 1104.122880 */
59 { .frequency = 282240000, .index = PLLVAL(92, 1, 2), }, /* FVco 1128.960000 */
60 { .frequency = 289578240, .index = PLLVAL(163, 3, 2), }, /* FVco 1158.312960 */
61 { .frequency = 294235200, .index = PLLVAL(131, 2, 2), }, /* FVco 1176.940800 */
62 { .frequency = 300200727, .index = PLLVAL(187, 9, 1), }, /* FVco 600.401454 */
63 { .frequency = 306358690, .index = PLLVAL(191, 9, 1), }, /* FVco 612.717380 */
64 { .frequency = 312076800, .index = PLLVAL(121, 5, 1), }, /* FVco 624.153600 */
65 { .frequency = 318366720, .index = PLLVAL(86, 3, 1), }, /* FVco 636.733440 */
66 { .frequency = 324172800, .index = PLLVAL(126, 5, 1), }, /* FVco 648.345600 */
67 { .frequency = 330220800, .index = PLLVAL(109, 4, 1), }, /* FVco 660.441600 */
68 { .frequency = 336268800, .index = PLLVAL(131, 5, 1), }, /* FVco 672.537600 */
69 { .frequency = 342074880, .index = PLLVAL(93, 3, 1), }, /* FVco 684.149760 */
70 { .frequency = 348096000, .index = PLLVAL(177, 7, 1), }, /* FVco 696.192000 */
71 { .frequency = 355622400, .index = PLLVAL(118, 4, 1), }, /* FVco 711.244800 */
72 { .frequency = 360460800, .index = PLLVAL(141, 5, 1), }, /* FVco 720.921600 */
73 { .frequency = 366206400, .index = PLLVAL(165, 6, 1), }, /* FVco 732.412800 */
74 { .frequency = 372556800, .index = PLLVAL(124, 4, 1), }, /* FVco 745.113600 */
75 { .frequency = 378201600, .index = PLLVAL(126, 4, 1), }, /* FVco 756.403200 */
76 { .frequency = 384652800, .index = PLLVAL(151, 5, 1), }, /* FVco 769.305600 */
77 { .frequency = 391608000, .index = PLLVAL(177, 6, 1), }, /* FVco 783.216000 */
78 { .frequency = 396264960, .index = PLLVAL(109, 3, 1), }, /* FVco 792.529920 */
79 { .frequency = 402192000, .index = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */
80};
81
82static int s3c2440_plls169344_add(struct sys_device *dev)
83{
84 struct clk *xtal_clk;
85 unsigned long xtal;
86
87 xtal_clk = clk_get(NULL, "xtal");
88 if (IS_ERR(xtal_clk))
89 return PTR_ERR(xtal_clk);
90
91 xtal = clk_get_rate(xtal_clk);
92 clk_put(xtal_clk);
93
94 if (xtal == 169344000) {
95 printk(KERN_INFO "Using PLL table for 16.9344MHz crystal\n");
96 return s3c_plltab_register(s3c2440_plls_169344,
97 ARRAY_SIZE(s3c2440_plls_169344));
98 }
99
100 return 0;
101}
102
103static struct sysdev_driver s3c2440_plls169344_drv = {
104 .add = s3c2440_plls169344_add,
105};
106
107static int __init s3c2440_pll_16934400(void)
108{
109 return sysdev_driver_register(&s3c2440_sysclass,
110 &s3c2440_plls169344_drv);
111
112}
113
114arch_initcall(s3c2440_pll_16934400);
115
116static struct sysdev_driver s3c2442_plls169344_drv = {
117 .add = s3c2440_plls169344_add,
118};
119
120static int __init s3c2442_pll_16934400(void)
121{
122 return sysdev_driver_register(&s3c2442_sysclass,
123 &s3c2442_plls169344_drv);
124
125}
126
127arch_initcall(s3c2442_pll_16934400);
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-29 13:33:33 -0400