diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2011-03-24 08:35:09 -0400 |
---|---|---|
committer | Thomas Gleixner <tglx@linutronix.de> | 2011-03-29 08:47:58 -0400 |
commit | f38c02f3b338651e145aac2889ba976baf6b28b3 (patch) | |
tree | 30cfbf42ccff4a9dc26d95e9058ec76f5fde78bb /arch/arm/plat-s3c24xx | |
parent | 9323f26186403433293e87e717a7785f74f75d80 (diff) |
arm: Fold irq_set_chip/irq_set_handler
Use irq_set_chip_and_handler() instead. Converted with coccinelle.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/arm/plat-s3c24xx')
-rw-r--r-- | arch/arm/plat-s3c24xx/irq.c | 31 |
1 files changed, 15 insertions, 16 deletions
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c index c2a42d526635..9aee7e1668b1 100644 --- a/arch/arm/plat-s3c24xx/irq.c +++ b/arch/arm/plat-s3c24xx/irq.c | |||
@@ -592,8 +592,8 @@ void __init s3c24xx_init_irq(void) | |||
592 | case IRQ_UART1: | 592 | case IRQ_UART1: |
593 | case IRQ_UART2: | 593 | case IRQ_UART2: |
594 | case IRQ_ADCPARENT: | 594 | case IRQ_ADCPARENT: |
595 | irq_set_chip(irqno, &s3c_irq_level_chip); | 595 | irq_set_chip_and_handler(irqno, &s3c_irq_level_chip, |
596 | irq_set_handler(irqno, handle_level_irq); | 596 | handle_level_irq); |
597 | break; | 597 | break; |
598 | 598 | ||
599 | case IRQ_RESERVED6: | 599 | case IRQ_RESERVED6: |
@@ -603,8 +603,8 @@ void __init s3c24xx_init_irq(void) | |||
603 | 603 | ||
604 | default: | 604 | default: |
605 | //irqdbf("registering irq %d (s3c irq)\n", irqno); | 605 | //irqdbf("registering irq %d (s3c irq)\n", irqno); |
606 | irq_set_chip(irqno, &s3c_irq_chip); | 606 | irq_set_chip_and_handler(irqno, &s3c_irq_chip, |
607 | irq_set_handler(irqno, handle_edge_irq); | 607 | handle_edge_irq); |
608 | set_irq_flags(irqno, IRQF_VALID); | 608 | set_irq_flags(irqno, IRQF_VALID); |
609 | } | 609 | } |
610 | } | 610 | } |
@@ -623,15 +623,15 @@ void __init s3c24xx_init_irq(void) | |||
623 | 623 | ||
624 | for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { | 624 | for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { |
625 | irqdbf("registering irq %d (ext int)\n", irqno); | 625 | irqdbf("registering irq %d (ext int)\n", irqno); |
626 | irq_set_chip(irqno, &s3c_irq_eint0t4); | 626 | irq_set_chip_and_handler(irqno, &s3c_irq_eint0t4, |
627 | irq_set_handler(irqno, handle_edge_irq); | 627 | handle_edge_irq); |
628 | set_irq_flags(irqno, IRQF_VALID); | 628 | set_irq_flags(irqno, IRQF_VALID); |
629 | } | 629 | } |
630 | 630 | ||
631 | for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) { | 631 | for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) { |
632 | irqdbf("registering irq %d (extended s3c irq)\n", irqno); | 632 | irqdbf("registering irq %d (extended s3c irq)\n", irqno); |
633 | irq_set_chip(irqno, &s3c_irqext_chip); | 633 | irq_set_chip_and_handler(irqno, &s3c_irqext_chip, |
634 | irq_set_handler(irqno, handle_edge_irq); | 634 | handle_edge_irq); |
635 | set_irq_flags(irqno, IRQF_VALID); | 635 | set_irq_flags(irqno, IRQF_VALID); |
636 | } | 636 | } |
637 | 637 | ||
@@ -641,29 +641,28 @@ void __init s3c24xx_init_irq(void) | |||
641 | 641 | ||
642 | for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) { | 642 | for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) { |
643 | irqdbf("registering irq %d (s3c uart0 irq)\n", irqno); | 643 | irqdbf("registering irq %d (s3c uart0 irq)\n", irqno); |
644 | irq_set_chip(irqno, &s3c_irq_uart0); | 644 | irq_set_chip_and_handler(irqno, &s3c_irq_uart0, |
645 | irq_set_handler(irqno, handle_level_irq); | 645 | handle_level_irq); |
646 | set_irq_flags(irqno, IRQF_VALID); | 646 | set_irq_flags(irqno, IRQF_VALID); |
647 | } | 647 | } |
648 | 648 | ||
649 | for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) { | 649 | for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) { |
650 | irqdbf("registering irq %d (s3c uart1 irq)\n", irqno); | 650 | irqdbf("registering irq %d (s3c uart1 irq)\n", irqno); |
651 | irq_set_chip(irqno, &s3c_irq_uart1); | 651 | irq_set_chip_and_handler(irqno, &s3c_irq_uart1, |
652 | irq_set_handler(irqno, handle_level_irq); | 652 | handle_level_irq); |
653 | set_irq_flags(irqno, IRQF_VALID); | 653 | set_irq_flags(irqno, IRQF_VALID); |
654 | } | 654 | } |
655 | 655 | ||
656 | for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) { | 656 | for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) { |
657 | irqdbf("registering irq %d (s3c uart2 irq)\n", irqno); | 657 | irqdbf("registering irq %d (s3c uart2 irq)\n", irqno); |
658 | irq_set_chip(irqno, &s3c_irq_uart2); | 658 | irq_set_chip_and_handler(irqno, &s3c_irq_uart2, |
659 | irq_set_handler(irqno, handle_level_irq); | 659 | handle_level_irq); |
660 | set_irq_flags(irqno, IRQF_VALID); | 660 | set_irq_flags(irqno, IRQF_VALID); |
661 | } | 661 | } |
662 | 662 | ||
663 | for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) { | 663 | for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) { |
664 | irqdbf("registering irq %d (s3c adc irq)\n", irqno); | 664 | irqdbf("registering irq %d (s3c adc irq)\n", irqno); |
665 | irq_set_chip(irqno, &s3c_irq_adc); | 665 | irq_set_chip_and_handler(irqno, &s3c_irq_adc, handle_edge_irq); |
666 | irq_set_handler(irqno, handle_edge_irq); | ||
667 | set_irq_flags(irqno, IRQF_VALID); | 666 | set_irq_flags(irqno, IRQF_VALID); |
668 | } | 667 | } |
669 | 668 | ||