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authorKukjin Kim <kgene.kim@samsung.com>2011-09-28 07:48:52 -0400
committerKukjin Kim <kgene.kim@samsung.com>2011-10-04 06:48:44 -0400
commitdc98e4145d82e471cc02d4e0b950a1945bcb084f (patch)
tree31ea62ddbcdea3d576298c5e4ac286a7581e57e5 /arch/arm/plat-s3c24xx
parent3cd7b62bbd54c9c59e7c8c5815cca9ded21a0a80 (diff)
ARM: SAMSUNG: Move S3C24XX header files to plat-samsung
This patch moves header files from plat-s3c24xx to plat-samsung to remove plat-s3c24xx directory to make one plat-samsung directory for Samsung SoCs. And this patch includes fixing coding style, too. Cc: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/plat-s3c24xx')
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/audio-simtec.h37
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/common-smdk.h15
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h287
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/fiq.h13
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/irq.h115
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/mci.h52
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/regs-dma.h145
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/regs-iis.h68
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/regs-spi.h81
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/regs-udc.h153
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/udc.h57
11 files changed, 0 insertions, 1023 deletions
diff --git a/arch/arm/plat-s3c24xx/include/plat/audio-simtec.h b/arch/arm/plat-s3c24xx/include/plat/audio-simtec.h
deleted file mode 100644
index de5e88fdcb31..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/audio-simtec.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/* arch/arm/plat-s3c24xx/include/plat/audio-simtec.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Simtec Audio support.
12*/
13
14/**
15 * struct s3c24xx_audio_simtec_pdata - platform data for simtec audio
16 * @use_mpllin: Select codec clock from MPLLin
17 * @output_cdclk: Need to output CDCLK to the codec
18 * @have_mic: Set if we have a MIC socket
19 * @have_lout: Set if we have a LineOut socket
20 * @amp_gpio: GPIO pin to enable the AMP
21 * @amp_gain: Option GPIO to control AMP gain
22 */
23struct s3c24xx_audio_simtec_pdata {
24 unsigned int use_mpllin:1;
25 unsigned int output_cdclk:1;
26
27 unsigned int have_mic:1;
28 unsigned int have_lout:1;
29
30 int amp_gpio;
31 int amp_gain[2];
32
33 void (*startup)(void);
34};
35
36extern int simtec_audio_add(const char *codec_name, bool has_lr_routing,
37 struct s3c24xx_audio_simtec_pdata *pdata);
diff --git a/arch/arm/plat-s3c24xx/include/plat/common-smdk.h b/arch/arm/plat-s3c24xx/include/plat/common-smdk.h
deleted file mode 100644
index 58d9094c935c..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/common-smdk.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/* linux/include/asm-arm/plat-s3c24xx/common-smdk.h
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Common code for SMDK2410 and SMDK2440 boards
7 *
8 * http://www.fluff.org/ben/smdk2440/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15extern void smdk_machine_init(void);
diff --git a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h
deleted file mode 100644
index d623235ae961..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h
+++ /dev/null
@@ -1,287 +0,0 @@
1/* arch/arm/plat-s3c/include/plat/cpu-freq.h
2 *
3 * Copyright (c) 2006-2009 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C CPU frequency scaling support - core support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <plat/cpu-freq.h>
15
16struct seq_file;
17
18#define MAX_BANKS (8)
19#define S3C2412_MAX_IO (8)
20
21/**
22 * struct s3c2410_iobank_timing - IO bank timings for S3C2410 style timings
23 * @bankcon: The cached version of settings in this structure.
24 * @tacp:
25 * @tacs: Time from address valid to nCS asserted.
26 * @tcos: Time from nCS asserted to nOE or nWE asserted.
27 * @tacc: Time that nOE or nWE is asserted.
28 * @tcoh: Time nCS is held after nOE or nWE are released.
29 * @tcah: Time address is held for after
30 * @nwait_en: Whether nWAIT is enabled for this bank.
31 *
32 * This structure represents the IO timings for a S3C2410 style IO bank
33 * used by the CPU frequency support if it needs to change the settings
34 * of the IO.
35 */
36struct s3c2410_iobank_timing {
37 unsigned long bankcon;
38 unsigned int tacp;
39 unsigned int tacs;
40 unsigned int tcos;
41 unsigned int tacc;
42 unsigned int tcoh; /* nCS hold afrer nOE/nWE */
43 unsigned int tcah; /* Address hold after nCS */
44 unsigned char nwait_en; /* nWait enabled for bank. */
45};
46
47/**
48 * struct s3c2412_iobank_timing - io timings for PL092 (S3C2412) style IO
49 * @idcy: The idle cycle time between transactions.
50 * @wstrd: nCS release to end of read cycle.
51 * @wstwr: nCS release to end of write cycle.
52 * @wstoen: nCS assertion to nOE assertion time.
53 * @wstwen: nCS assertion to nWE assertion time.
54 * @wstbrd: Burst ready delay.
55 * @smbidcyr: Register cache for smbidcyr value.
56 * @smbwstrd: Register cache for smbwstrd value.
57 * @smbwstwr: Register cache for smbwstwr value.
58 * @smbwstoen: Register cache for smbwstoen value.
59 * @smbwstwen: Register cache for smbwstwen value.
60 * @smbwstbrd: Register cache for smbwstbrd value.
61 *
62 * Timing information for a IO bank on an S3C2412 or similar system which
63 * uses a PL093 block.
64 */
65struct s3c2412_iobank_timing {
66 unsigned int idcy;
67 unsigned int wstrd;
68 unsigned int wstwr;
69 unsigned int wstoen;
70 unsigned int wstwen;
71 unsigned int wstbrd;
72
73 /* register cache */
74 unsigned char smbidcyr;
75 unsigned char smbwstrd;
76 unsigned char smbwstwr;
77 unsigned char smbwstoen;
78 unsigned char smbwstwen;
79 unsigned char smbwstbrd;
80};
81
82union s3c_iobank {
83 struct s3c2410_iobank_timing *io_2410;
84 struct s3c2412_iobank_timing *io_2412;
85};
86
87/**
88 * struct s3c_iotimings - Chip IO timings holder
89 * @bank: The timings for each IO bank.
90 */
91struct s3c_iotimings {
92 union s3c_iobank bank[MAX_BANKS];
93};
94
95/**
96 * struct s3c_plltab - PLL table information.
97 * @vals: List of PLL values.
98 * @size: Size of the PLL table @vals.
99 */
100struct s3c_plltab {
101 struct s3c_pllval *vals;
102 int size;
103};
104
105/**
106 * struct s3c_cpufreq_config - current cpu frequency configuration
107 * @freq: The current settings for the core clocks.
108 * @max: Maxium settings, derived from core, board and user settings.
109 * @pll: The PLL table entry for the current PLL settings.
110 * @divs: The divisor settings for the core clocks.
111 * @info: The current core driver information.
112 * @board: The information for the board we are running on.
113 * @lock_pll: Set if the PLL settings cannot be changed.
114 *
115 * This is for the core drivers that need to know information about
116 * the current settings and values. It should not be needed by any
117 * device drivers.
118*/
119struct s3c_cpufreq_config {
120 struct s3c_freq freq;
121 struct s3c_freq max;
122 struct cpufreq_frequency_table pll;
123 struct s3c_clkdivs divs;
124 struct s3c_cpufreq_info *info; /* for core, not drivers */
125 struct s3c_cpufreq_board *board;
126
127 unsigned int lock_pll:1;
128};
129
130/**
131 * struct s3c_cpufreq_info - Information for the CPU frequency driver.
132 * @name: The name of this implementation.
133 * @max: The maximum frequencies for the system.
134 * @latency: Transition latency to give to cpufreq.
135 * @locktime_m: The lock-time in uS for the MPLL.
136 * @locktime_u: The lock-time in uS for the UPLL.
137 * @locttime_bits: The number of bits each LOCKTIME field.
138 * @need_pll: Set if this driver needs to change the PLL values to achieve
139 * any frequency changes. This is really only need by devices like the
140 * S3C2410 where there is no or limited divider between the PLL and the
141 * ARMCLK.
142 * @resume_clocks: Update the clocks on resume.
143 * @get_iotiming: Get the current IO timing data, mainly for use at start.
144 * @set_iotiming: Update the IO timings from the cached copies calculated
145 * from the @calc_iotiming entry when changing the frequency.
146 * @calc_iotiming: Calculate and update the cached copies of the IO timings
147 * from the newly calculated frequencies.
148 * @calc_freqtable: Calculate (fill in) the given frequency table from the
149 * current frequency configuration. If the table passed in is NULL,
150 * then the return is the number of elements to be filled for allocation
151 * of the table.
152 * @set_refresh: Set the memory refresh configuration.
153 * @set_fvco: Set the PLL frequencies.
154 * @set_divs: Update the clock divisors.
155 * @calc_divs: Calculate the clock divisors.
156 */
157struct s3c_cpufreq_info {
158 const char *name;
159 struct s3c_freq max;
160
161 unsigned int latency;
162
163 unsigned int locktime_m;
164 unsigned int locktime_u;
165 unsigned char locktime_bits;
166
167 unsigned int need_pll:1;
168
169 /* driver routines */
170
171 void (*resume_clocks)(void);
172
173 int (*get_iotiming)(struct s3c_cpufreq_config *cfg,
174 struct s3c_iotimings *timings);
175
176 void (*set_iotiming)(struct s3c_cpufreq_config *cfg,
177 struct s3c_iotimings *timings);
178
179 int (*calc_iotiming)(struct s3c_cpufreq_config *cfg,
180 struct s3c_iotimings *timings);
181
182 int (*calc_freqtable)(struct s3c_cpufreq_config *cfg,
183 struct cpufreq_frequency_table *t,
184 size_t table_size);
185
186 void (*debug_io_show)(struct seq_file *seq,
187 struct s3c_cpufreq_config *cfg,
188 union s3c_iobank *iob);
189
190 void (*set_refresh)(struct s3c_cpufreq_config *cfg);
191 void (*set_fvco)(struct s3c_cpufreq_config *cfg);
192 void (*set_divs)(struct s3c_cpufreq_config *cfg);
193 int (*calc_divs)(struct s3c_cpufreq_config *cfg);
194};
195
196extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info);
197
198extern int s3c_plltab_register(struct cpufreq_frequency_table *plls, unsigned int plls_no);
199
200/* exports and utilities for debugfs */
201extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void);
202extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void);
203
204extern void s3c2410_iotiming_debugfs(struct seq_file *seq,
205 struct s3c_cpufreq_config *cfg,
206 union s3c_iobank *iob);
207
208extern void s3c2412_iotiming_debugfs(struct seq_file *seq,
209 struct s3c_cpufreq_config *cfg,
210 union s3c_iobank *iob);
211
212#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS
213#define s3c_cpufreq_debugfs_call(x) x
214#else
215#define s3c_cpufreq_debugfs_call(x) NULL
216#endif
217
218/* Useful utility functions. */
219
220extern struct clk *s3c_cpufreq_clk_get(struct device *, const char *);
221
222/* S3C2410 and compatible exported functions */
223
224extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg);
225extern void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg);
226
227#ifdef CONFIG_S3C2410_IOTIMING
228extern int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
229 struct s3c_iotimings *iot);
230
231extern int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
232 struct s3c_iotimings *timings);
233
234extern void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
235 struct s3c_iotimings *iot);
236#else
237#define s3c2410_iotiming_calc NULL
238#define s3c2410_iotiming_get NULL
239#define s3c2410_iotiming_set NULL
240#endif /* CONFIG_S3C2410_IOTIMING */
241
242/* S3C2412 compatible routines */
243
244extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
245 struct s3c_iotimings *timings);
246
247extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
248 struct s3c_iotimings *timings);
249
250extern int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg,
251 struct s3c_iotimings *iot);
252
253extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
254 struct s3c_iotimings *iot);
255
256#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUG
257#define s3c_freq_dbg(x...) printk(KERN_INFO x)
258#else
259#define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0)
260#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUG */
261
262#ifdef CONFIG_CPU_FREQ_S3C24XX_IODEBUG
263#define s3c_freq_iodbg(x...) printk(KERN_INFO x)
264#else
265#define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0)
266#endif /* CONFIG_CPU_FREQ_S3C24XX_IODEBUG */
267
268static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table,
269 int index, size_t table_size,
270 unsigned int freq)
271{
272 if (index < 0)
273 return index;
274
275 if (table) {
276 if (index >= table_size)
277 return -ENOMEM;
278
279 s3c_freq_dbg("%s: { %d = %u kHz }\n",
280 __func__, index, freq);
281
282 table[index].index = index;
283 table[index].frequency = freq;
284 }
285
286 return index + 1;
287}
diff --git a/arch/arm/plat-s3c24xx/include/plat/fiq.h b/arch/arm/plat-s3c24xx/include/plat/fiq.h
deleted file mode 100644
index 8521b8372c5f..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/fiq.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/* linux/include/asm-arm/plat-s3c24xx/fiq.h
2 *
3 * Copyright (c) 2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C24XX CPU FIQ support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13extern int s3c24xx_set_fiq(unsigned int irq, bool on);
diff --git a/arch/arm/plat-s3c24xx/include/plat/irq.h b/arch/arm/plat-s3c24xx/include/plat/irq.h
deleted file mode 100644
index ec087d6054b1..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/irq.h
+++ /dev/null
@@ -1,115 +0,0 @@
1/* linux/include/asm-arm/plat-s3c24xx/irq.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C24XX CPU IRQ support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/io.h>
14
15#include <mach/hardware.h>
16#include <mach/regs-irq.h>
17#include <mach/regs-gpio.h>
18
19#define irqdbf(x...)
20#define irqdbf2(x...)
21
22#define EXTINT_OFF (IRQ_EINT4 - 4)
23
24/* these are exported for arch/arm/mach-* usage */
25extern struct irq_chip s3c_irq_level_chip;
26extern struct irq_chip s3c_irq_chip;
27
28static inline void
29s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
30 int subcheck)
31{
32 unsigned long mask;
33 unsigned long submask;
34
35 submask = __raw_readl(S3C2410_INTSUBMSK);
36 mask = __raw_readl(S3C2410_INTMSK);
37
38 submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
39
40 /* check to see if we need to mask the parent IRQ */
41
42 if ((submask & subcheck) == subcheck) {
43 __raw_writel(mask | parentbit, S3C2410_INTMSK);
44 }
45
46 /* write back masks */
47 __raw_writel(submask, S3C2410_INTSUBMSK);
48
49}
50
51static inline void
52s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit)
53{
54 unsigned long mask;
55 unsigned long submask;
56
57 submask = __raw_readl(S3C2410_INTSUBMSK);
58 mask = __raw_readl(S3C2410_INTMSK);
59
60 submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
61 mask &= ~parentbit;
62
63 /* write back masks */
64 __raw_writel(submask, S3C2410_INTSUBMSK);
65 __raw_writel(mask, S3C2410_INTMSK);
66}
67
68
69static inline void
70s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group)
71{
72 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
73
74 s3c_irqsub_mask(irqno, parentmask, group);
75
76 __raw_writel(bit, S3C2410_SUBSRCPND);
77
78 /* only ack parent if we've got all the irqs (seems we must
79 * ack, all and hope that the irq system retriggers ok when
80 * the interrupt goes off again)
81 */
82
83 if (1) {
84 __raw_writel(parentmask, S3C2410_SRCPND);
85 __raw_writel(parentmask, S3C2410_INTPND);
86 }
87}
88
89static inline void
90s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group)
91{
92 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
93
94 __raw_writel(bit, S3C2410_SUBSRCPND);
95
96 /* only ack parent if we've got all the irqs (seems we must
97 * ack, all and hope that the irq system retriggers ok when
98 * the interrupt goes off again)
99 */
100
101 if (1) {
102 __raw_writel(parentmask, S3C2410_SRCPND);
103 __raw_writel(parentmask, S3C2410_INTPND);
104 }
105}
106
107/* exported for use in arch/arm/mach-s3c2410 */
108
109#ifdef CONFIG_PM
110extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
111#else
112#define s3c_irq_wake NULL
113#endif
114
115extern int s3c_irqext_type(struct irq_data *d, unsigned int type);
diff --git a/arch/arm/plat-s3c24xx/include/plat/mci.h b/arch/arm/plat-s3c24xx/include/plat/mci.h
deleted file mode 100644
index 2ac2b21ec490..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/mci.h
+++ /dev/null
@@ -1,52 +0,0 @@
1#ifndef _ARCH_MCI_H
2#define _ARCH_MCI_H
3
4/**
5 * struct s3c24xx_mci_pdata - sd/mmc controller platform data
6 * @no_wprotect: Set this to indicate there is no write-protect switch.
7 * @no_detect: Set this if there is no detect switch.
8 * @wprotect_invert: Invert the default sense of the write protect switch.
9 * @detect_invert: Invert the default sense of the write protect switch.
10 * @use_dma: Set to allow the use of DMA.
11 * @gpio_detect: GPIO number for the card detect line.
12 * @gpio_wprotect: GPIO number for the write protect line.
13 * @ocr_avail: The mask of the available power states, non-zero to use.
14 * @set_power: Callback to control the power mode.
15 *
16 * The @gpio_detect is used for card detection when @no_wprotect is unset,
17 * and the default sense is that 0 returned from gpio_get_value() means
18 * that a card is inserted. If @detect_invert is set, then the value from
19 * gpio_get_value() is inverted, which makes 1 mean card inserted.
20 *
21 * The driver will use @gpio_wprotect to signal whether the card is write
22 * protected if @no_wprotect is not set. A 0 returned from gpio_get_value()
23 * means the card is read/write, and 1 means read-only. The @wprotect_invert
24 * will invert the value returned from gpio_get_value().
25 *
26 * Card power is set by @ocr_availa, using MCC_VDD_ constants if it is set
27 * to a non-zero value, otherwise the default of 3.2-3.4V is used.
28 */
29struct s3c24xx_mci_pdata {
30 unsigned int no_wprotect : 1;
31 unsigned int no_detect : 1;
32 unsigned int wprotect_invert : 1;
33 unsigned int detect_invert : 1; /* set => detect active high. */
34 unsigned int use_dma : 1;
35
36 unsigned int gpio_detect;
37 unsigned int gpio_wprotect;
38 unsigned long ocr_avail;
39 void (*set_power)(unsigned char power_mode,
40 unsigned short vdd);
41};
42
43/**
44 * s3c24xx_mci_set_platdata - set platform data for mmc/sdi device
45 * @pdata: The platform data
46 *
47 * Copy the platform data supplied by @pdata so that this can be marked
48 * __initdata.
49 */
50extern void s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata);
51
52#endif /* _ARCH_NCI_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-dma.h b/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
deleted file mode 100644
index 1b0f4c36d384..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
+++ /dev/null
@@ -1,145 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/dma.h
2 *
3 * Copyright (C) 2003-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C24XX DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* DMA Register definitions */
14
15#define S3C2410_DMA_DISRC (0x00)
16#define S3C2410_DMA_DISRCC (0x04)
17#define S3C2410_DMA_DIDST (0x08)
18#define S3C2410_DMA_DIDSTC (0x0C)
19#define S3C2410_DMA_DCON (0x10)
20#define S3C2410_DMA_DSTAT (0x14)
21#define S3C2410_DMA_DCSRC (0x18)
22#define S3C2410_DMA_DCDST (0x1C)
23#define S3C2410_DMA_DMASKTRIG (0x20)
24#define S3C2412_DMA_DMAREQSEL (0x24)
25#define S3C2443_DMA_DMAREQSEL (0x24)
26
27#define S3C2410_DISRCC_INC (1<<0)
28#define S3C2410_DISRCC_APB (1<<1)
29
30#define S3C2410_DMASKTRIG_STOP (1<<2)
31#define S3C2410_DMASKTRIG_ON (1<<1)
32#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
33
34#define S3C2410_DCON_DEMAND (0<<31)
35#define S3C2410_DCON_HANDSHAKE (1<<31)
36#define S3C2410_DCON_SYNC_PCLK (0<<30)
37#define S3C2410_DCON_SYNC_HCLK (1<<30)
38
39#define S3C2410_DCON_INTREQ (1<<29)
40
41#define S3C2410_DCON_CH0_XDREQ0 (0<<24)
42#define S3C2410_DCON_CH0_UART0 (1<<24)
43#define S3C2410_DCON_CH0_SDI (2<<24)
44#define S3C2410_DCON_CH0_TIMER (3<<24)
45#define S3C2410_DCON_CH0_USBEP1 (4<<24)
46
47#define S3C2410_DCON_CH1_XDREQ1 (0<<24)
48#define S3C2410_DCON_CH1_UART1 (1<<24)
49#define S3C2410_DCON_CH1_I2SSDI (2<<24)
50#define S3C2410_DCON_CH1_SPI (3<<24)
51#define S3C2410_DCON_CH1_USBEP2 (4<<24)
52
53#define S3C2410_DCON_CH2_I2SSDO (0<<24)
54#define S3C2410_DCON_CH2_I2SSDI (1<<24)
55#define S3C2410_DCON_CH2_SDI (2<<24)
56#define S3C2410_DCON_CH2_TIMER (3<<24)
57#define S3C2410_DCON_CH2_USBEP3 (4<<24)
58
59#define S3C2410_DCON_CH3_UART2 (0<<24)
60#define S3C2410_DCON_CH3_SDI (1<<24)
61#define S3C2410_DCON_CH3_SPI (2<<24)
62#define S3C2410_DCON_CH3_TIMER (3<<24)
63#define S3C2410_DCON_CH3_USBEP4 (4<<24)
64
65#define S3C2410_DCON_SRCSHIFT (24)
66#define S3C2410_DCON_SRCMASK (7<<24)
67
68#define S3C2410_DCON_BYTE (0<<20)
69#define S3C2410_DCON_HALFWORD (1<<20)
70#define S3C2410_DCON_WORD (2<<20)
71
72#define S3C2410_DCON_AUTORELOAD (0<<22)
73#define S3C2410_DCON_NORELOAD (1<<22)
74#define S3C2410_DCON_HWTRIG (1<<23)
75
76#ifdef CONFIG_CPU_S3C2440
77#define S3C2440_DIDSTC_CHKINT (1<<2)
78
79#define S3C2440_DCON_CH0_I2SSDO (5<<24)
80#define S3C2440_DCON_CH0_PCMIN (6<<24)
81
82#define S3C2440_DCON_CH1_PCMOUT (5<<24)
83#define S3C2440_DCON_CH1_SDI (6<<24)
84
85#define S3C2440_DCON_CH2_PCMIN (5<<24)
86#define S3C2440_DCON_CH2_MICIN (6<<24)
87
88#define S3C2440_DCON_CH3_MICIN (5<<24)
89#define S3C2440_DCON_CH3_PCMOUT (6<<24)
90#endif
91
92#ifdef CONFIG_CPU_S3C2412
93
94#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1)
95
96#define S3C2412_DMAREQSEL_HW (1)
97
98#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
99#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
100#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
101#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
102#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
103#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
104#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
105#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
106#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
107#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
108#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
109#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
110#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
111#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
112#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
113#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
114#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
115#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
116#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
117#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
118
119#endif
120
121#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1)
122
123#define S3C2443_DMAREQSEL_HW (1)
124
125#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
126#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
127#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
128#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
129#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
130#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
131#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
132#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
133#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
134#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
135#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
136#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
137#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
138#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
139#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
140#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
141#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
142#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
143#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
144#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
145#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-iis.h b/arch/arm/plat-s3c24xx/include/plat/regs-iis.h
deleted file mode 100644
index cc44e0e931e9..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/regs-iis.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-iis.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 IIS register definition
11*/
12
13#ifndef __ASM_ARCH_REGS_IIS_H
14#define __ASM_ARCH_REGS_IIS_H
15
16#define S3C2410_IISCON (0x00)
17
18#define S3C2410_IISCON_LRINDEX (1<<8)
19#define S3C2410_IISCON_TXFIFORDY (1<<7)
20#define S3C2410_IISCON_RXFIFORDY (1<<6)
21#define S3C2410_IISCON_TXDMAEN (1<<5)
22#define S3C2410_IISCON_RXDMAEN (1<<4)
23#define S3C2410_IISCON_TXIDLE (1<<3)
24#define S3C2410_IISCON_RXIDLE (1<<2)
25#define S3C2410_IISCON_PSCEN (1<<1)
26#define S3C2410_IISCON_IISEN (1<<0)
27
28#define S3C2410_IISMOD (0x04)
29
30#define S3C2440_IISMOD_MPLL (1<<9)
31#define S3C2410_IISMOD_SLAVE (1<<8)
32#define S3C2410_IISMOD_NOXFER (0<<6)
33#define S3C2410_IISMOD_RXMODE (1<<6)
34#define S3C2410_IISMOD_TXMODE (2<<6)
35#define S3C2410_IISMOD_TXRXMODE (3<<6)
36#define S3C2410_IISMOD_LR_LLOW (0<<5)
37#define S3C2410_IISMOD_LR_RLOW (1<<5)
38#define S3C2410_IISMOD_IIS (0<<4)
39#define S3C2410_IISMOD_MSB (1<<4)
40#define S3C2410_IISMOD_8BIT (0<<3)
41#define S3C2410_IISMOD_16BIT (1<<3)
42#define S3C2410_IISMOD_BITMASK (1<<3)
43#define S3C2410_IISMOD_256FS (0<<2)
44#define S3C2410_IISMOD_384FS (1<<2)
45#define S3C2410_IISMOD_16FS (0<<0)
46#define S3C2410_IISMOD_32FS (1<<0)
47#define S3C2410_IISMOD_48FS (2<<0)
48#define S3C2410_IISMOD_FS_MASK (3<<0)
49
50#define S3C2410_IISPSR (0x08)
51#define S3C2410_IISPSR_INTMASK (31<<5)
52#define S3C2410_IISPSR_INTSHIFT (5)
53#define S3C2410_IISPSR_EXTMASK (31<<0)
54#define S3C2410_IISPSR_EXTSHFIT (0)
55
56#define S3C2410_IISFCON (0x0c)
57
58#define S3C2410_IISFCON_TXDMA (1<<15)
59#define S3C2410_IISFCON_RXDMA (1<<14)
60#define S3C2410_IISFCON_TXENABLE (1<<13)
61#define S3C2410_IISFCON_RXENABLE (1<<12)
62#define S3C2410_IISFCON_TXMASK (0x3f << 6)
63#define S3C2410_IISFCON_TXSHIFT (6)
64#define S3C2410_IISFCON_RXMASK (0x3f)
65#define S3C2410_IISFCON_RXSHIFT (0)
66
67#define S3C2410_IISFIFO (0x10)
68#endif /* __ASM_ARCH_REGS_IIS_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-spi.h b/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
deleted file mode 100644
index 892e2f680fca..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
+++ /dev/null
@@ -1,81 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-spi.h
2 *
3 * Copyright (c) 2004 Fetron GmbH
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * S3C2410 SPI register definition
10*/
11
12#ifndef __ASM_ARCH_REGS_SPI_H
13#define __ASM_ARCH_REGS_SPI_H
14
15#define S3C2410_SPI1 (0x20)
16#define S3C2412_SPI1 (0x100)
17
18#define S3C2410_SPCON (0x00)
19
20#define S3C2412_SPCON_RXFIFO_RB2 (0<<14)
21#define S3C2412_SPCON_RXFIFO_RB4 (1<<14)
22#define S3C2412_SPCON_RXFIFO_RB12 (2<<14)
23#define S3C2412_SPCON_RXFIFO_RB14 (3<<14)
24#define S3C2412_SPCON_TXFIFO_RB2 (0<<12)
25#define S3C2412_SPCON_TXFIFO_RB4 (1<<12)
26#define S3C2412_SPCON_TXFIFO_RB12 (2<<12)
27#define S3C2412_SPCON_TXFIFO_RB14 (3<<12)
28#define S3C2412_SPCON_RXFIFO_RESET (1<<11) /* RxFIFO reset */
29#define S3C2412_SPCON_TXFIFO_RESET (1<<10) /* TxFIFO reset */
30#define S3C2412_SPCON_RXFIFO_EN (1<<9) /* RxFIFO Enable */
31#define S3C2412_SPCON_TXFIFO_EN (1<<8) /* TxFIFO Enable */
32
33#define S3C2412_SPCON_DIRC_RX (1<<7)
34
35#define S3C2410_SPCON_SMOD_DMA (2<<5) /* DMA mode */
36#define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */
37#define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */
38#define S3C2410_SPCON_ENSCK (1<<4) /* Enable SCK */
39#define S3C2410_SPCON_MSTR (1<<3) /* Master/Slave select
40 0: slave, 1: master */
41#define S3C2410_SPCON_CPOL_HIGH (1<<2) /* Clock polarity select */
42#define S3C2410_SPCON_CPOL_LOW (0<<2) /* Clock polarity select */
43
44#define S3C2410_SPCON_CPHA_FMTB (1<<1) /* Clock Phase Select */
45#define S3C2410_SPCON_CPHA_FMTA (0<<1) /* Clock Phase Select */
46
47#define S3C2410_SPCON_TAGD (1<<0) /* Tx auto garbage data mode */
48
49
50#define S3C2410_SPSTA (0x04)
51
52#define S3C2412_SPSTA_RXFIFO_AE (1<<11)
53#define S3C2412_SPSTA_TXFIFO_AE (1<<10)
54#define S3C2412_SPSTA_RXFIFO_ERROR (1<<9)
55#define S3C2412_SPSTA_TXFIFO_ERROR (1<<8)
56#define S3C2412_SPSTA_RXFIFO_FIFO (1<<7)
57#define S3C2412_SPSTA_RXFIFO_EMPTY (1<<6)
58#define S3C2412_SPSTA_TXFIFO_NFULL (1<<5)
59#define S3C2412_SPSTA_TXFIFO_EMPTY (1<<4)
60
61#define S3C2410_SPSTA_DCOL (1<<2) /* Data Collision Error */
62#define S3C2410_SPSTA_MULD (1<<1) /* Multi Master Error */
63#define S3C2410_SPSTA_READY (1<<0) /* Data Tx/Rx ready */
64#define S3C2412_SPSTA_READY_ORG (1<<3)
65
66#define S3C2410_SPPIN (0x08)
67
68#define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */
69#define S3C2410_SPPIN_RESERVED (1<<1)
70#define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */
71
72#define S3C2410_SPPRE (0x0C)
73#define S3C2410_SPTDAT (0x10)
74#define S3C2410_SPRDAT (0x14)
75
76#define S3C2412_TXFIFO (0x18)
77#define S3C2412_RXFIFO (0x18)
78#define S3C2412_SPFIC (0x24)
79
80
81#endif /* __ASM_ARCH_REGS_SPI_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-udc.h b/arch/arm/plat-s3c24xx/include/plat/regs-udc.h
deleted file mode 100644
index f0dd4a41b37b..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/regs-udc.h
+++ /dev/null
@@ -1,153 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-udc.h
2 *
3 * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
4 *
5 * This include file is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9*/
10
11#ifndef __ASM_ARCH_REGS_UDC_H
12#define __ASM_ARCH_REGS_UDC_H
13
14#define S3C2410_USBDREG(x) (x)
15
16#define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140)
17#define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144)
18#define S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148)
19
20#define S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158)
21#define S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c)
22
23#define S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c)
24
25#define S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170)
26#define S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174)
27
28#define S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0)
29#define S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4)
30#define S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8)
31#define S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc)
32#define S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0)
33
34#define S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200)
35#define S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204)
36#define S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208)
37#define S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c)
38#define S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210)
39#define S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214)
40
41#define S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218)
42#define S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c)
43#define S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220)
44#define S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224)
45#define S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228)
46#define S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c)
47
48#define S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240)
49#define S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244)
50#define S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248)
51#define S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c)
52#define S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250)
53#define S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254)
54
55#define S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258)
56#define S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c)
57#define S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260)
58#define S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264)
59#define S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268)
60#define S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c)
61
62#define S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178)
63
64/* indexed registers */
65
66#define S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x0180)
67
68#define S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184)
69
70#define S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184)
71#define S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188)
72
73#define S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190)
74#define S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194)
75#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198)
76#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c)
77
78#define S3C2410_UDC_FUNCADDR_UPDATE (1<<7)
79
80#define S3C2410_UDC_PWR_ISOUP (1<<7) // R/W
81#define S3C2410_UDC_PWR_RESET (1<<3) // R
82#define S3C2410_UDC_PWR_RESUME (1<<2) // R/W
83#define S3C2410_UDC_PWR_SUSPEND (1<<1) // R
84#define S3C2410_UDC_PWR_ENSUSPEND (1<<0) // R/W
85
86#define S3C2410_UDC_PWR_DEFAULT 0x00
87
88#define S3C2410_UDC_INT_EP4 (1<<4) // R/W (clear only)
89#define S3C2410_UDC_INT_EP3 (1<<3) // R/W (clear only)
90#define S3C2410_UDC_INT_EP2 (1<<2) // R/W (clear only)
91#define S3C2410_UDC_INT_EP1 (1<<1) // R/W (clear only)
92#define S3C2410_UDC_INT_EP0 (1<<0) // R/W (clear only)
93
94#define S3C2410_UDC_USBINT_RESET (1<<2) // R/W (clear only)
95#define S3C2410_UDC_USBINT_RESUME (1<<1) // R/W (clear only)
96#define S3C2410_UDC_USBINT_SUSPEND (1<<0) // R/W (clear only)
97
98#define S3C2410_UDC_INTE_EP4 (1<<4) // R/W
99#define S3C2410_UDC_INTE_EP3 (1<<3) // R/W
100#define S3C2410_UDC_INTE_EP2 (1<<2) // R/W
101#define S3C2410_UDC_INTE_EP1 (1<<1) // R/W
102#define S3C2410_UDC_INTE_EP0 (1<<0) // R/W
103
104#define S3C2410_UDC_USBINTE_RESET (1<<2) // R/W
105#define S3C2410_UDC_USBINTE_SUSPEND (1<<0) // R/W
106
107
108#define S3C2410_UDC_INDEX_EP0 (0x00)
109#define S3C2410_UDC_INDEX_EP1 (0x01) // ??
110#define S3C2410_UDC_INDEX_EP2 (0x02) // ??
111#define S3C2410_UDC_INDEX_EP3 (0x03) // ??
112#define S3C2410_UDC_INDEX_EP4 (0x04) // ??
113
114#define S3C2410_UDC_ICSR1_CLRDT (1<<6) // R/W
115#define S3C2410_UDC_ICSR1_SENTSTL (1<<5) // R/W (clear only)
116#define S3C2410_UDC_ICSR1_SENDSTL (1<<4) // R/W
117#define S3C2410_UDC_ICSR1_FFLUSH (1<<3) // W (set only)
118#define S3C2410_UDC_ICSR1_UNDRUN (1<<2) // R/W (clear only)
119#define S3C2410_UDC_ICSR1_PKTRDY (1<<0) // R/W (set only)
120
121#define S3C2410_UDC_ICSR2_AUTOSET (1<<7) // R/W
122#define S3C2410_UDC_ICSR2_ISO (1<<6) // R/W
123#define S3C2410_UDC_ICSR2_MODEIN (1<<5) // R/W
124#define S3C2410_UDC_ICSR2_DMAIEN (1<<4) // R/W
125
126#define S3C2410_UDC_OCSR1_CLRDT (1<<7) // R/W
127#define S3C2410_UDC_OCSR1_SENTSTL (1<<6) // R/W (clear only)
128#define S3C2410_UDC_OCSR1_SENDSTL (1<<5) // R/W
129#define S3C2410_UDC_OCSR1_FFLUSH (1<<4) // R/W
130#define S3C2410_UDC_OCSR1_DERROR (1<<3) // R
131#define S3C2410_UDC_OCSR1_OVRRUN (1<<2) // R/W (clear only)
132#define S3C2410_UDC_OCSR1_PKTRDY (1<<0) // R/W (clear only)
133
134#define S3C2410_UDC_OCSR2_AUTOCLR (1<<7) // R/W
135#define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W
136#define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W
137
138#define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0)
139#define S3C2410_UDC_EP0_CSR_IPKRDY (1<<1)
140#define S3C2410_UDC_EP0_CSR_SENTSTL (1<<2)
141#define S3C2410_UDC_EP0_CSR_DE (1<<3)
142#define S3C2410_UDC_EP0_CSR_SE (1<<4)
143#define S3C2410_UDC_EP0_CSR_SENDSTL (1<<5)
144#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1<<6)
145#define S3C2410_UDC_EP0_CSR_SSE (1<<7)
146
147#define S3C2410_UDC_MAXP_8 (1<<0)
148#define S3C2410_UDC_MAXP_16 (1<<1)
149#define S3C2410_UDC_MAXP_32 (1<<2)
150#define S3C2410_UDC_MAXP_64 (1<<3)
151
152
153#endif
diff --git a/arch/arm/plat-s3c24xx/include/plat/udc.h b/arch/arm/plat-s3c24xx/include/plat/udc.h
deleted file mode 100644
index f63884242506..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/udc.h
+++ /dev/null
@@ -1,57 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/udc.h
2 *
3 * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 *
11 * Changelog:
12 * 14-Mar-2005 RTP Created file
13 * 02-Aug-2005 RTP File rename
14 * 07-Sep-2005 BJD Minor cleanups, changed cmd to enum
15 * 18-Jan-2007 HMW Add per-platform vbus_draw function
16*/
17
18#ifndef __ASM_ARM_ARCH_UDC_H
19#define __ASM_ARM_ARCH_UDC_H
20
21enum s3c2410_udc_cmd_e {
22 S3C2410_UDC_P_ENABLE = 1, /* Pull-up enable */
23 S3C2410_UDC_P_DISABLE = 2, /* Pull-up disable */
24 S3C2410_UDC_P_RESET = 3, /* UDC reset, in case of */
25};
26
27struct s3c2410_udc_mach_info {
28 void (*udc_command)(enum s3c2410_udc_cmd_e);
29 void (*vbus_draw)(unsigned int ma);
30
31 unsigned int pullup_pin;
32 unsigned int pullup_pin_inverted;
33
34 unsigned int vbus_pin;
35 unsigned char vbus_pin_inverted;
36};
37
38extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
39
40/**
41 * s3c24xx_hsudc_platdata - Platform data for USB High-Speed gadget controller.
42 * @epnum: Number of endpoints to be instantiated by the controller driver.
43 * @gpio_init: Platform specific USB related GPIO initialization.
44 * @gpio_uninit: Platform specific USB releted GPIO uninitialzation.
45 *
46 * Representation of platform data for the S3C24XX USB 2.0 High Speed gadget
47 * controllers.
48 */
49struct s3c24xx_hsudc_platdata {
50 unsigned int epnum;
51 void (*gpio_init)(void);
52 void (*gpio_uninit)(void);
53};
54
55extern void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd);
56
57#endif /* __ASM_ARM_ARCH_UDC_H */
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