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authorThomas Gleixner <tglx@linutronix.de>2011-03-24 08:25:22 -0400
committerThomas Gleixner <tglx@linutronix.de>2011-03-29 08:47:57 -0400
commit6845664a6a7d443f03883db59d10749d38d98b8e (patch)
tree4b4499f4d41f24152190220d93ea186fbf991fca /arch/arm/plat-s3c24xx
parent25a5662a13e604d86b0a9fd71703582a7393d8ec (diff)
arm: Cleanup the irq namespace
Convert to the new function names. Automated with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/arm/plat-s3c24xx')
-rw-r--r--arch/arm/plat-s3c24xx/irq.c44
1 files changed, 22 insertions, 22 deletions
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index 4434cb56bd9a..c2a42d526635 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -592,8 +592,8 @@ void __init s3c24xx_init_irq(void)
592 case IRQ_UART1: 592 case IRQ_UART1:
593 case IRQ_UART2: 593 case IRQ_UART2:
594 case IRQ_ADCPARENT: 594 case IRQ_ADCPARENT:
595 set_irq_chip(irqno, &s3c_irq_level_chip); 595 irq_set_chip(irqno, &s3c_irq_level_chip);
596 set_irq_handler(irqno, handle_level_irq); 596 irq_set_handler(irqno, handle_level_irq);
597 break; 597 break;
598 598
599 case IRQ_RESERVED6: 599 case IRQ_RESERVED6:
@@ -603,35 +603,35 @@ void __init s3c24xx_init_irq(void)
603 603
604 default: 604 default:
605 //irqdbf("registering irq %d (s3c irq)\n", irqno); 605 //irqdbf("registering irq %d (s3c irq)\n", irqno);
606 set_irq_chip(irqno, &s3c_irq_chip); 606 irq_set_chip(irqno, &s3c_irq_chip);
607 set_irq_handler(irqno, handle_edge_irq); 607 irq_set_handler(irqno, handle_edge_irq);
608 set_irq_flags(irqno, IRQF_VALID); 608 set_irq_flags(irqno, IRQF_VALID);
609 } 609 }
610 } 610 }
611 611
612 /* setup the cascade irq handlers */ 612 /* setup the cascade irq handlers */
613 613
614 set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7); 614 irq_set_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
615 set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8); 615 irq_set_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);
616 616
617 set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0); 617 irq_set_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
618 set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1); 618 irq_set_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
619 set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2); 619 irq_set_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
620 set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc); 620 irq_set_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
621 621
622 /* external interrupts */ 622 /* external interrupts */
623 623
624 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { 624 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
625 irqdbf("registering irq %d (ext int)\n", irqno); 625 irqdbf("registering irq %d (ext int)\n", irqno);
626 set_irq_chip(irqno, &s3c_irq_eint0t4); 626 irq_set_chip(irqno, &s3c_irq_eint0t4);
627 set_irq_handler(irqno, handle_edge_irq); 627 irq_set_handler(irqno, handle_edge_irq);
628 set_irq_flags(irqno, IRQF_VALID); 628 set_irq_flags(irqno, IRQF_VALID);
629 } 629 }
630 630
631 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) { 631 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
632 irqdbf("registering irq %d (extended s3c irq)\n", irqno); 632 irqdbf("registering irq %d (extended s3c irq)\n", irqno);
633 set_irq_chip(irqno, &s3c_irqext_chip); 633 irq_set_chip(irqno, &s3c_irqext_chip);
634 set_irq_handler(irqno, handle_edge_irq); 634 irq_set_handler(irqno, handle_edge_irq);
635 set_irq_flags(irqno, IRQF_VALID); 635 set_irq_flags(irqno, IRQF_VALID);
636 } 636 }
637 637
@@ -641,29 +641,29 @@ void __init s3c24xx_init_irq(void)
641 641
642 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) { 642 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
643 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno); 643 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
644 set_irq_chip(irqno, &s3c_irq_uart0); 644 irq_set_chip(irqno, &s3c_irq_uart0);
645 set_irq_handler(irqno, handle_level_irq); 645 irq_set_handler(irqno, handle_level_irq);
646 set_irq_flags(irqno, IRQF_VALID); 646 set_irq_flags(irqno, IRQF_VALID);
647 } 647 }
648 648
649 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) { 649 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
650 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno); 650 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
651 set_irq_chip(irqno, &s3c_irq_uart1); 651 irq_set_chip(irqno, &s3c_irq_uart1);
652 set_irq_handler(irqno, handle_level_irq); 652 irq_set_handler(irqno, handle_level_irq);
653 set_irq_flags(irqno, IRQF_VALID); 653 set_irq_flags(irqno, IRQF_VALID);
654 } 654 }
655 655
656 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) { 656 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
657 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno); 657 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
658 set_irq_chip(irqno, &s3c_irq_uart2); 658 irq_set_chip(irqno, &s3c_irq_uart2);
659 set_irq_handler(irqno, handle_level_irq); 659 irq_set_handler(irqno, handle_level_irq);
660 set_irq_flags(irqno, IRQF_VALID); 660 set_irq_flags(irqno, IRQF_VALID);
661 } 661 }
662 662
663 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) { 663 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
664 irqdbf("registering irq %d (s3c adc irq)\n", irqno); 664 irqdbf("registering irq %d (s3c adc irq)\n", irqno);
665 set_irq_chip(irqno, &s3c_irq_adc); 665 irq_set_chip(irqno, &s3c_irq_adc);
666 set_irq_handler(irqno, handle_edge_irq); 666 irq_set_handler(irqno, handle_edge_irq);
667 set_irq_flags(irqno, IRQF_VALID); 667 set_irq_flags(irqno, IRQF_VALID);
668 } 668 }
669 669