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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2009-03-26 18:44:43 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-03-26 18:44:43 -0400
commitf5f0e17a8475dee913f362510e6a8ab987d27b9f (patch)
treeebe44e7774400730f6c15cd5a84187113c274e3d /arch/arm/plat-s3c24xx
parent2f3ec501ba1e1a68ab9d413f143bdc8f46417fc1 (diff)
parentfff94cd9f5527bbba13aa5ea5719d16531ca8e65 (diff)
Merge branch 'next-s3c-pm' of git://aeryn.fluff.org.uk/bjdooks/linux into devel
Diffstat (limited to 'arch/arm/plat-s3c24xx')
-rw-r--r--arch/arm/plat-s3c24xx/Makefile1
-rw-r--r--arch/arm/plat-s3c24xx/common-smdk.c2
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/irq.h6
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/map.h2
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/pm-core.h59
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/pm.h73
-rw-r--r--arch/arm/plat-s3c24xx/irq-pm.c95
-rw-r--r--arch/arm/plat-s3c24xx/irq.c152
-rw-r--r--arch/arm/plat-s3c24xx/pm-simtec.c2
-rw-r--r--arch/arm/plat-s3c24xx/pm.c503
-rw-r--r--arch/arm/plat-s3c24xx/s3c244x.c4
-rw-r--r--arch/arm/plat-s3c24xx/sleep.S43
12 files changed, 210 insertions, 732 deletions
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index 1e0767b266b8..636cb12711df 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_CPU_S3C244X) += s3c244x-irq.o
27obj-$(CONFIG_CPU_S3C244X) += s3c244x-clock.o 27obj-$(CONFIG_CPU_S3C244X) += s3c244x-clock.o
28obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o 28obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
29obj-$(CONFIG_PM) += pm.o 29obj-$(CONFIG_PM) += pm.o
30obj-$(CONFIG_PM) += irq-pm.o
30obj-$(CONFIG_PM) += sleep.o 31obj-$(CONFIG_PM) += sleep.o
31obj-$(CONFIG_HAVE_PWM) += pwm.o 32obj-$(CONFIG_HAVE_PWM) += pwm.o
32obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o 33obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index 3d4837021ac7..1a8347cec20a 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -201,5 +201,5 @@ void __init smdk_machine_init(void)
201 201
202 platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs)); 202 platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs));
203 203
204 s3c2410_pm_init(); 204 s3c_pm_init();
205} 205}
diff --git a/arch/arm/plat-s3c24xx/include/plat/irq.h b/arch/arm/plat-s3c24xx/include/plat/irq.h
index 45746a995343..69e1be8bec35 100644
--- a/arch/arm/plat-s3c24xx/include/plat/irq.h
+++ b/arch/arm/plat-s3c24xx/include/plat/irq.h
@@ -10,6 +10,12 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11*/ 11*/
12 12
13#include <linux/io.h>
14
15#include <mach/hardware.h>
16#include <mach/regs-irq.h>
17#include <mach/regs-gpio.h>
18
13#define irqdbf(x...) 19#define irqdbf(x...)
14#define irqdbf2(x...) 20#define irqdbf2(x...)
15 21
diff --git a/arch/arm/plat-s3c24xx/include/plat/map.h b/arch/arm/plat-s3c24xx/include/plat/map.h
index fef8ea8b8e1e..eed8f78e7593 100644
--- a/arch/arm/plat-s3c24xx/include/plat/map.h
+++ b/arch/arm/plat-s3c24xx/include/plat/map.h
@@ -31,6 +31,8 @@
31#define S3C24XX_SZ_UART SZ_1M 31#define S3C24XX_SZ_UART SZ_1M
32#define S3C_UART_OFFSET (0x4000) 32#define S3C_UART_OFFSET (0x4000)
33 33
34#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
35
34/* Timers */ 36/* Timers */
35#define S3C24XX_VA_TIMER S3C_VA_TIMER 37#define S3C24XX_VA_TIMER S3C_VA_TIMER
36#define S3C2410_PA_TIMER (0x51000000) 38#define S3C2410_PA_TIMER (0x51000000)
diff --git a/arch/arm/plat-s3c24xx/include/plat/pm-core.h b/arch/arm/plat-s3c24xx/include/plat/pm-core.h
new file mode 100644
index 000000000000..c75882113e04
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/pm-core.h
@@ -0,0 +1,59 @@
1/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C24xx - PM core support for arch/arm/plat-s3c/pm.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14static inline void s3c_pm_debug_init_uart(void)
15{
16 unsigned long tmp = __raw_readl(S3C2410_CLKCON);
17
18 /* re-start uart clocks */
19 tmp |= S3C2410_CLKCON_UART0;
20 tmp |= S3C2410_CLKCON_UART1;
21 tmp |= S3C2410_CLKCON_UART2;
22
23 __raw_writel(tmp, S3C2410_CLKCON);
24 udelay(10);
25}
26
27static inline void s3c_pm_arch_prepare_irqs(void)
28{
29 __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
30 __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
31
32 /* ack any outstanding external interrupts before we go to sleep */
33
34 __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
35 __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
36 __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
37
38}
39
40static inline void s3c_pm_arch_stop_clocks(void)
41{
42 __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */
43}
44
45static void s3c_pm_show_resume_irqs(int start, unsigned long which,
46 unsigned long mask);
47
48static inline void s3c_pm_arch_show_resume_irqs(void)
49{
50 S3C_PMDBG("post sleep: IRQs 0x%08x, 0x%08x\n",
51 __raw_readl(S3C2410_SRCPND),
52 __raw_readl(S3C2410_EINTPEND));
53
54 s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
55 s3c_irqwake_intmask);
56
57 s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
58 s3c_irqwake_eintmask);
59}
diff --git a/arch/arm/plat-s3c24xx/include/plat/pm.h b/arch/arm/plat-s3c24xx/include/plat/pm.h
deleted file mode 100644
index cc623667e48a..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/pm.h
+++ /dev/null
@@ -1,73 +0,0 @@
1/* linux/include/asm-arm/plat-s3c24xx/pm.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Written by Ben Dooks, <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11/* s3c2410_pm_init
12 *
13 * called from board at initialisation time to setup the power
14 * management
15*/
16
17#ifdef CONFIG_PM
18
19extern __init int s3c2410_pm_init(void);
20
21#else
22
23static inline int s3c2410_pm_init(void)
24{
25 return 0;
26}
27#endif
28
29/* configuration for the IRQ mask over sleep */
30extern unsigned long s3c_irqwake_intmask;
31extern unsigned long s3c_irqwake_eintmask;
32
33/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
34extern unsigned long s3c_irqwake_intallow;
35extern unsigned long s3c_irqwake_eintallow;
36
37/* per-cpu sleep functions */
38
39extern void (*pm_cpu_prep)(void);
40extern void (*pm_cpu_sleep)(void);
41
42/* Flags for PM Control */
43
44extern unsigned long s3c_pm_flags;
45
46/* from sleep.S */
47
48extern int s3c2410_cpu_save(unsigned long *saveblk);
49extern void s3c2410_cpu_suspend(void);
50extern void s3c2410_cpu_resume(void);
51
52extern unsigned long s3c2410_sleep_save_phys;
53
54/* sleep save info */
55
56struct sleep_save {
57 void __iomem *reg;
58 unsigned long val;
59};
60
61#define SAVE_ITEM(x) \
62 { .reg = (x) }
63
64extern void s3c2410_pm_do_save(struct sleep_save *ptr, int count);
65extern void s3c2410_pm_do_restore(struct sleep_save *ptr, int count);
66
67#ifdef CONFIG_PM
68extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state);
69extern int s3c24xx_irq_resume(struct sys_device *dev);
70#else
71#define s3c24xx_irq_suspend NULL
72#define s3c24xx_irq_resume NULL
73#endif
diff --git a/arch/arm/plat-s3c24xx/irq-pm.c b/arch/arm/plat-s3c24xx/irq-pm.c
new file mode 100644
index 000000000000..b7acf1a8ecd2
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/irq-pm.c
@@ -0,0 +1,95 @@
1/* linux/arch/arm/plat-s3c24xx/irq-om.c
2 *
3 * Copyright (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C24XX - IRQ PM code
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/sysdev.h>
18
19#include <plat/cpu.h>
20#include <plat/pm.h>
21#include <plat/irq.h>
22
23/* state for IRQs over sleep */
24
25/* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
26 *
27 * set bit to 1 in allow bitfield to enable the wakeup settings on it
28*/
29
30unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
31unsigned long s3c_irqwake_eintallow = 0x0000fff0L;
32
33int s3c_irq_wake(unsigned int irqno, unsigned int state)
34{
35 unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
36
37 if (!(s3c_irqwake_intallow & irqbit))
38 return -ENOENT;
39
40 printk(KERN_INFO "wake %s for irq %d\n",
41 state ? "enabled" : "disabled", irqno);
42
43 if (!state)
44 s3c_irqwake_intmask |= irqbit;
45 else
46 s3c_irqwake_intmask &= ~irqbit;
47
48 return 0;
49}
50
51static struct sleep_save irq_save[] = {
52 SAVE_ITEM(S3C2410_INTMSK),
53 SAVE_ITEM(S3C2410_INTSUBMSK),
54};
55
56/* the extint values move between the s3c2410/s3c2440 and the s3c2412
57 * so we use an array to hold them, and to calculate the address of
58 * the register at run-time
59*/
60
61static unsigned long save_extint[3];
62static unsigned long save_eintflt[4];
63static unsigned long save_eintmask;
64
65int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
66{
67 unsigned int i;
68
69 for (i = 0; i < ARRAY_SIZE(save_extint); i++)
70 save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4));
71
72 for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
73 save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4));
74
75 s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
76 save_eintmask = __raw_readl(S3C24XX_EINTMASK);
77
78 return 0;
79}
80
81int s3c24xx_irq_resume(struct sys_device *dev)
82{
83 unsigned int i;
84
85 for (i = 0; i < ARRAY_SIZE(save_extint); i++)
86 __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4));
87
88 for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
89 __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4));
90
91 s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
92 __raw_writel(save_eintmask, S3C24XX_EINTMASK);
93
94 return 0;
95}
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index 0192ecdc1442..958737775ad2 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -1,6 +1,6 @@
1/* linux/arch/arm/plat-s3c24xx/irq.c 1/* linux/arch/arm/plat-s3c24xx/irq.c
2 * 2 *
3 * Copyright (c) 2003,2004 Simtec Electronics 3 * Copyright (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
@@ -16,38 +16,6 @@
16 * You should have received a copy of the GNU General Public License 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * Changelog:
21 *
22 * 22-Jul-2004 Ben Dooks <ben@simtec.co.uk>
23 * Fixed compile warnings
24 *
25 * 22-Jul-2004 Roc Wu <cooloney@yahoo.com.cn>
26 * Fixed s3c_extirq_type
27 *
28 * 21-Jul-2004 Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
29 * Addition of ADC/TC demux
30 *
31 * 04-Oct-2004 Klaus Fetscher <k.fetscher@fetron.de>
32 * Fix for set_irq_type() on low EINT numbers
33 *
34 * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk>
35 * Tidy up KF's patch and sort out new release
36 *
37 * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk>
38 * Add support for power management controls
39 *
40 * 04-Nov-2004 Ben Dooks
41 * Fix standard IRQ wake for EINT0..4 and RTC
42 *
43 * 22-Feb-2005 Ben Dooks
44 * Fixed edge-triggering on ADC IRQ
45 *
46 * 28-Jun-2005 Ben Dooks
47 * Mark IRQ_LCD valid
48 *
49 * 25-Jul-2005 Ben Dooks
50 * Split the S3C2440 IRQ code to separate file
51*/ 19*/
52 20
53#include <linux/init.h> 21#include <linux/init.h>
@@ -55,81 +23,16 @@
55#include <linux/interrupt.h> 23#include <linux/interrupt.h>
56#include <linux/ioport.h> 24#include <linux/ioport.h>
57#include <linux/sysdev.h> 25#include <linux/sysdev.h>
58#include <linux/io.h>
59 26
60#include <mach/hardware.h>
61#include <asm/irq.h> 27#include <asm/irq.h>
62
63#include <asm/mach/irq.h> 28#include <asm/mach/irq.h>
64 29
65#include <plat/regs-irqtype.h> 30#include <plat/regs-irqtype.h>
66#include <mach/regs-irq.h>
67#include <mach/regs-gpio.h>
68 31
69#include <plat/cpu.h> 32#include <plat/cpu.h>
70#include <plat/pm.h> 33#include <plat/pm.h>
71#include <plat/irq.h> 34#include <plat/irq.h>
72 35
73/* wakeup irq control */
74
75#ifdef CONFIG_PM
76
77/* state for IRQs over sleep */
78
79/* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
80 *
81 * set bit to 1 in allow bitfield to enable the wakeup settings on it
82*/
83
84unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
85unsigned long s3c_irqwake_intmask = 0xffffffffL;
86unsigned long s3c_irqwake_eintallow = 0x0000fff0L;
87unsigned long s3c_irqwake_eintmask = 0xffffffffL;
88
89int
90s3c_irq_wake(unsigned int irqno, unsigned int state)
91{
92 unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
93
94 if (!(s3c_irqwake_intallow & irqbit))
95 return -ENOENT;
96
97 printk(KERN_INFO "wake %s for irq %d\n",
98 state ? "enabled" : "disabled", irqno);
99
100 if (!state)
101 s3c_irqwake_intmask |= irqbit;
102 else
103 s3c_irqwake_intmask &= ~irqbit;
104
105 return 0;
106}
107
108static int
109s3c_irqext_wake(unsigned int irqno, unsigned int state)
110{
111 unsigned long bit = 1L << (irqno - EXTINT_OFF);
112
113 if (!(s3c_irqwake_eintallow & bit))
114 return -ENOENT;
115
116 printk(KERN_INFO "wake %s for irq %d\n",
117 state ? "enabled" : "disabled", irqno);
118
119 if (!state)
120 s3c_irqwake_eintmask |= bit;
121 else
122 s3c_irqwake_eintmask &= ~bit;
123
124 return 0;
125}
126
127#else
128#define s3c_irqext_wake NULL
129#define s3c_irq_wake NULL
130#endif
131
132
133static void 36static void
134s3c_irq_mask(unsigned int irqno) 37s3c_irq_mask(unsigned int irqno)
135{ 38{
@@ -590,59 +493,6 @@ s3c_irq_demux_extint4t7(unsigned int irq,
590 } 493 }
591} 494}
592 495
593#ifdef CONFIG_PM
594
595static struct sleep_save irq_save[] = {
596 SAVE_ITEM(S3C2410_INTMSK),
597 SAVE_ITEM(S3C2410_INTSUBMSK),
598};
599
600/* the extint values move between the s3c2410/s3c2440 and the s3c2412
601 * so we use an array to hold them, and to calculate the address of
602 * the register at run-time
603*/
604
605static unsigned long save_extint[3];
606static unsigned long save_eintflt[4];
607static unsigned long save_eintmask;
608
609int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
610{
611 unsigned int i;
612
613 for (i = 0; i < ARRAY_SIZE(save_extint); i++)
614 save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4));
615
616 for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
617 save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4));
618
619 s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
620 save_eintmask = __raw_readl(S3C24XX_EINTMASK);
621
622 return 0;
623}
624
625int s3c24xx_irq_resume(struct sys_device *dev)
626{
627 unsigned int i;
628
629 for (i = 0; i < ARRAY_SIZE(save_extint); i++)
630 __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4));
631
632 for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
633 __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4));
634
635 s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
636 __raw_writel(save_eintmask, S3C24XX_EINTMASK);
637
638 return 0;
639}
640
641#else
642#define s3c24xx_irq_suspend NULL
643#define s3c24xx_irq_resume NULL
644#endif
645
646/* s3c24xx_init_irq 496/* s3c24xx_init_irq
647 * 497 *
648 * Initialise S3C2410 IRQ system 498 * Initialise S3C2410 IRQ system
diff --git a/arch/arm/plat-s3c24xx/pm-simtec.c b/arch/arm/plat-s3c24xx/pm-simtec.c
index 21dfa74773d1..da0d3217d3e3 100644
--- a/arch/arm/plat-s3c24xx/pm-simtec.c
+++ b/arch/arm/plat-s3c24xx/pm-simtec.c
@@ -61,7 +61,7 @@ static __init int pm_simtec_init(void)
61 61
62 __raw_writel(gstatus4, S3C2410_GSTATUS4); 62 __raw_writel(gstatus4, S3C2410_GSTATUS4);
63 63
64 return s3c2410_pm_init(); 64 return s3c_pm_init();
65} 65}
66 66
67arch_initcall(pm_simtec_init); 67arch_initcall(pm_simtec_init);
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index 34ef18e5b2a1..062a29339a91 100644
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -31,14 +31,9 @@
31#include <linux/errno.h> 31#include <linux/errno.h>
32#include <linux/time.h> 32#include <linux/time.h>
33#include <linux/interrupt.h> 33#include <linux/interrupt.h>
34#include <linux/crc32.h>
35#include <linux/ioport.h>
36#include <linux/serial_core.h> 34#include <linux/serial_core.h>
37#include <linux/io.h> 35#include <linux/io.h>
38 36
39#include <asm/cacheflush.h>
40#include <mach/hardware.h>
41
42#include <plat/regs-serial.h> 37#include <plat/regs-serial.h>
43#include <mach/regs-clock.h> 38#include <mach/regs-clock.h>
44#include <mach/regs-gpio.h> 39#include <mach/regs-gpio.h>
@@ -49,10 +44,6 @@
49 44
50#include <plat/pm.h> 45#include <plat/pm.h>
51 46
52/* for external use */
53
54unsigned long s3c_pm_flags;
55
56#define PFX "s3c24xx-pm: " 47#define PFX "s3c24xx-pm: "
57 48
58static struct sleep_save core_save[] = { 49static struct sleep_save core_save[] = {
@@ -120,328 +111,14 @@ static struct sleep_save misc_save[] = {
120 SAVE_ITEM(S3C2410_DCLKCON), 111 SAVE_ITEM(S3C2410_DCLKCON),
121}; 112};
122 113
123#ifdef CONFIG_S3C2410_PM_DEBUG
124
125#define SAVE_UART(va) \
126 SAVE_ITEM((va) + S3C2410_ULCON), \
127 SAVE_ITEM((va) + S3C2410_UCON), \
128 SAVE_ITEM((va) + S3C2410_UFCON), \
129 SAVE_ITEM((va) + S3C2410_UMCON), \
130 SAVE_ITEM((va) + S3C2410_UBRDIV)
131
132static struct sleep_save uart_save[] = {
133 SAVE_UART(S3C24XX_VA_UART0),
134 SAVE_UART(S3C24XX_VA_UART1),
135#ifndef CONFIG_CPU_S3C2400
136 SAVE_UART(S3C24XX_VA_UART2),
137#endif
138};
139
140/* debug
141 *
142 * we send the debug to printascii() to allow it to be seen if the
143 * system never wakes up from the sleep
144*/
145
146extern void printascii(const char *);
147
148void pm_dbg(const char *fmt, ...)
149{
150 va_list va;
151 char buff[256];
152
153 va_start(va, fmt);
154 vsprintf(buff, fmt, va);
155 va_end(va);
156
157 printascii(buff);
158}
159
160static void s3c2410_pm_debug_init(void)
161{
162 unsigned long tmp = __raw_readl(S3C2410_CLKCON);
163
164 /* re-start uart clocks */
165 tmp |= S3C2410_CLKCON_UART0;
166 tmp |= S3C2410_CLKCON_UART1;
167 tmp |= S3C2410_CLKCON_UART2;
168
169 __raw_writel(tmp, S3C2410_CLKCON);
170 udelay(10);
171}
172
173#define DBG(fmt...) pm_dbg(fmt)
174#else
175#define DBG(fmt...) printk(KERN_DEBUG fmt)
176
177#define s3c2410_pm_debug_init() do { } while(0)
178
179static struct sleep_save uart_save[] = {};
180#endif
181
182#if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0
183
184/* suspend checking code...
185 *
186 * this next area does a set of crc checks over all the installed
187 * memory, so the system can verify if the resume was ok.
188 *
189 * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
190 * increasing it will mean that the area corrupted will be less easy to spot,
191 * and reducing the size will cause the CRC save area to grow
192*/
193
194#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024)
195
196static u32 crc_size; /* size needed for the crc block */
197static u32 *crcs; /* allocated over suspend/resume */
198
199typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
200
201/* s3c2410_pm_run_res
202 *
203 * go thorugh the given resource list, and look for system ram
204*/
205
206static void s3c2410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
207{
208 while (ptr != NULL) {
209 if (ptr->child != NULL)
210 s3c2410_pm_run_res(ptr->child, fn, arg);
211
212 if ((ptr->flags & IORESOURCE_MEM) &&
213 strcmp(ptr->name, "System RAM") == 0) {
214 DBG("Found system RAM at %08lx..%08lx\n",
215 ptr->start, ptr->end);
216 arg = (fn)(ptr, arg);
217 }
218
219 ptr = ptr->sibling;
220 }
221}
222
223static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg)
224{
225 s3c2410_pm_run_res(&iomem_resource, fn, arg);
226}
227
228static u32 *s3c2410_pm_countram(struct resource *res, u32 *val)
229{
230 u32 size = (u32)(res->end - res->start)+1;
231
232 size += CHECK_CHUNKSIZE-1;
233 size /= CHECK_CHUNKSIZE;
234
235 DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size);
236
237 *val += size * sizeof(u32);
238 return val;
239}
240
241/* s3c2410_pm_prepare_check
242 *
243 * prepare the necessary information for creating the CRCs. This
244 * must be done before the final save, as it will require memory
245 * allocating, and thus touching bits of the kernel we do not
246 * know about.
247*/
248
249static void s3c2410_pm_check_prepare(void)
250{
251 crc_size = 0;
252
253 s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size);
254
255 DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size);
256
257 crcs = kmalloc(crc_size+4, GFP_KERNEL);
258 if (crcs == NULL)
259 printk(KERN_ERR "Cannot allocated CRC save area\n");
260}
261
262static u32 *s3c2410_pm_makecheck(struct resource *res, u32 *val)
263{
264 unsigned long addr, left;
265
266 for (addr = res->start; addr < res->end;
267 addr += CHECK_CHUNKSIZE) {
268 left = res->end - addr;
269
270 if (left > CHECK_CHUNKSIZE)
271 left = CHECK_CHUNKSIZE;
272
273 *val = crc32_le(~0, phys_to_virt(addr), left);
274 val++;
275 }
276
277 return val;
278}
279
280/* s3c2410_pm_check_store
281 *
282 * compute the CRC values for the memory blocks before the final
283 * sleep.
284*/
285
286static void s3c2410_pm_check_store(void)
287{
288 if (crcs != NULL)
289 s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs);
290}
291
292/* in_region
293 *
294 * return TRUE if the area defined by ptr..ptr+size contatins the
295 * what..what+whatsz
296*/
297
298static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
299{
300 if ((what+whatsz) < ptr)
301 return 0;
302
303 if (what > (ptr+size))
304 return 0;
305
306 return 1;
307}
308
309static u32 *s3c2410_pm_runcheck(struct resource *res, u32 *val)
310{
311 void *save_at = phys_to_virt(s3c2410_sleep_save_phys);
312 unsigned long addr;
313 unsigned long left;
314 void *ptr;
315 u32 calc;
316
317 for (addr = res->start; addr < res->end;
318 addr += CHECK_CHUNKSIZE) {
319 left = res->end - addr;
320
321 if (left > CHECK_CHUNKSIZE)
322 left = CHECK_CHUNKSIZE;
323
324 ptr = phys_to_virt(addr);
325
326 if (in_region(ptr, left, crcs, crc_size)) {
327 DBG("skipping %08lx, has crc block in\n", addr);
328 goto skip_check;
329 }
330
331 if (in_region(ptr, left, save_at, 32*4 )) {
332 DBG("skipping %08lx, has save block in\n", addr);
333 goto skip_check;
334 }
335
336 /* calculate and check the checksum */
337
338 calc = crc32_le(~0, ptr, left);
339 if (calc != *val) {
340 printk(KERN_ERR PFX "Restore CRC error at "
341 "%08lx (%08x vs %08x)\n", addr, calc, *val);
342
343 DBG("Restore CRC error at %08lx (%08x vs %08x)\n",
344 addr, calc, *val);
345 }
346
347 skip_check:
348 val++;
349 }
350
351 return val;
352}
353
354/* s3c2410_pm_check_restore
355 *
356 * check the CRCs after the restore event and free the memory used
357 * to hold them
358*/
359
360static void s3c2410_pm_check_restore(void)
361{
362 if (crcs != NULL) {
363 s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs);
364 kfree(crcs);
365 crcs = NULL;
366 }
367}
368
369#else
370
371#define s3c2410_pm_check_prepare() do { } while(0)
372#define s3c2410_pm_check_restore() do { } while(0)
373#define s3c2410_pm_check_store() do { } while(0)
374#endif
375
376/* helper functions to save and restore register state */
377
378void s3c2410_pm_do_save(struct sleep_save *ptr, int count)
379{
380 for (; count > 0; count--, ptr++) {
381 ptr->val = __raw_readl(ptr->reg);
382 DBG("saved %p value %08lx\n", ptr->reg, ptr->val);
383 }
384}
385
386/* s3c2410_pm_do_restore
387 *
388 * restore the system from the given list of saved registers
389 *
390 * Note, we do not use DBG() in here, as the system may not have
391 * restore the UARTs state yet
392*/
393
394void s3c2410_pm_do_restore(struct sleep_save *ptr, int count)
395{
396 for (; count > 0; count--, ptr++) {
397 printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
398 ptr->reg, ptr->val, __raw_readl(ptr->reg));
399
400 __raw_writel(ptr->val, ptr->reg);
401 }
402}
403
404/* s3c2410_pm_do_restore_core
405 *
406 * similar to s3c2410_pm_do_restore_core
407 *
408 * WARNING: Do not put any debug in here that may effect memory or use
409 * peripherals, as things may be changing!
410*/
411
412static void s3c2410_pm_do_restore_core(struct sleep_save *ptr, int count)
413{
414 for (; count > 0; count--, ptr++) {
415 __raw_writel(ptr->val, ptr->reg);
416 }
417}
418 114
419/* s3c2410_pm_show_resume_irqs 115/* s3c_pm_check_resume_pin
420 *
421 * print any IRQs asserted at resume time (ie, we woke from)
422*/
423
424static void s3c2410_pm_show_resume_irqs(int start, unsigned long which,
425 unsigned long mask)
426{
427 int i;
428
429 which &= ~mask;
430
431 for (i = 0; i <= 31; i++) {
432 if ((which) & (1L<<i)) {
433 DBG("IRQ %d asserted at resume\n", start+i);
434 }
435 }
436}
437
438/* s3c2410_pm_check_resume_pin
439 * 116 *
440 * check to see if the pin is configured correctly for sleep mode, and 117 * check to see if the pin is configured correctly for sleep mode, and
441 * make any necessary adjustments if it is not 118 * make any necessary adjustments if it is not
442*/ 119*/
443 120
444static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs) 121static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
445{ 122{
446 unsigned long irqstate; 123 unsigned long irqstate;
447 unsigned long pinstate; 124 unsigned long pinstate;
@@ -456,21 +133,21 @@ static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
456 133
457 if (!irqstate) { 134 if (!irqstate) {
458 if (pinstate == S3C2410_GPIO_IRQ) 135 if (pinstate == S3C2410_GPIO_IRQ)
459 DBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin); 136 S3C_PMDBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
460 } else { 137 } else {
461 if (pinstate == S3C2410_GPIO_IRQ) { 138 if (pinstate == S3C2410_GPIO_IRQ) {
462 DBG("Disabling IRQ %d (pin %d)\n", irq, pin); 139 S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin);
463 s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT); 140 s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
464 } 141 }
465 } 142 }
466} 143}
467 144
468/* s3c2410_pm_configure_extint 145/* s3c_pm_configure_extint
469 * 146 *
470 * configure all external interrupt pins 147 * configure all external interrupt pins
471*/ 148*/
472 149
473static void s3c2410_pm_configure_extint(void) 150void s3c_pm_configure_extint(void)
474{ 151{
475 int pin; 152 int pin;
476 153
@@ -480,11 +157,11 @@ static void s3c2410_pm_configure_extint(void)
480 */ 157 */
481 158
482 for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) { 159 for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) {
483 s3c2410_pm_check_resume_pin(pin, pin - S3C2410_GPF0); 160 s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
484 } 161 }
485 162
486 for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) { 163 for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
487 s3c2410_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8); 164 s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
488 } 165 }
489} 166}
490 167
@@ -494,12 +171,12 @@ static void s3c2410_pm_configure_extint(void)
494#define OFFS_DAT (S3C2410_GPADAT - S3C2410_GPACON) 171#define OFFS_DAT (S3C2410_GPADAT - S3C2410_GPACON)
495#define OFFS_UP (S3C2410_GPBUP - S3C2410_GPBCON) 172#define OFFS_UP (S3C2410_GPBUP - S3C2410_GPBCON)
496 173
497/* s3c2410_pm_save_gpios() 174/* s3c_pm_save_gpios()
498 * 175 *
499 * Save the state of the GPIOs 176 * Save the state of the GPIOs
500 */ 177 */
501 178
502static void s3c2410_pm_save_gpios(void) 179void s3c_pm_save_gpios(void)
503{ 180{
504 struct gpio_sleep *gps = gpio_save; 181 struct gpio_sleep *gps = gpio_save;
505 unsigned int gpio; 182 unsigned int gpio;
@@ -538,7 +215,10 @@ static inline int is_out(unsigned long con)
538 return con == 1; 215 return con == 1;
539} 216}
540 217
541/* s3c2410_pm_restore_gpio() 218/**
219 * s3c2410_pm_restore_gpio() - restore the given GPIO bank
220 * @index: The number of the GPIO bank being resumed.
221 * @gps: The sleep confgiuration for the bank.
542 * 222 *
543 * Restore one of the GPIO banks that was saved during suspend. This is 223 * Restore one of the GPIO banks that was saved during suspend. This is
544 * not as simple as once thought, due to the possibility of glitches 224 * not as simple as once thought, due to the possibility of glitches
@@ -646,8 +326,8 @@ static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps)
646 __raw_writel(gps->gpup, base + OFFS_UP); 326 __raw_writel(gps->gpup, base + OFFS_UP);
647 } 327 }
648 328
649 DBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n", 329 S3C_PMDBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n",
650 index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); 330 index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
651} 331}
652 332
653 333
@@ -656,7 +336,7 @@ static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps)
656 * Restore the state of the GPIOs 336 * Restore the state of the GPIOs
657 */ 337 */
658 338
659static void s3c2410_pm_restore_gpios(void) 339void s3c_pm_restore_gpios(void)
660{ 340{
661 struct gpio_sleep *gps = gpio_save; 341 struct gpio_sleep *gps = gpio_save;
662 int gpio; 342 int gpio;
@@ -666,150 +346,15 @@ static void s3c2410_pm_restore_gpios(void)
666 } 346 }
667} 347}
668 348
669void (*pm_cpu_prep)(void); 349void s3c_pm_restore_core(void)
670void (*pm_cpu_sleep)(void);
671
672#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
673
674/* s3c2410_pm_enter
675 *
676 * central control for sleep/resume process
677*/
678
679static int s3c2410_pm_enter(suspend_state_t state)
680{ 350{
681 unsigned long regs_save[16]; 351 s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
682 352 s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
683 /* ensure the debug is initialised (if enabled) */
684
685 s3c2410_pm_debug_init();
686
687 DBG("s3c2410_pm_enter(%d)\n", state);
688
689 if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
690 printk(KERN_ERR PFX "error: no cpu sleep functions set\n");
691 return -EINVAL;
692 }
693
694 /* check if we have anything to wake-up with... bad things seem
695 * to happen if you suspend with no wakeup (system will often
696 * require a full power-cycle)
697 */
698
699 if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
700 !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
701 printk(KERN_ERR PFX "No sources enabled for wake-up!\n");
702 printk(KERN_ERR PFX "Aborting sleep\n");
703 return -EINVAL;
704 }
705
706 /* prepare check area if configured */
707
708 s3c2410_pm_check_prepare();
709
710 /* store the physical address of the register recovery block */
711
712 s3c2410_sleep_save_phys = virt_to_phys(regs_save);
713
714 DBG("s3c2410_sleep_save_phys=0x%08lx\n", s3c2410_sleep_save_phys);
715
716 /* save all necessary core registers not covered by the drivers */
717
718 s3c2410_pm_save_gpios();
719 s3c2410_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
720 s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save));
721 s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
722
723 /* set the irq configuration for wake */
724
725 s3c2410_pm_configure_extint();
726
727 DBG("sleep: irq wakeup masks: %08lx,%08lx\n",
728 s3c_irqwake_intmask, s3c_irqwake_eintmask);
729
730 __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
731 __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
732
733 /* ack any outstanding external interrupts before we go to sleep */
734
735 __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
736 __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
737 __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
738
739 /* call cpu specific preparation */
740
741 pm_cpu_prep();
742
743 /* flush cache back to ram */
744
745 flush_cache_all();
746
747 s3c2410_pm_check_store();
748
749 /* send the cpu to sleep... */
750
751 __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */
752
753 /* s3c2410_cpu_save will also act as our return point from when
754 * we resume as it saves its own register state, so use the return
755 * code to differentiate return from save and return from sleep */
756
757 if (s3c2410_cpu_save(regs_save) == 0) {
758 flush_cache_all();
759 pm_cpu_sleep();
760 }
761
762 /* restore the cpu state */
763
764 cpu_init();
765
766 /* restore the system state */
767
768 s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
769 s3c2410_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
770 s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
771 s3c2410_pm_restore_gpios();
772
773 s3c2410_pm_debug_init();
774
775 /* check what irq (if any) restored the system */
776
777 DBG("post sleep: IRQs 0x%08x, 0x%08x\n",
778 __raw_readl(S3C2410_SRCPND),
779 __raw_readl(S3C2410_EINTPEND));
780
781 s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
782 s3c_irqwake_intmask);
783
784 s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
785 s3c_irqwake_eintmask);
786
787 DBG("post sleep, preparing to return\n");
788
789 s3c2410_pm_check_restore();
790
791 /* ok, let's return from sleep */
792
793 DBG("S3C2410 PM Resume (post-restore)\n");
794 return 0;
795} 353}
796 354
797static struct platform_suspend_ops s3c2410_pm_ops = { 355void s3c_pm_save_core(void)
798 .enter = s3c2410_pm_enter,
799 .valid = suspend_valid_only_mem,
800};
801
802/* s3c2410_pm_init
803 *
804 * Attach the power management functions. This should be called
805 * from the board specific initialisation if the board supports
806 * it.
807*/
808
809int __init s3c2410_pm_init(void)
810{ 356{
811 printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n"); 357 s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
812 358 s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
813 suspend_set_ops(&s3c2410_pm_ops);
814 return 0;
815} 359}
360
diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c
index c1de6bb0101b..1364317d421e 100644
--- a/arch/arm/plat-s3c24xx/s3c244x.c
+++ b/arch/arm/plat-s3c24xx/s3c244x.c
@@ -145,13 +145,13 @@ static struct sleep_save s3c244x_sleep[] = {
145 145
146static int s3c244x_suspend(struct sys_device *dev, pm_message_t state) 146static int s3c244x_suspend(struct sys_device *dev, pm_message_t state)
147{ 147{
148 s3c2410_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); 148 s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
149 return 0; 149 return 0;
150} 150}
151 151
152static int s3c244x_resume(struct sys_device *dev) 152static int s3c244x_resume(struct sys_device *dev)
153{ 153{
154 s3c2410_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); 154 s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
155 return 0; 155 return 0;
156} 156}
157 157
diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S
index 76594b212802..e73e3b6e88d2 100644
--- a/arch/arm/plat-s3c24xx/sleep.S
+++ b/arch/arm/plat-s3c24xx/sleep.S
@@ -41,25 +41,13 @@
41 41
42 .text 42 .text
43 43
44 /* s3c2410_cpu_save 44 /* s3c_cpu_save
45 *
46 * save enough of the CPU state to allow us to re-start
47 * pm.c code. as we store items like the sp/lr, we will
48 * end up returning from this function when the cpu resumes
49 * so the return value is set to mark this.
50 *
51 * This arangement means we avoid having to flush the cache
52 * from this code.
53 * 45 *
54 * entry: 46 * entry:
55 * r0 = pointer to save block 47 * r0 = save address (virtual addr of s3c_sleep_save_phys)
56 *
57 * exit:
58 * r0 = 0 => we stored everything
59 * 1 => resumed from sleep
60 */ 48 */
61 49
62ENTRY(s3c2410_cpu_save) 50ENTRY(s3c_cpu_save)
63 stmfd sp!, { r4 - r12, lr } 51 stmfd sp!, { r4 - r12, lr }
64 52
65 @@ store co-processor registers 53 @@ store co-processor registers
@@ -71,20 +59,25 @@ ENTRY(s3c2410_cpu_save)
71 59
72 stmia r0, { r4 - r13 } 60 stmia r0, { r4 - r13 }
73 61
74 mov r0, #0 62 @@ write our state back to RAM
75 ldmfd sp, { r4 - r12, pc } 63 bl s3c_pm_cb_flushcache
76 64
65 @@ jump to final code to send system to sleep
66 ldr r0, =pm_cpu_sleep
67 @@ldr pc, [ r0 ]
68 ldr r0, [ r0 ]
69 mov pc, r0
70
77 @@ return to the caller, after having the MMU 71 @@ return to the caller, after having the MMU
78 @@ turned on, this restores the last bits from the 72 @@ turned on, this restores the last bits from the
79 @@ stack 73 @@ stack
80resume_with_mmu: 74resume_with_mmu:
81 mov r0, #1
82 ldmfd sp!, { r4 - r12, pc } 75 ldmfd sp!, { r4 - r12, pc }
83 76
84 .ltorg 77 .ltorg
85 78
86 @@ the next bits sit in the .data segment, even though they 79 @@ the next bits sit in the .data segment, even though they
87 @@ happen to be code... the s3c2410_sleep_save_phys needs to be 80 @@ happen to be code... the s3c_sleep_save_phys needs to be
88 @@ accessed by the resume code before it can restore the MMU. 81 @@ accessed by the resume code before it can restore the MMU.
89 @@ This means that the variable has to be close enough for the 82 @@ This means that the variable has to be close enough for the
90 @@ code to read it... since the .text segment needs to be RO, 83 @@ code to read it... since the .text segment needs to be RO,
@@ -92,19 +85,19 @@ resume_with_mmu:
92 85
93 .data 86 .data
94 87
95 .global s3c2410_sleep_save_phys 88 .global s3c_sleep_save_phys
96s3c2410_sleep_save_phys: 89s3c_sleep_save_phys:
97 .word 0 90 .word 0
98 91
99 92
100 /* sleep magic, to allow the bootloader to check for an valid 93 /* sleep magic, to allow the bootloader to check for an valid
101 * image to resume to. Must be the first word before the 94 * image to resume to. Must be the first word before the
102 * s3c2410_cpu_resume entry. 95 * s3c_cpu_resume entry.
103 */ 96 */
104 97
105 .word 0x2bedf00d 98 .word 0x2bedf00d
106 99
107 /* s3c2410_cpu_resume 100 /* s3c_cpu_resume
108 * 101 *
109 * resume code entry for bootloader to call 102 * resume code entry for bootloader to call
110 * 103 *
@@ -113,7 +106,7 @@ s3c2410_sleep_save_phys:
113 * must not write to the code segment (code is read-only) 106 * must not write to the code segment (code is read-only)
114 */ 107 */
115 108
116ENTRY(s3c2410_cpu_resume) 109ENTRY(s3c_cpu_resume)
117 mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE 110 mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
118 msr cpsr_c, r0 111 msr cpsr_c, r0
119 112
@@ -145,7 +138,7 @@ ENTRY(s3c2410_cpu_resume)
145 mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs 138 mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs
146 mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches 139 mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches
147 140
148 ldr r0, s3c2410_sleep_save_phys @ address of restore block 141 ldr r0, s3c_sleep_save_phys @ address of restore block
149 ldmia r0, { r4 - r13 } 142 ldmia r0, { r4 - r13 }
150 143
151 mcr p15, 0, r4, c13, c0, 0 @ PID 144 mcr p15, 0, r4, c13, c0, 0 @ PID
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 09:59:31 -0500