diff options
author | Ben Dooks <ben-linux@fluff.org> | 2008-12-11 19:24:19 -0500 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2009-03-08 08:37:05 -0400 |
commit | ef30e14420df546bc6576b00f9caf3379b6699d1 (patch) | |
tree | 8037b6f610fee43c8b71088dd0a6d65d7d6df937 /arch/arm/plat-s3c24xx | |
parent | 4e59c25dcbc1f033d043f1009a7f6aaa1f2aef26 (diff) |
[ARM] S3C: Rename sleep.S functions to be non-cpu specific
Rename s3c2410_cpu_resume to s3c_cpu_resume and s3c2410_cpu_save to
s3c_cpu_save to remove the CPU specific naming of these functions
which are now in the generic PM code.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c24xx')
-rw-r--r-- | arch/arm/plat-s3c24xx/sleep.S | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S index 7c1955ff3171..ecb830be67d6 100644 --- a/arch/arm/plat-s3c24xx/sleep.S +++ b/arch/arm/plat-s3c24xx/sleep.S | |||
@@ -41,7 +41,7 @@ | |||
41 | 41 | ||
42 | .text | 42 | .text |
43 | 43 | ||
44 | /* s3c2410_cpu_save | 44 | /* s3c_cpu_save |
45 | * | 45 | * |
46 | * save enough of the CPU state to allow us to re-start | 46 | * save enough of the CPU state to allow us to re-start |
47 | * pm.c code. as we store items like the sp/lr, we will | 47 | * pm.c code. as we store items like the sp/lr, we will |
@@ -59,7 +59,7 @@ | |||
59 | * 1 => resumed from sleep | 59 | * 1 => resumed from sleep |
60 | */ | 60 | */ |
61 | 61 | ||
62 | ENTRY(s3c2410_cpu_save) | 62 | ENTRY(s3c_cpu_save) |
63 | stmfd sp!, { r4 - r12, lr } | 63 | stmfd sp!, { r4 - r12, lr } |
64 | 64 | ||
65 | @@ store co-processor registers | 65 | @@ store co-processor registers |
@@ -99,12 +99,12 @@ s3c_sleep_save_phys: | |||
99 | 99 | ||
100 | /* sleep magic, to allow the bootloader to check for an valid | 100 | /* sleep magic, to allow the bootloader to check for an valid |
101 | * image to resume to. Must be the first word before the | 101 | * image to resume to. Must be the first word before the |
102 | * s3c2410_cpu_resume entry. | 102 | * s3c_cpu_resume entry. |
103 | */ | 103 | */ |
104 | 104 | ||
105 | .word 0x2bedf00d | 105 | .word 0x2bedf00d |
106 | 106 | ||
107 | /* s3c2410_cpu_resume | 107 | /* s3c_cpu_resume |
108 | * | 108 | * |
109 | * resume code entry for bootloader to call | 109 | * resume code entry for bootloader to call |
110 | * | 110 | * |
@@ -113,7 +113,7 @@ s3c_sleep_save_phys: | |||
113 | * must not write to the code segment (code is read-only) | 113 | * must not write to the code segment (code is read-only) |
114 | */ | 114 | */ |
115 | 115 | ||
116 | ENTRY(s3c2410_cpu_resume) | 116 | ENTRY(s3c_cpu_resume) |
117 | mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE | 117 | mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE |
118 | msr cpsr_c, r0 | 118 | msr cpsr_c, r0 |
119 | 119 | ||