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authorBen Dooks <ben-linux@fluff.org>2008-04-15 19:15:20 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-04-17 12:04:41 -0400
commit3c7d9c81e1302c244180e62999a08ca95b175cf5 (patch)
treea67961f6c0435e0a1965df9770433c73cdfe1664 /arch/arm/plat-s3c24xx
parentd96a980441a70168a8ead0a0f23c4c63725da5fa (diff)
[ARM] 4987/1: S3C24XX: Ensure watchdog reset initiated from cached code.
There seems to be some problem with at-least the S3C2440 and bus traffic during an reset. It is unlikely, but still possible that the system will hang in such a way that the watchdog cannot get the system out of the state it is in. Change to making the code that calls the watchdog reset run from cached memory so that instruction fetches have quiesced before the watchdog fires. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/plat-s3c24xx')
-rw-r--r--arch/arm/plat-s3c24xx/cpu.c27
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index f513ab083b8f..f5699cadb0c3 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -28,15 +28,19 @@
28#include <linux/ioport.h> 28#include <linux/ioport.h>
29#include <linux/serial_core.h> 29#include <linux/serial_core.h>
30#include <linux/platform_device.h> 30#include <linux/platform_device.h>
31#include <linux/delay.h>
31 32
32#include <asm/hardware.h> 33#include <asm/hardware.h>
33#include <asm/irq.h> 34#include <asm/irq.h>
34#include <asm/io.h> 35#include <asm/io.h>
35#include <asm/delay.h> 36#include <asm/delay.h>
37#include <asm/cacheflush.h>
36 38
37#include <asm/mach/arch.h> 39#include <asm/mach/arch.h>
38#include <asm/mach/map.h> 40#include <asm/mach/map.h>
39 41
42#include <asm/arch/system-reset.h>
43
40#include <asm/arch/regs-gpio.h> 44#include <asm/arch/regs-gpio.h>
41#include <asm/plat-s3c/regs-serial.h> 45#include <asm/plat-s3c/regs-serial.h>
42 46
@@ -203,6 +207,27 @@ static unsigned long s3c24xx_read_idcode_v4(void)
203#endif 207#endif
204} 208}
205 209
210/* Hook for arm_pm_restart to ensure we execute the reset code
211 * with the caches enabled. It seems at least the S3C2440 has a problem
212 * resetting if there is bus activity interrupted by the reset.
213 */
214static void s3c24xx_pm_restart(char mode)
215{
216 if (mode != 's') {
217 unsigned long flags;
218
219 local_irq_save(flags);
220 __cpuc_flush_kern_all();
221 __cpuc_flush_user_all();
222
223 arch_reset(mode);
224 local_irq_restore(flags);
225 }
226
227 /* fallback, or unhandled */
228 arm_machine_restart(mode);
229}
230
206void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) 231void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
207{ 232{
208 unsigned long idcode = 0x0; 233 unsigned long idcode = 0x0;
@@ -230,6 +255,8 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
230 panic("Unsupported S3C24XX CPU"); 255 panic("Unsupported S3C24XX CPU");
231 } 256 }
232 257
258 arm_pm_restart = s3c24xx_pm_restart;
259
233 (cpu->map_io)(mach_desc, size); 260 (cpu->map_io)(mach_desc, size);
234} 261}
235 262