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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-05-17 03:49:25 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-05-17 03:49:25 -0400
commita3685f00652af83f12b63e3b4ef48f29581ba48b (patch)
tree18ec9eed3deabf3c6b9bec206765a4dd0d8cf9ec /arch/arm/plat-s3c24xx
parentb12f3cbd7a9a869eae1eb108da02526b132ba80b (diff)
parent63b1f51b2405573d47bf5b9ab6e7cd5c697d3dcc (diff)
Merge branch 'for-rmk/2635' of git://git.fluff.org/bjdooks/linux into devel-stable
Diffstat (limited to 'arch/arm/plat-s3c24xx')
-rw-r--r--arch/arm/plat-s3c24xx/Kconfig7
-rw-r--r--arch/arm/plat-s3c24xx/Makefile1
-rw-r--r--arch/arm/plat-s3c24xx/common-smdk.c9
-rw-r--r--arch/arm/plat-s3c24xx/cpu.c21
-rw-r--r--arch/arm/plat-s3c24xx/gpio.c144
-rw-r--r--arch/arm/plat-s3c24xx/gpiolib.c60
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/pll.h25
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/s3c2416.h31
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/s3c2443.h19
-rw-r--r--arch/arm/plat-s3c24xx/pm.c9
-rw-r--r--arch/arm/plat-s3c24xx/s3c2410-clock.c15
-rw-r--r--arch/arm/plat-s3c24xx/s3c2443-clock.c472
-rw-r--r--arch/arm/plat-s3c24xx/setup-i2c.c5
-rw-r--r--arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c16
-rw-r--r--arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c16
-rw-r--r--arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c16
16 files changed, 692 insertions, 174 deletions
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 6e93ef8f3d43..3ce8f010b3c6 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -9,6 +9,7 @@ config PLAT_S3C24XX
9 select NO_IOPORT 9 select NO_IOPORT
10 select ARCH_REQUIRE_GPIOLIB 10 select ARCH_REQUIRE_GPIOLIB
11 select S3C_DEVICE_NAND 11 select S3C_DEVICE_NAND
12 select S3C_GPIO_CFG_S3C24XX
12 help 13 help
13 Base platform code for any Samsung S3C24XX device 14 Base platform code for any Samsung S3C24XX device
14 15
@@ -44,6 +45,12 @@ config S3C2410_CLOCK
44 Clock code for the S3C2410, and similar processors which 45 Clock code for the S3C2410, and similar processors which
45 is currently includes the S3C2410, S3C2440, S3C2442. 46 is currently includes the S3C2410, S3C2440, S3C2442.
46 47
48config S3C2443_CLOCK
49 bool
50 help
51 Clock code for the S3C2443 and similar processors, which includes
52 the S3C2416 and S3C2450.
53
47config S3C24XX_DCLK 54config S3C24XX_DCLK
48 bool 55 bool
49 help 56 help
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index c2237c41141f..44aea8868f89 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_PM) += pm.o
30obj-$(CONFIG_PM) += irq-pm.o 30obj-$(CONFIG_PM) += irq-pm.o
31obj-$(CONFIG_PM) += sleep.o 31obj-$(CONFIG_PM) += sleep.o
32obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o 32obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o
33obj-$(CONFIG_S3C2443_CLOCK) += s3c2443-clock.o
33obj-$(CONFIG_S3C2410_DMA) += dma.o 34obj-$(CONFIG_S3C2410_DMA) += dma.o
34obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o 35obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o
35obj-$(CONFIG_S3C2412_IOTIMING) += s3c2412-iotiming.o 36obj-$(CONFIG_S3C2412_IOTIMING) += s3c2412-iotiming.o
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index 9e0e20ad2e46..7b44d0c592b5 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -42,6 +42,7 @@
42#include <plat/nand.h> 42#include <plat/nand.h>
43 43
44#include <plat/common-smdk.h> 44#include <plat/common-smdk.h>
45#include <plat/gpio-cfg.h>
45#include <plat/devs.h> 46#include <plat/devs.h>
46#include <plat/pm.h> 47#include <plat/pm.h>
47 48
@@ -185,10 +186,10 @@ void __init smdk_machine_init(void)
185{ 186{
186 /* Configure the LEDs (even if we have no LED support)*/ 187 /* Configure the LEDs (even if we have no LED support)*/
187 188
188 s3c2410_gpio_cfgpin(S3C2410_GPF(4), S3C2410_GPIO_OUTPUT); 189 s3c_gpio_cfgpin(S3C2410_GPF(4), S3C2410_GPIO_OUTPUT);
189 s3c2410_gpio_cfgpin(S3C2410_GPF(5), S3C2410_GPIO_OUTPUT); 190 s3c_gpio_cfgpin(S3C2410_GPF(5), S3C2410_GPIO_OUTPUT);
190 s3c2410_gpio_cfgpin(S3C2410_GPF(6), S3C2410_GPIO_OUTPUT); 191 s3c_gpio_cfgpin(S3C2410_GPF(6), S3C2410_GPIO_OUTPUT);
191 s3c2410_gpio_cfgpin(S3C2410_GPF(7), S3C2410_GPIO_OUTPUT); 192 s3c_gpio_cfgpin(S3C2410_GPF(7), S3C2410_GPIO_OUTPUT);
192 193
193 s3c2410_gpio_setpin(S3C2410_GPF(4), 1); 194 s3c2410_gpio_setpin(S3C2410_GPF(4), 1);
194 s3c2410_gpio_setpin(S3C2410_GPF(5), 1); 195 s3c2410_gpio_setpin(S3C2410_GPF(5), 1);
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 9ca64df35bf6..76d0858c3cbb 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -49,6 +49,7 @@
49#include <plat/s3c2400.h> 49#include <plat/s3c2400.h>
50#include <plat/s3c2410.h> 50#include <plat/s3c2410.h>
51#include <plat/s3c2412.h> 51#include <plat/s3c2412.h>
52#include <plat/s3c2416.h>
52#include <plat/s3c244x.h> 53#include <plat/s3c244x.h>
53#include <plat/s3c2443.h> 54#include <plat/s3c2443.h>
54 55
@@ -57,6 +58,7 @@
57static const char name_s3c2400[] = "S3C2400"; 58static const char name_s3c2400[] = "S3C2400";
58static const char name_s3c2410[] = "S3C2410"; 59static const char name_s3c2410[] = "S3C2410";
59static const char name_s3c2412[] = "S3C2412"; 60static const char name_s3c2412[] = "S3C2412";
61static const char name_s3c2416[] = "S3C2416/S3C2450";
60static const char name_s3c2440[] = "S3C2440"; 62static const char name_s3c2440[] = "S3C2440";
61static const char name_s3c2442[] = "S3C2442"; 63static const char name_s3c2442[] = "S3C2442";
62static const char name_s3c2442b[] = "S3C2442B"; 64static const char name_s3c2442b[] = "S3C2442B";
@@ -137,6 +139,15 @@ static struct cpu_table cpu_ids[] __initdata = {
137 .init = s3c2412_init, 139 .init = s3c2412_init,
138 .name = name_s3c2412, 140 .name = name_s3c2412,
139 }, 141 },
142 { /* a strange version of the s3c2416 */
143 .idcode = 0x32450003,
144 .idmask = 0xffffffff,
145 .map_io = s3c2416_map_io,
146 .init_clocks = s3c2416_init_clocks,
147 .init_uarts = s3c2416_init_uarts,
148 .init = s3c2416_init,
149 .name = name_s3c2416,
150 },
140 { 151 {
141 .idcode = 0x32443001, 152 .idcode = 0x32443001,
142 .idmask = 0xffffffff, 153 .idmask = 0xffffffff,
@@ -170,6 +181,16 @@ static struct map_desc s3c_iodesc[] __initdata = {
170 181
171static unsigned long s3c24xx_read_idcode_v5(void) 182static unsigned long s3c24xx_read_idcode_v5(void)
172{ 183{
184#if defined(CONFIG_CPU_S3C2416)
185 /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
186
187 u32 gs = __raw_readl(S3C24XX_GSTATUS1);
188
189 /* test for s3c2416 or similar device */
190 if ((gs >> 16) == 0x3245)
191 return gs;
192#endif
193
173#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) 194#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
174 return __raw_readl(S3C2412_GSTATUS1); 195 return __raw_readl(S3C2412_GSTATUS1);
175#else 196#else
diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c
index 5467470badfd..45126d3aafc6 100644
--- a/arch/arm/plat-s3c24xx/gpio.c
+++ b/arch/arm/plat-s3c24xx/gpio.c
@@ -1,6 +1,6 @@
1/* linux/arch/arm/plat-s3c24xx/gpio.c 1/* linux/arch/arm/plat-s3c24xx/gpio.c
2 * 2 *
3 * Copyright (c) 2004-2005 Simtec Electronics 3 * Copyright (c) 2004-2010 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
5 * 5 *
6 * S3C24XX GPIO support 6 * S3C24XX GPIO support
@@ -20,12 +20,12 @@
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21*/ 21*/
22 22
23
24#include <linux/kernel.h> 23#include <linux/kernel.h>
25#include <linux/init.h> 24#include <linux/init.h>
26#include <linux/module.h> 25#include <linux/module.h>
27#include <linux/interrupt.h> 26#include <linux/interrupt.h>
28#include <linux/ioport.h> 27#include <linux/ioport.h>
28#include <linux/gpio.h>
29#include <linux/io.h> 29#include <linux/io.h>
30 30
31#include <mach/hardware.h> 31#include <mach/hardware.h>
@@ -34,123 +34,34 @@
34 34
35#include <mach/regs-gpio.h> 35#include <mach/regs-gpio.h>
36 36
37void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function) 37/* gpiolib wrappers until these are totally eliminated */
38{
39 void __iomem *base = S3C24XX_GPIO_BASE(pin);
40 unsigned long mask;
41 unsigned long con;
42 unsigned long flags;
43
44 if (pin < S3C2410_GPIO_BANKB) {
45 mask = 1 << S3C2410_GPIO_OFFSET(pin);
46 } else {
47 mask = 3 << S3C2410_GPIO_OFFSET(pin)*2;
48 }
49
50 switch (function) {
51 case S3C2410_GPIO_LEAVE:
52 mask = 0;
53 function = 0;
54 break;
55
56 case S3C2410_GPIO_INPUT:
57 case S3C2410_GPIO_OUTPUT:
58 case S3C2410_GPIO_SFN2:
59 case S3C2410_GPIO_SFN3:
60 if (pin < S3C2410_GPIO_BANKB) {
61 function -= 1;
62 function &= 1;
63 function <<= S3C2410_GPIO_OFFSET(pin);
64 } else {
65 function &= 3;
66 function <<= S3C2410_GPIO_OFFSET(pin)*2;
67 }
68 }
69
70 /* modify the specified register wwith IRQs off */
71
72 local_irq_save(flags);
73
74 con = __raw_readl(base + 0x00);
75 con &= ~mask;
76 con |= function;
77
78 __raw_writel(con, base + 0x00);
79
80 local_irq_restore(flags);
81}
82
83EXPORT_SYMBOL(s3c2410_gpio_cfgpin);
84
85unsigned int s3c2410_gpio_getcfg(unsigned int pin)
86{
87 void __iomem *base = S3C24XX_GPIO_BASE(pin);
88 unsigned long val = __raw_readl(base);
89
90 if (pin < S3C2410_GPIO_BANKB) {
91 val >>= S3C2410_GPIO_OFFSET(pin);
92 val &= 1;
93 val += 1;
94 } else {
95 val >>= S3C2410_GPIO_OFFSET(pin)*2;
96 val &= 3;
97 }
98
99 return val | S3C2410_GPIO_INPUT;
100}
101
102EXPORT_SYMBOL(s3c2410_gpio_getcfg);
103 38
104void s3c2410_gpio_pullup(unsigned int pin, unsigned int to) 39void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
105{ 40{
106 void __iomem *base = S3C24XX_GPIO_BASE(pin); 41 int ret;
107 unsigned long offs = S3C2410_GPIO_OFFSET(pin);
108 unsigned long flags;
109 unsigned long up;
110 42
111 if (pin < S3C2410_GPIO_BANKB) 43 WARN_ON(to); /* should be none of these left */
112 return;
113 44
114 local_irq_save(flags); 45 if (!to) {
115 46 /* if pull is enabled, try first with up, and if that
116 up = __raw_readl(base + 0x08); 47 * fails, try using down */
117 up &= ~(1L << offs);
118 up |= to << offs;
119 __raw_writel(up, base + 0x08);
120 48
121 local_irq_restore(flags); 49 ret = s3c_gpio_setpull(pin, S3C_GPIO_PULL_UP);
50 if (ret)
51 s3c_gpio_setpull(pin, S3C_GPIO_PULL_DOWN);
52 } else {
53 s3c_gpio_setpull(pin, S3C_GPIO_PULL_NONE);
54 }
122} 55}
123
124EXPORT_SYMBOL(s3c2410_gpio_pullup); 56EXPORT_SYMBOL(s3c2410_gpio_pullup);
125 57
126int s3c2410_gpio_getpull(unsigned int pin)
127{
128 void __iomem *base = S3C24XX_GPIO_BASE(pin);
129 unsigned long offs = S3C2410_GPIO_OFFSET(pin);
130
131 if (pin < S3C2410_GPIO_BANKB)
132 return -EINVAL;
133
134 return (__raw_readl(base + 0x08) & (1L << offs)) ? 1 : 0;
135}
136
137EXPORT_SYMBOL(s3c2410_gpio_getpull);
138
139void s3c2410_gpio_setpin(unsigned int pin, unsigned int to) 58void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
140{ 59{
141 void __iomem *base = S3C24XX_GPIO_BASE(pin); 60 /* do this via gpiolib until all users removed */
142 unsigned long offs = S3C2410_GPIO_OFFSET(pin);
143 unsigned long flags;
144 unsigned long dat;
145
146 local_irq_save(flags);
147 61
148 dat = __raw_readl(base + 0x04); 62 gpio_request(pin, "temporary");
149 dat &= ~(1 << offs); 63 gpio_set_value(pin, to);
150 dat |= to << offs; 64 gpio_free(pin);
151 __raw_writel(dat, base + 0x04);
152
153 local_irq_restore(flags);
154} 65}
155 66
156EXPORT_SYMBOL(s3c2410_gpio_setpin); 67EXPORT_SYMBOL(s3c2410_gpio_setpin);
@@ -181,22 +92,3 @@ unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
181} 92}
182 93
183EXPORT_SYMBOL(s3c2410_modify_misccr); 94EXPORT_SYMBOL(s3c2410_modify_misccr);
184
185int s3c2410_gpio_getirq(unsigned int pin)
186{
187 if (pin < S3C2410_GPF(0) || pin > S3C2410_GPG(15))
188 return -EINVAL; /* not valid interrupts */
189
190 if (pin < S3C2410_GPG(0) && pin > S3C2410_GPF(7))
191 return -EINVAL; /* not valid pin */
192
193 if (pin < S3C2410_GPF(4))
194 return (pin - S3C2410_GPF(0)) + IRQ_EINT0;
195
196 if (pin < S3C2410_GPG(0))
197 return (pin - S3C2410_GPF(4)) + IRQ_EINT4;
198
199 return (pin - S3C2410_GPG(0)) + IRQ_EINT8;
200}
201
202EXPORT_SYMBOL(s3c2410_gpio_getirq);
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
index 4f0f11a6a677..4c0896f2572d 100644
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -1,6 +1,6 @@
1/* linux/arch/arm/plat-s3c24xx/gpiolib.c 1/* linux/arch/arm/plat-s3c24xx/gpiolib.c
2 * 2 *
3 * Copyright (c) 2008 Simtec Electronics 3 * Copyright (c) 2008-2010 Simtec Electronics
4 * http://armlinux.simtec.co.uk/ 4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk> 5 * Ben Dooks <ben@simtec.co.uk>
6 * 6 *
@@ -21,6 +21,8 @@
21#include <linux/gpio.h> 21#include <linux/gpio.h>
22 22
23#include <plat/gpio-core.h> 23#include <plat/gpio-core.h>
24#include <plat/gpio-cfg.h>
25#include <plat/gpio-cfg-helpers.h>
24#include <mach/hardware.h> 26#include <mach/hardware.h>
25#include <asm/irq.h> 27#include <asm/irq.h>
26#include <plat/pm.h> 28#include <plat/pm.h>
@@ -77,10 +79,21 @@ static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
77 return IRQ_EINT8 + offset; 79 return IRQ_EINT8 + offset;
78} 80}
79 81
82static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = {
83 .set_config = s3c_gpio_setcfg_s3c24xx_a,
84 .get_config = s3c_gpio_getcfg_s3c24xx_a,
85};
86
87struct s3c_gpio_cfg s3c24xx_gpiocfg_default = {
88 .set_config = s3c_gpio_setcfg_s3c24xx,
89 .get_config = s3c_gpio_getcfg_s3c24xx,
90};
91
80struct s3c_gpio_chip s3c24xx_gpios[] = { 92struct s3c_gpio_chip s3c24xx_gpios[] = {
81 [0] = { 93 [0] = {
82 .base = S3C2410_GPACON, 94 .base = S3C2410_GPACON,
83 .pm = __gpio_pm(&s3c_gpio_pm_1bit), 95 .pm = __gpio_pm(&s3c_gpio_pm_1bit),
96 .config = &s3c24xx_gpiocfg_banka,
84 .chip = { 97 .chip = {
85 .base = S3C2410_GPA(0), 98 .base = S3C2410_GPA(0),
86 .owner = THIS_MODULE, 99 .owner = THIS_MODULE,
@@ -161,15 +174,58 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
161 .ngpio = 11, 174 .ngpio = 11,
162 }, 175 },
163 }, 176 },
177 /* GPIOS for the S3C2443 and later devices. */
178 {
179 .base = S3C2440_GPJCON,
180 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
181 .chip = {
182 .base = S3C2410_GPJ(0),
183 .owner = THIS_MODULE,
184 .label = "GPIOJ",
185 .ngpio = 16,
186 },
187 }, {
188 .base = S3C2443_GPKCON,
189 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
190 .chip = {
191 .base = S3C2410_GPK(0),
192 .owner = THIS_MODULE,
193 .label = "GPIOK",
194 .ngpio = 16,
195 },
196 }, {
197 .base = S3C2443_GPLCON,
198 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
199 .chip = {
200 .base = S3C2410_GPL(0),
201 .owner = THIS_MODULE,
202 .label = "GPIOL",
203 .ngpio = 15,
204 },
205 }, {
206 .base = S3C2443_GPMCON,
207 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
208 .chip = {
209 .base = S3C2410_GPM(0),
210 .owner = THIS_MODULE,
211 .label = "GPIOM",
212 .ngpio = 2,
213 },
214 },
164}; 215};
165 216
217
166static __init int s3c24xx_gpiolib_init(void) 218static __init int s3c24xx_gpiolib_init(void)
167{ 219{
168 struct s3c_gpio_chip *chip = s3c24xx_gpios; 220 struct s3c_gpio_chip *chip = s3c24xx_gpios;
169 int gpn; 221 int gpn;
170 222
171 for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) 223 for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) {
224 if (!chip->config)
225 chip->config = &s3c24xx_gpiocfg_default;
226
172 s3c_gpiolib_add(chip); 227 s3c_gpiolib_add(chip);
228 }
173 229
174 return 0; 230 return 0;
175} 231}
diff --git a/arch/arm/plat-s3c24xx/include/plat/pll.h b/arch/arm/plat-s3c24xx/include/plat/pll.h
index 7ea8bffa7a9c..005729a1077a 100644
--- a/arch/arm/plat-s3c24xx/include/plat/pll.h
+++ b/arch/arm/plat-s3c24xx/include/plat/pll.h
@@ -35,3 +35,28 @@ s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk)
35 35
36 return (unsigned int)fvco; 36 return (unsigned int)fvco;
37} 37}
38
39#define S3C2416_PLL_M_SHIFT (14)
40#define S3C2416_PLL_P_SHIFT (5)
41#define S3C2416_PLL_S_MASK (7)
42#define S3C2416_PLL_M_MASK ((1 << 10) - 1)
43#define S3C2416_PLL_P_MASK (63)
44
45static inline unsigned int
46s3c2416_get_pll(unsigned int pllval, unsigned int baseclk)
47{
48 unsigned int m, p, s;
49 uint64_t fvco;
50
51 m = pllval >> S3C2416_PLL_M_SHIFT;
52 p = pllval >> S3C2416_PLL_P_SHIFT;
53
54 s = pllval & S3C2416_PLL_S_MASK;
55 m &= S3C2416_PLL_M_MASK;
56 p &= S3C2416_PLL_P_MASK;
57
58 fvco = (uint64_t)baseclk * m;
59 do_div(fvco, (p << s));
60
61 return (unsigned int)fvco;
62}
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2416.h b/arch/arm/plat-s3c24xx/include/plat/s3c2416.h
new file mode 100644
index 000000000000..dc3c0907d221
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2416.h
@@ -0,0 +1,31 @@
1/* linux/include/asm-arm/plat-s3c24xx/s3c2443.h
2 *
3 * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>
4 *
5 * Header file for s3c2416 cpu support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifdef CONFIG_CPU_S3C2416
13
14struct s3c2410_uartcfg;
15
16extern int s3c2416_init(void);
17
18extern void s3c2416_map_io(void);
19
20extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
21
22extern void s3c2416_init_clocks(int xtal);
23
24extern int s3c2416_baseclk_add(void);
25
26#else
27#define s3c2416_init_clocks NULL
28#define s3c2416_init_uarts NULL
29#define s3c2416_map_io NULL
30#define s3c2416_init NULL
31#endif
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h b/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
index 815b107ed890..a19715feb798 100644
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
@@ -30,3 +30,22 @@ extern int s3c2443_baseclk_add(void);
30#define s3c2443_map_io NULL 30#define s3c2443_map_io NULL
31#define s3c2443_init NULL 31#define s3c2443_init NULL
32#endif 32#endif
33
34/* common code used by s3c2443 and others.
35 * note, not to be used outside of arch/arm/mach-s3c* */
36
37struct clk; /* some files don't need clk.h otherwise */
38
39typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
40typedef unsigned int (*fdiv_fn)(unsigned long clkcon0);
41
42extern void s3c2443_common_setup_clocks(pll_fn get_mpll, fdiv_fn fdiv);
43extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, fdiv_fn fdiv);
44
45extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable);
46extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable);
47extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable);
48
49extern struct clksrc_clk clk_epllref;
50extern struct clksrc_clk clk_esysclk;
51extern struct clksrc_clk clk_msysclk;
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index 3620dd299095..60627e63a254 100644
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -43,6 +43,7 @@
43 43
44#include <asm/mach/time.h> 44#include <asm/mach/time.h>
45 45
46#include <plat/gpio-cfg.h>
46#include <plat/pm.h> 47#include <plat/pm.h>
47 48
48#define PFX "s3c24xx-pm: " 49#define PFX "s3c24xx-pm: "
@@ -90,22 +91,22 @@ static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
90{ 91{
91 unsigned long irqstate; 92 unsigned long irqstate;
92 unsigned long pinstate; 93 unsigned long pinstate;
93 int irq = s3c2410_gpio_getirq(pin); 94 int irq = gpio_to_irq(pin);
94 95
95 if (irqoffs < 4) 96 if (irqoffs < 4)
96 irqstate = s3c_irqwake_intmask & (1L<<irqoffs); 97 irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
97 else 98 else
98 irqstate = s3c_irqwake_eintmask & (1L<<irqoffs); 99 irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
99 100
100 pinstate = s3c2410_gpio_getcfg(pin); 101 pinstate = s3c_gpio_getcfg(pin);
101 102
102 if (!irqstate) { 103 if (!irqstate) {
103 if (pinstate == S3C2410_GPIO_IRQ) 104 if (pinstate == S3C2410_GPIO_IRQ)
104 S3C_PMDBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin); 105 S3C_PMDBG("Leaving IRQ %d (pin %d) as is\n", irq, pin);
105 } else { 106 } else {
106 if (pinstate == S3C2410_GPIO_IRQ) { 107 if (pinstate == S3C2410_GPIO_IRQ) {
107 S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin); 108 S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin);
108 s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT); 109 s3c_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
109 } 110 }
110 } 111 }
111} 112}
diff --git a/arch/arm/plat-s3c24xx/s3c2410-clock.c b/arch/arm/plat-s3c24xx/s3c2410-clock.c
index b61bdb793734..9ecc5d913679 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2410-clock.c
@@ -87,7 +87,7 @@ static int s3c2410_upll_enable(struct clk *clk, int enable)
87 87
88/* standard clock definitions */ 88/* standard clock definitions */
89 89
90static struct clk init_clocks_disable[] = { 90static struct clk init_clocks_off[] = {
91 { 91 {
92 .name = "nand", 92 .name = "nand",
93 .id = -1, 93 .id = -1,
@@ -249,17 +249,8 @@ int __init s3c2410_baseclk_add(void)
249 249
250 /* install (and disable) the clocks we do not need immediately */ 250 /* install (and disable) the clocks we do not need immediately */
251 251
252 clkp = init_clocks_disable; 252 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
253 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { 253 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
254
255 ret = s3c24xx_register_clock(clkp);
256 if (ret < 0) {
257 printk(KERN_ERR "Failed to register clock %s (%d)\n",
258 clkp->name, ret);
259 }
260
261 s3c2410_clkcon_enable(clkp, 0);
262 }
263 254
264 /* show the clock-slow value */ 255 /* show the clock-slow value */
265 256
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
new file mode 100644
index 000000000000..461f070eb62d
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -0,0 +1,472 @@
1/* linux/arch/arm/plat-s3c24xx/s3c2443-clock.c
2 *
3 * Copyright (c) 2007, 2010 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2443 Clock control suport - common code
7 */
8
9#include <linux/init.h>
10#include <linux/clk.h>
11#include <linux/io.h>
12
13#include <mach/regs-s3c2443-clock.h>
14
15#include <plat/s3c2443.h>
16#include <plat/clock.h>
17#include <plat/clock-clksrc.h>
18#include <plat/cpu.h>
19
20#include <plat/cpu-freq.h>
21
22
23static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
24{
25 u32 ctrlbit = clk->ctrlbit;
26 u32 con = __raw_readl(reg);
27
28 if (enable)
29 con |= ctrlbit;
30 else
31 con &= ~ctrlbit;
32
33 __raw_writel(con, reg);
34 return 0;
35}
36
37int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
38{
39 return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
40}
41
42int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
43{
44 return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
45}
46
47int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
48{
49 return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
50}
51
52/* mpllref is a direct descendant of clk_xtal by default, but it is not
53 * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
54 * such directly equating the two source clocks is impossible.
55 */
56struct clk clk_mpllref = {
57 .name = "mpllref",
58 .parent = &clk_xtal,
59 .id = -1,
60};
61
62static struct clk *clk_epllref_sources[] = {
63 [0] = &clk_mpllref,
64 [1] = &clk_mpllref,
65 [2] = &clk_xtal,
66 [3] = &clk_ext,
67};
68
69struct clksrc_clk clk_epllref = {
70 .clk = {
71 .name = "epllref",
72 .id = -1,
73 },
74 .sources = &(struct clksrc_sources) {
75 .sources = clk_epllref_sources,
76 .nr_sources = ARRAY_SIZE(clk_epllref_sources),
77 },
78 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
79};
80
81/* esysclk
82 *
83 * this is sourced from either the EPLL or the EPLLref clock
84*/
85
86static struct clk *clk_sysclk_sources[] = {
87 [0] = &clk_epllref.clk,
88 [1] = &clk_epll,
89};
90
91struct clksrc_clk clk_esysclk = {
92 .clk = {
93 .name = "esysclk",
94 .parent = &clk_epll,
95 .id = -1,
96 },
97 .sources = &(struct clksrc_sources) {
98 .sources = clk_sysclk_sources,
99 .nr_sources = ARRAY_SIZE(clk_sysclk_sources),
100 },
101 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 },
102};
103
104static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
105{
106 unsigned long parent_rate = clk_get_rate(clk->parent);
107 unsigned long div = __raw_readl(S3C2443_CLKDIV0);
108
109 div &= S3C2443_CLKDIV0_EXTDIV_MASK;
110 div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */
111
112 return parent_rate / (div + 1);
113}
114
115static struct clk clk_mdivclk = {
116 .name = "mdivclk",
117 .parent = &clk_mpllref,
118 .id = -1,
119 .ops = &(struct clk_ops) {
120 .get_rate = s3c2443_getrate_mdivclk,
121 },
122};
123
124static struct clk *clk_msysclk_sources[] = {
125 [0] = &clk_mpllref,
126 [1] = &clk_mpll,
127 [2] = &clk_mdivclk,
128 [3] = &clk_mpllref,
129};
130
131struct clksrc_clk clk_msysclk = {
132 .clk = {
133 .name = "msysclk",
134 .parent = &clk_xtal,
135 .id = -1,
136 },
137 .sources = &(struct clksrc_sources) {
138 .sources = clk_msysclk_sources,
139 .nr_sources = ARRAY_SIZE(clk_msysclk_sources),
140 },
141 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 },
142};
143
144/* prediv
145 *
146 * this divides the msysclk down to pass to h/p/etc.
147 */
148
149static unsigned long s3c2443_prediv_getrate(struct clk *clk)
150{
151 unsigned long rate = clk_get_rate(clk->parent);
152 unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
153
154 clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
155 clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
156
157 return rate / (clkdiv0 + 1);
158}
159
160static struct clk clk_prediv = {
161 .name = "prediv",
162 .id = -1,
163 .parent = &clk_msysclk.clk,
164 .ops = &(struct clk_ops) {
165 .get_rate = s3c2443_prediv_getrate,
166 },
167};
168
169/* usbhost
170 *
171 * usb host bus-clock, usually 48MHz to provide USB bus clock timing
172*/
173
174static struct clksrc_clk clk_usb_bus_host = {
175 .clk = {
176 .name = "usb-bus-host-parent",
177 .id = -1,
178 .parent = &clk_esysclk.clk,
179 .ctrlbit = S3C2443_SCLKCON_USBHOST,
180 .enable = s3c2443_clkcon_enable_s,
181 },
182 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
183};
184
185/* common clksrc clocks */
186
187static struct clksrc_clk clksrc_clks[] = {
188 {
189 /* ART baud-rate clock sourced from esysclk via a divisor */
190 .clk = {
191 .name = "uartclk",
192 .id = -1,
193 .parent = &clk_esysclk.clk,
194 },
195 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
196 }, {
197 /* camera interface bus-clock, divided down from esysclk */
198 .clk = {
199 .name = "camif-upll", /* same as 2440 name */
200 .id = -1,
201 .parent = &clk_esysclk.clk,
202 .ctrlbit = S3C2443_SCLKCON_CAMCLK,
203 .enable = s3c2443_clkcon_enable_s,
204 },
205 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
206 }, {
207 .clk = {
208 .name = "display-if",
209 .id = -1,
210 .parent = &clk_esysclk.clk,
211 .ctrlbit = S3C2443_SCLKCON_DISPCLK,
212 .enable = s3c2443_clkcon_enable_s,
213 },
214 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
215 },
216};
217
218
219static struct clk init_clocks_off[] = {
220 {
221 .name = "adc",
222 .id = -1,
223 .parent = &clk_p,
224 .enable = s3c2443_clkcon_enable_p,
225 .ctrlbit = S3C2443_PCLKCON_ADC,
226 }, {
227 .name = "i2c",
228 .id = -1,
229 .parent = &clk_p,
230 .enable = s3c2443_clkcon_enable_p,
231 .ctrlbit = S3C2443_PCLKCON_IIC,
232 }
233};
234
235static struct clk init_clocks[] = {
236 {
237 .name = "dma",
238 .id = 0,
239 .parent = &clk_h,
240 .enable = s3c2443_clkcon_enable_h,
241 .ctrlbit = S3C2443_HCLKCON_DMA0,
242 }, {
243 .name = "dma",
244 .id = 1,
245 .parent = &clk_h,
246 .enable = s3c2443_clkcon_enable_h,
247 .ctrlbit = S3C2443_HCLKCON_DMA1,
248 }, {
249 .name = "dma",
250 .id = 2,
251 .parent = &clk_h,
252 .enable = s3c2443_clkcon_enable_h,
253 .ctrlbit = S3C2443_HCLKCON_DMA2,
254 }, {
255 .name = "dma",
256 .id = 3,
257 .parent = &clk_h,
258 .enable = s3c2443_clkcon_enable_h,
259 .ctrlbit = S3C2443_HCLKCON_DMA3,
260 }, {
261 .name = "dma",
262 .id = 4,
263 .parent = &clk_h,
264 .enable = s3c2443_clkcon_enable_h,
265 .ctrlbit = S3C2443_HCLKCON_DMA4,
266 }, {
267 .name = "dma",
268 .id = 5,
269 .parent = &clk_h,
270 .enable = s3c2443_clkcon_enable_h,
271 .ctrlbit = S3C2443_HCLKCON_DMA5,
272 }, {
273 .name = "hsmmc",
274 .id = 0,
275 .parent = &clk_h,
276 .enable = s3c2443_clkcon_enable_h,
277 .ctrlbit = S3C2443_HCLKCON_HSMMC,
278 }, {
279 .name = "gpio",
280 .id = -1,
281 .parent = &clk_p,
282 .enable = s3c2443_clkcon_enable_p,
283 .ctrlbit = S3C2443_PCLKCON_GPIO,
284 }, {
285 .name = "usb-host",
286 .id = -1,
287 .parent = &clk_h,
288 .enable = s3c2443_clkcon_enable_h,
289 .ctrlbit = S3C2443_HCLKCON_USBH,
290 }, {
291 .name = "usb-device",
292 .id = -1,
293 .parent = &clk_h,
294 .enable = s3c2443_clkcon_enable_h,
295 .ctrlbit = S3C2443_HCLKCON_USBD,
296 }, {
297 .name = "lcd",
298 .id = -1,
299 .parent = &clk_h,
300 .enable = s3c2443_clkcon_enable_h,
301 .ctrlbit = S3C2443_HCLKCON_LCDC,
302
303 }, {
304 .name = "timers",
305 .id = -1,
306 .parent = &clk_p,
307 .enable = s3c2443_clkcon_enable_p,
308 .ctrlbit = S3C2443_PCLKCON_PWMT,
309 }, {
310 .name = "cfc",
311 .id = -1,
312 .parent = &clk_h,
313 .enable = s3c2443_clkcon_enable_h,
314 .ctrlbit = S3C2443_HCLKCON_CFC,
315 }, {
316 .name = "ssmc",
317 .id = -1,
318 .parent = &clk_h,
319 .enable = s3c2443_clkcon_enable_h,
320 .ctrlbit = S3C2443_HCLKCON_SSMC,
321 }, {
322 .name = "uart",
323 .id = 0,
324 .parent = &clk_p,
325 .enable = s3c2443_clkcon_enable_p,
326 .ctrlbit = S3C2443_PCLKCON_UART0,
327 }, {
328 .name = "uart",
329 .id = 1,
330 .parent = &clk_p,
331 .enable = s3c2443_clkcon_enable_p,
332 .ctrlbit = S3C2443_PCLKCON_UART1,
333 }, {
334 .name = "uart",
335 .id = 2,
336 .parent = &clk_p,
337 .enable = s3c2443_clkcon_enable_p,
338 .ctrlbit = S3C2443_PCLKCON_UART2,
339 }, {
340 .name = "uart",
341 .id = 3,
342 .parent = &clk_p,
343 .enable = s3c2443_clkcon_enable_p,
344 .ctrlbit = S3C2443_PCLKCON_UART3,
345 }, {
346 .name = "rtc",
347 .id = -1,
348 .parent = &clk_p,
349 .enable = s3c2443_clkcon_enable_p,
350 .ctrlbit = S3C2443_PCLKCON_RTC,
351 }, {
352 .name = "watchdog",
353 .id = -1,
354 .parent = &clk_p,
355 .ctrlbit = S3C2443_PCLKCON_WDT,
356 }, {
357 .name = "ac97",
358 .id = -1,
359 .parent = &clk_p,
360 .ctrlbit = S3C2443_PCLKCON_AC97,
361 }, {
362 .name = "nand",
363 .id = -1,
364 .parent = &clk_h,
365 }, {
366 .name = "usb-bus-host",
367 .id = -1,
368 .parent = &clk_usb_bus_host.clk,
369 }
370};
371
372static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
373{
374 clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
375
376 return clkcon0 + 1;
377}
378
379/* EPLLCON compatible enough to get on/off information */
380
381void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll,
382 fdiv_fn get_fdiv)
383{
384 unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
385 unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
386 unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
387 struct clk *xtal_clk;
388 unsigned long xtal;
389 unsigned long pll;
390 unsigned long fclk;
391 unsigned long hclk;
392 unsigned long pclk;
393 int ptr;
394
395 xtal_clk = clk_get(NULL, "xtal");
396 xtal = clk_get_rate(xtal_clk);
397 clk_put(xtal_clk);
398
399 pll = get_mpll(mpllcon, xtal);
400 clk_msysclk.clk.rate = pll;
401
402 fclk = pll / get_fdiv(clkdiv0);
403 hclk = s3c2443_prediv_getrate(&clk_prediv);
404 hclk /= s3c2443_get_hdiv(clkdiv0);
405 pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
406
407 s3c24xx_setup_clocks(fclk, hclk, pclk);
408
409 printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
410 (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
411 print_mhz(pll), print_mhz(fclk),
412 print_mhz(hclk), print_mhz(pclk));
413
414 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
415 s3c_set_clksrc(&clksrc_clks[ptr], true);
416
417 /* ensure usb bus clock is within correct rate of 48MHz */
418
419 if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
420 printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
421 clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
422 }
423
424 printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
425 (epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
426 print_mhz(clk_get_rate(&clk_epll)),
427 print_mhz(clk_get_rate(&clk_usb_bus)));
428}
429
430static struct clk *clks[] __initdata = {
431 &clk_prediv,
432 &clk_mpllref,
433 &clk_mdivclk,
434 &clk_ext,
435 &clk_epll,
436 &clk_usb_bus,
437};
438
439static struct clksrc_clk *clksrcs[] __initdata = {
440 &clk_usb_bus_host,
441 &clk_epllref,
442 &clk_esysclk,
443 &clk_msysclk,
444};
445
446void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
447 fdiv_fn get_fdiv)
448{
449 int ptr;
450
451 /* s3c2443 parents h and p clocks from prediv */
452 clk_h.parent = &clk_prediv;
453 clk_p.parent = &clk_prediv;
454
455 clk_usb_bus.parent = &clk_usb_bus_host.clk;
456 clk_epll.parent = &clk_epllref.clk;
457
458 s3c24xx_register_baseclocks(xtal);
459 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
460
461 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
462 s3c_register_clksrc(clksrcs[ptr], 1);
463
464 s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
465 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
466
467 /* See s3c2443/etc notes on disabling clocks at init time */
468 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
469 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
470
471 s3c2443_common_setup_clocks(get_mpll, get_fdiv);
472}
diff --git a/arch/arm/plat-s3c24xx/setup-i2c.c b/arch/arm/plat-s3c24xx/setup-i2c.c
index 71a6accf114e..9e90a7cbd1d6 100644
--- a/arch/arm/plat-s3c24xx/setup-i2c.c
+++ b/arch/arm/plat-s3c24xx/setup-i2c.c
@@ -15,12 +15,13 @@
15 15
16struct platform_device; 16struct platform_device;
17 17
18#include <plat/gpio-cfg.h>
18#include <plat/iic.h> 19#include <plat/iic.h>
19#include <mach/hardware.h> 20#include <mach/hardware.h>
20#include <mach/regs-gpio.h> 21#include <mach/regs-gpio.h>
21 22
22void s3c_i2c0_cfg_gpio(struct platform_device *dev) 23void s3c_i2c0_cfg_gpio(struct platform_device *dev)
23{ 24{
24 s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPE15_IICSDA); 25 s3c_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPE15_IICSDA);
25 s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPE14_IICSCL); 26 s3c_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPE14_IICSCL);
26} 27}
diff --git a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
index da7a61728c18..9793544a6ace 100644
--- a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
+++ b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
@@ -21,16 +21,16 @@ void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
21 int enable) 21 int enable)
22{ 22{
23 if (enable) { 23 if (enable) {
24 s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPE13_SPICLK0); 24 s3c_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPE13_SPICLK0);
25 s3c2410_gpio_cfgpin(S3C2410_GPE(12), S3C2410_GPE12_SPIMOSI0); 25 s3c_gpio_cfgpin(S3C2410_GPE(12), S3C2410_GPE12_SPIMOSI0);
26 s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPE11_SPIMISO0); 26 s3c_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPE11_SPIMISO0);
27 s3c2410_gpio_pullup(S3C2410_GPE(11), 0); 27 s3c2410_gpio_pullup(S3C2410_GPE(11), 0);
28 s3c2410_gpio_pullup(S3C2410_GPE(13), 0); 28 s3c2410_gpio_pullup(S3C2410_GPE(13), 0);
29 } else { 29 } else {
30 s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPIO_INPUT); 30 s3c_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPIO_INPUT);
31 s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPIO_INPUT); 31 s3c_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPIO_INPUT);
32 s3c2410_gpio_pullup(S3C2410_GPE(11), 1); 32 s3c_gpio_cfgpull(S3C2410_GPE(11), S3C_GPIO_PULL_NONE);
33 s3c2410_gpio_pullup(S3C2410_GPE(12), 1); 33 s3c_gpio_cfgpull(S3C2410_GPE(12), S3C_GPIO_PULL_NONE);
34 s3c2410_gpio_pullup(S3C2410_GPE(13), 1); 34 s3c_gpio_cfgpull(S3C2410_GPE(13), S3C_GPIO_PULL_NONE);
35 } 35 }
36} 36}
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
index 89fcf5308cf6..db9e9e477ec1 100644
--- a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
+++ b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
@@ -23,16 +23,16 @@ void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi,
23 23
24 printk(KERN_INFO "%s(%d)\n", __func__, enable); 24 printk(KERN_INFO "%s(%d)\n", __func__, enable);
25 if (enable) { 25 if (enable) {
26 s3c2410_gpio_cfgpin(S3C2410_GPD(10), S3C2440_GPD10_SPICLK1); 26 s3c_gpio_cfgpin(S3C2410_GPD(10), S3C2440_GPD10_SPICLK1);
27 s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2440_GPD9_SPIMOSI1); 27 s3c_gpio_cfgpin(S3C2410_GPD(9), S3C2440_GPD9_SPIMOSI1);
28 s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2440_GPD8_SPIMISO1); 28 s3c_gpio_cfgpin(S3C2410_GPD(8), S3C2440_GPD8_SPIMISO1);
29 s3c2410_gpio_pullup(S3C2410_GPD(10), 0); 29 s3c2410_gpio_pullup(S3C2410_GPD(10), 0);
30 s3c2410_gpio_pullup(S3C2410_GPD(9), 0); 30 s3c2410_gpio_pullup(S3C2410_GPD(9), 0);
31 } else { 31 } else {
32 s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2410_GPIO_INPUT); 32 s3c_gpio_cfgpin(S3C2410_GPD(8), S3C2410_GPIO_INPUT);
33 s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2410_GPIO_INPUT); 33 s3c_gpio_cfgpin(S3C2410_GPD(9), S3C2410_GPIO_INPUT);
34 s3c2410_gpio_pullup(S3C2410_GPD(10), 1); 34 s3c_gpio_cfgpull(S3C2410_GPD(10), S3C_GPIO_PULL_NONE);
35 s3c2410_gpio_pullup(S3C2410_GPD(9), 1); 35 s3c_gpio_cfgpull(S3C2410_GPD(9), S3C_GPIO_PULL_NONE);
36 s3c2410_gpio_pullup(S3C2410_GPD(8), 1); 36 s3c_gpio_cfgpull(S3C2410_GPD(8), S3C_GPIO_PULL_NONE);
37 } 37 }
38} 38}
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
index 86b9edc67413..8ea663a438bb 100644
--- a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
+++ b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
@@ -21,16 +21,16 @@ void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
21 int enable) 21 int enable)
22{ 22{
23 if (enable) { 23 if (enable) {
24 s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPG7_SPICLK1); 24 s3c_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPG7_SPICLK1);
25 s3c2410_gpio_cfgpin(S3C2410_GPG(6), S3C2410_GPG6_SPIMOSI1); 25 s3c_gpio_cfgpin(S3C2410_GPG(6), S3C2410_GPG6_SPIMOSI1);
26 s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPG5_SPIMISO1); 26 s3c_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPG5_SPIMISO1);
27 s3c2410_gpio_pullup(S3C2410_GPG(5), 0); 27 s3c2410_gpio_pullup(S3C2410_GPG(5), 0);
28 s3c2410_gpio_pullup(S3C2410_GPG(6), 0); 28 s3c2410_gpio_pullup(S3C2410_GPG(6), 0);
29 } else { 29 } else {
30 s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPIO_INPUT); 30 s3c_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPIO_INPUT);
31 s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPIO_INPUT); 31 s3c_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPIO_INPUT);
32 s3c2410_gpio_pullup(S3C2410_GPG(5), 1); 32 s3c_gpio_cfgpull(S3C2410_GPG(5), S3C_GPIO_PULL_NONE);
33 s3c2410_gpio_pullup(S3C2410_GPG(6), 1); 33 s3c_gpio_cfgpull(S3C2410_GPG(6), S3C_GPIO_PULL_NONE);
34 s3c2410_gpio_pullup(S3C2410_GPG(7), 1); 34 s3c_gpio_cfgpull(S3C2410_GPG(7), S3C_GPIO_PULL_NONE);
35 } 35 }
36} 36}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 13:50:19 -0500