diff options
author | Ben Dooks <ben@simtec.co.uk> | 2009-07-30 18:23:21 -0400 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2009-07-30 18:22:51 -0400 |
commit | 2e4ea6e8209e0c1d93c69c34c32002337b3f747e (patch) | |
tree | 11f2a4291e5cfbc7444d225eedd415bc9e9d23a9 /arch/arm/plat-s3c24xx | |
parent | b0e66522f4d86713b0450255210e26c4f11ee86b (diff) |
ARM: S3C24XX: CPUFREQ: Add core support.
Add the core of the support for enabling the CPUFreq driver on
all S3C24XX based systems.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c24xx')
-rw-r--r-- | arch/arm/plat-s3c24xx/Makefile | 2 | ||||
-rw-r--r-- | arch/arm/plat-s3c24xx/cpu-freq.c | 704 | ||||
-rw-r--r-- | arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h | 183 |
3 files changed, 889 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile index 579a165c2827..1f6add552bd0 100644 --- a/arch/arm/plat-s3c24xx/Makefile +++ b/arch/arm/plat-s3c24xx/Makefile | |||
@@ -20,6 +20,8 @@ obj-y += gpiolib.o | |||
20 | obj-y += clock.o | 20 | obj-y += clock.o |
21 | obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o | 21 | obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o |
22 | 22 | ||
23 | obj-$(CONFIG_CPU_FREQ_S3C24XX) += cpu-freq.o | ||
24 | |||
23 | # Architecture dependant builds | 25 | # Architecture dependant builds |
24 | 26 | ||
25 | obj-$(CONFIG_CPU_S3C244X) += s3c244x.o | 27 | obj-$(CONFIG_CPU_S3C244X) += s3c244x.o |
diff --git a/arch/arm/plat-s3c24xx/cpu-freq.c b/arch/arm/plat-s3c24xx/cpu-freq.c new file mode 100644 index 000000000000..40ff7e2569dc --- /dev/null +++ b/arch/arm/plat-s3c24xx/cpu-freq.c | |||
@@ -0,0 +1,704 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/cpu-freq.c | ||
2 | * | ||
3 | * Copyright (c) 2006,2007,2008 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C24XX CPU Frequency scaling | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/init.h> | ||
15 | #include <linux/module.h> | ||
16 | #include <linux/interrupt.h> | ||
17 | #include <linux/ioport.h> | ||
18 | #include <linux/cpufreq.h> | ||
19 | #include <linux/cpu.h> | ||
20 | #include <linux/clk.h> | ||
21 | #include <linux/err.h> | ||
22 | #include <linux/io.h> | ||
23 | #include <linux/sysdev.h> | ||
24 | #include <linux/kobject.h> | ||
25 | #include <linux/sysfs.h> | ||
26 | |||
27 | #include <asm/mach/arch.h> | ||
28 | #include <asm/mach/map.h> | ||
29 | |||
30 | #include <plat/cpu.h> | ||
31 | #include <plat/clock.h> | ||
32 | #include <plat/cpu-freq-core.h> | ||
33 | |||
34 | #include <mach/regs-clock.h> | ||
35 | |||
36 | /* note, cpufreq support deals in kHz, no Hz */ | ||
37 | |||
38 | static struct cpufreq_driver s3c24xx_driver; | ||
39 | static struct s3c_cpufreq_config cpu_cur; | ||
40 | static struct s3c_iotimings s3c24xx_iotiming; | ||
41 | static struct cpufreq_frequency_table *pll_reg; | ||
42 | static unsigned int last_target = ~0; | ||
43 | static unsigned int ftab_size; | ||
44 | static struct cpufreq_frequency_table *ftab; | ||
45 | |||
46 | static struct clk *_clk_mpll; | ||
47 | static struct clk *_clk_xtal; | ||
48 | static struct clk *clk_fclk; | ||
49 | static struct clk *clk_hclk; | ||
50 | static struct clk *clk_pclk; | ||
51 | static struct clk *clk_arm; | ||
52 | |||
53 | static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg) | ||
54 | { | ||
55 | unsigned long fclk, pclk, hclk, armclk; | ||
56 | |||
57 | cfg->freq.fclk = fclk = clk_get_rate(clk_fclk); | ||
58 | cfg->freq.hclk = hclk = clk_get_rate(clk_hclk); | ||
59 | cfg->freq.pclk = pclk = clk_get_rate(clk_pclk); | ||
60 | cfg->freq.armclk = armclk = clk_get_rate(clk_arm); | ||
61 | |||
62 | cfg->pll.index = __raw_readl(S3C2410_MPLLCON); | ||
63 | cfg->pll.frequency = fclk; | ||
64 | |||
65 | cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); | ||
66 | |||
67 | cfg->divs.h_divisor = fclk / hclk; | ||
68 | cfg->divs.p_divisor = fclk / pclk; | ||
69 | } | ||
70 | |||
71 | static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config *cfg) | ||
72 | { | ||
73 | unsigned long pll = cfg->pll.frequency; | ||
74 | |||
75 | cfg->freq.fclk = pll; | ||
76 | cfg->freq.hclk = pll / cfg->divs.h_divisor; | ||
77 | cfg->freq.pclk = pll / cfg->divs.p_divisor; | ||
78 | |||
79 | /* convert hclk into 10ths of nanoseconds for io calcs */ | ||
80 | cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); | ||
81 | } | ||
82 | |||
83 | static inline int closer(unsigned int target, unsigned int n, unsigned int c) | ||
84 | { | ||
85 | int diff_cur = abs(target - c); | ||
86 | int diff_new = abs(target - n); | ||
87 | |||
88 | return (diff_new < diff_cur); | ||
89 | } | ||
90 | |||
91 | static void s3c_cpufreq_show(const char *pfx, | ||
92 | struct s3c_cpufreq_config *cfg) | ||
93 | { | ||
94 | s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n", | ||
95 | pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk, | ||
96 | cfg->freq.hclk, cfg->divs.h_divisor, | ||
97 | cfg->freq.pclk, cfg->divs.p_divisor); | ||
98 | } | ||
99 | |||
100 | /* functions to wrapper the driver info calls to do the cpu specific work */ | ||
101 | |||
102 | static void s3c_cpufreq_setio(struct s3c_cpufreq_config *cfg) | ||
103 | { | ||
104 | if (cfg->info->set_iotiming) | ||
105 | (cfg->info->set_iotiming)(cfg, &s3c24xx_iotiming); | ||
106 | } | ||
107 | |||
108 | static int s3c_cpufreq_calcio(struct s3c_cpufreq_config *cfg) | ||
109 | { | ||
110 | if (cfg->info->calc_iotiming) | ||
111 | return (cfg->info->calc_iotiming)(cfg, &s3c24xx_iotiming); | ||
112 | |||
113 | return 0; | ||
114 | } | ||
115 | |||
116 | static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) | ||
117 | { | ||
118 | (cfg->info->set_refresh)(cfg); | ||
119 | } | ||
120 | |||
121 | static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) | ||
122 | { | ||
123 | (cfg->info->set_divs)(cfg); | ||
124 | } | ||
125 | |||
126 | static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) | ||
127 | { | ||
128 | return (cfg->info->calc_divs)(cfg); | ||
129 | } | ||
130 | |||
131 | static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg) | ||
132 | { | ||
133 | (cfg->info->set_fvco)(cfg); | ||
134 | } | ||
135 | |||
136 | static inline void s3c_cpufreq_resume_clocks(void) | ||
137 | { | ||
138 | cpu_cur.info->resume_clocks(); | ||
139 | } | ||
140 | |||
141 | static inline void s3c_cpufreq_updateclk(struct clk *clk, | ||
142 | unsigned int freq) | ||
143 | { | ||
144 | clk_set_rate(clk, freq); | ||
145 | } | ||
146 | |||
147 | static int s3c_cpufreq_settarget(struct cpufreq_policy *policy, | ||
148 | unsigned int target_freq, | ||
149 | struct cpufreq_frequency_table *pll) | ||
150 | { | ||
151 | struct s3c_cpufreq_freqs freqs; | ||
152 | struct s3c_cpufreq_config cpu_new; | ||
153 | unsigned long flags; | ||
154 | |||
155 | cpu_new = cpu_cur; /* copy new from current */ | ||
156 | |||
157 | s3c_cpufreq_show("cur", &cpu_cur); | ||
158 | |||
159 | /* TODO - check for DMA currently outstanding */ | ||
160 | |||
161 | cpu_new.pll = pll ? *pll : cpu_cur.pll; | ||
162 | |||
163 | if (pll) | ||
164 | freqs.pll_changing = 1; | ||
165 | |||
166 | /* update our frequencies */ | ||
167 | |||
168 | cpu_new.freq.armclk = target_freq; | ||
169 | cpu_new.freq.fclk = cpu_new.pll.frequency; | ||
170 | |||
171 | if (s3c_cpufreq_calcdivs(&cpu_new) < 0) { | ||
172 | printk(KERN_ERR "no divisors for %d\n", target_freq); | ||
173 | goto err_notpossible; | ||
174 | } | ||
175 | |||
176 | s3c_freq_dbg("%s: got divs\n", __func__); | ||
177 | |||
178 | s3c_cpufreq_calc(&cpu_new); | ||
179 | |||
180 | s3c_freq_dbg("%s: calculated frequencies for new\n", __func__); | ||
181 | |||
182 | if (cpu_new.freq.hclk != cpu_cur.freq.hclk) { | ||
183 | if (s3c_cpufreq_calcio(&cpu_new) < 0) { | ||
184 | printk(KERN_ERR "%s: no IO timings\n", __func__); | ||
185 | goto err_notpossible; | ||
186 | } | ||
187 | } | ||
188 | |||
189 | s3c_cpufreq_show("new", &cpu_new); | ||
190 | |||
191 | /* setup our cpufreq parameters */ | ||
192 | |||
193 | freqs.old = cpu_cur.freq; | ||
194 | freqs.new = cpu_new.freq; | ||
195 | |||
196 | freqs.freqs.cpu = 0; | ||
197 | freqs.freqs.old = cpu_cur.freq.armclk / 1000; | ||
198 | freqs.freqs.new = cpu_new.freq.armclk / 1000; | ||
199 | |||
200 | /* update f/h/p clock settings before we issue the change | ||
201 | * notification, so that drivers do not need to do anything | ||
202 | * special if they want to recalculate on CPUFREQ_PRECHANGE. */ | ||
203 | |||
204 | s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency); | ||
205 | s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk); | ||
206 | s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk); | ||
207 | s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk); | ||
208 | |||
209 | /* start the frequency change */ | ||
210 | |||
211 | if (policy) | ||
212 | cpufreq_notify_transition(&freqs.freqs, CPUFREQ_PRECHANGE); | ||
213 | |||
214 | /* If hclk is staying the same, then we do not need to | ||
215 | * re-write the IO or the refresh timings whilst we are changing | ||
216 | * speed. */ | ||
217 | |||
218 | local_irq_save(flags); | ||
219 | |||
220 | /* is our memory clock slowing down? */ | ||
221 | if (cpu_new.freq.hclk < cpu_cur.freq.hclk) { | ||
222 | s3c_cpufreq_setrefresh(&cpu_new); | ||
223 | s3c_cpufreq_setio(&cpu_new); | ||
224 | } | ||
225 | |||
226 | if (cpu_new.freq.fclk == cpu_cur.freq.fclk) { | ||
227 | /* not changing PLL, just set the divisors */ | ||
228 | |||
229 | s3c_cpufreq_setdivs(&cpu_new); | ||
230 | } else { | ||
231 | if (cpu_new.freq.fclk < cpu_cur.freq.fclk) { | ||
232 | /* slow the cpu down, then set divisors */ | ||
233 | |||
234 | s3c_cpufreq_setfvco(&cpu_new); | ||
235 | s3c_cpufreq_setdivs(&cpu_new); | ||
236 | } else { | ||
237 | /* set the divisors, then speed up */ | ||
238 | |||
239 | s3c_cpufreq_setdivs(&cpu_new); | ||
240 | s3c_cpufreq_setfvco(&cpu_new); | ||
241 | } | ||
242 | } | ||
243 | |||
244 | /* did our memory clock speed up */ | ||
245 | if (cpu_new.freq.hclk > cpu_cur.freq.hclk) { | ||
246 | s3c_cpufreq_setrefresh(&cpu_new); | ||
247 | s3c_cpufreq_setio(&cpu_new); | ||
248 | } | ||
249 | |||
250 | /* update our current settings */ | ||
251 | cpu_cur = cpu_new; | ||
252 | |||
253 | local_irq_restore(flags); | ||
254 | |||
255 | /* notify everyone we've done this */ | ||
256 | if (policy) | ||
257 | cpufreq_notify_transition(&freqs.freqs, CPUFREQ_POSTCHANGE); | ||
258 | |||
259 | s3c_freq_dbg("%s: finished\n", __func__); | ||
260 | return 0; | ||
261 | |||
262 | err_notpossible: | ||
263 | printk(KERN_ERR "no compatible settings for %d\n", target_freq); | ||
264 | return -EINVAL; | ||
265 | } | ||
266 | |||
267 | /* s3c_cpufreq_target | ||
268 | * | ||
269 | * called by the cpufreq core to adjust the frequency that the CPU | ||
270 | * is currently running at. | ||
271 | */ | ||
272 | |||
273 | static int s3c_cpufreq_target(struct cpufreq_policy *policy, | ||
274 | unsigned int target_freq, | ||
275 | unsigned int relation) | ||
276 | { | ||
277 | struct cpufreq_frequency_table *pll; | ||
278 | unsigned int index; | ||
279 | |||
280 | /* avoid repeated calls which cause a needless amout of duplicated | ||
281 | * logging output (and CPU time as the calculation process is | ||
282 | * done) */ | ||
283 | if (target_freq == last_target) | ||
284 | return 0; | ||
285 | |||
286 | last_target = target_freq; | ||
287 | |||
288 | s3c_freq_dbg("%s: policy %p, target %u, relation %u\n", | ||
289 | __func__, policy, target_freq, relation); | ||
290 | |||
291 | if (ftab) { | ||
292 | if (cpufreq_frequency_table_target(policy, ftab, | ||
293 | target_freq, relation, | ||
294 | &index)) { | ||
295 | s3c_freq_dbg("%s: table failed\n", __func__); | ||
296 | return -EINVAL; | ||
297 | } | ||
298 | |||
299 | s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__, | ||
300 | target_freq, index, ftab[index].frequency); | ||
301 | target_freq = ftab[index].frequency; | ||
302 | } | ||
303 | |||
304 | target_freq *= 1000; /* convert target to Hz */ | ||
305 | |||
306 | /* find the settings for our new frequency */ | ||
307 | |||
308 | if (!pll_reg || cpu_cur.lock_pll) { | ||
309 | /* either we've not got any PLL values, or we've locked | ||
310 | * to the current one. */ | ||
311 | pll = NULL; | ||
312 | } else { | ||
313 | struct cpufreq_policy tmp_policy; | ||
314 | int ret; | ||
315 | |||
316 | /* we keep the cpu pll table in Hz, to ensure we get an | ||
317 | * accurate value for the PLL output. */ | ||
318 | |||
319 | tmp_policy.min = policy->min * 1000; | ||
320 | tmp_policy.max = policy->max * 1000; | ||
321 | tmp_policy.cpu = policy->cpu; | ||
322 | |||
323 | /* cpufreq_frequency_table_target uses a pointer to 'index' | ||
324 | * which is the number of the table entry, not the value of | ||
325 | * the table entry's index field. */ | ||
326 | |||
327 | ret = cpufreq_frequency_table_target(&tmp_policy, pll_reg, | ||
328 | target_freq, relation, | ||
329 | &index); | ||
330 | |||
331 | if (ret < 0) { | ||
332 | printk(KERN_ERR "%s: no PLL available\n", __func__); | ||
333 | goto err_notpossible; | ||
334 | } | ||
335 | |||
336 | pll = pll_reg + index; | ||
337 | |||
338 | s3c_freq_dbg("%s: target %u => %u\n", | ||
339 | __func__, target_freq, pll->frequency); | ||
340 | |||
341 | target_freq = pll->frequency; | ||
342 | } | ||
343 | |||
344 | return s3c_cpufreq_settarget(policy, target_freq, pll); | ||
345 | |||
346 | err_notpossible: | ||
347 | printk(KERN_ERR "no compatible settings for %d\n", target_freq); | ||
348 | return -EINVAL; | ||
349 | } | ||
350 | |||
351 | static unsigned int s3c_cpufreq_get(unsigned int cpu) | ||
352 | { | ||
353 | return clk_get_rate(clk_arm) / 1000; | ||
354 | } | ||
355 | |||
356 | struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name) | ||
357 | { | ||
358 | struct clk *clk; | ||
359 | |||
360 | clk = clk_get(dev, name); | ||
361 | if (IS_ERR(clk)) | ||
362 | printk(KERN_ERR "cpufreq: failed to get clock '%s'\n", name); | ||
363 | |||
364 | return clk; | ||
365 | } | ||
366 | |||
367 | static int s3c_cpufreq_init(struct cpufreq_policy *policy) | ||
368 | { | ||
369 | printk(KERN_INFO "%s: initialising policy %p\n", __func__, policy); | ||
370 | |||
371 | if (policy->cpu != 0) | ||
372 | return -EINVAL; | ||
373 | |||
374 | policy->cur = s3c_cpufreq_get(0); | ||
375 | policy->min = policy->cpuinfo.min_freq = 0; | ||
376 | policy->max = policy->cpuinfo.max_freq = cpu_cur.info->max.fclk / 1000; | ||
377 | policy->governor = CPUFREQ_DEFAULT_GOVERNOR; | ||
378 | |||
379 | /* feed the latency information from the cpu driver */ | ||
380 | policy->cpuinfo.transition_latency = cpu_cur.info->latency; | ||
381 | |||
382 | if (ftab) | ||
383 | cpufreq_frequency_table_cpuinfo(policy, ftab); | ||
384 | |||
385 | return 0; | ||
386 | } | ||
387 | |||
388 | static __init int s3c_cpufreq_initclks(void) | ||
389 | { | ||
390 | _clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll"); | ||
391 | _clk_xtal = s3c_cpufreq_clk_get(NULL, "xtal"); | ||
392 | clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk"); | ||
393 | clk_hclk = s3c_cpufreq_clk_get(NULL, "hclk"); | ||
394 | clk_pclk = s3c_cpufreq_clk_get(NULL, "pclk"); | ||
395 | clk_arm = s3c_cpufreq_clk_get(NULL, "armclk"); | ||
396 | |||
397 | if (IS_ERR(clk_fclk) || IS_ERR(clk_hclk) || IS_ERR(clk_pclk) || | ||
398 | IS_ERR(_clk_mpll) || IS_ERR(clk_arm) || IS_ERR(_clk_xtal)) { | ||
399 | printk(KERN_ERR "%s: could not get clock(s)\n", __func__); | ||
400 | return -ENOENT; | ||
401 | } | ||
402 | |||
403 | printk(KERN_INFO "%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n", __func__, | ||
404 | clk_get_rate(clk_fclk) / 1000, | ||
405 | clk_get_rate(clk_hclk) / 1000, | ||
406 | clk_get_rate(clk_pclk) / 1000, | ||
407 | clk_get_rate(clk_arm) / 1000); | ||
408 | |||
409 | return 0; | ||
410 | } | ||
411 | |||
412 | static int s3c_cpufreq_verify(struct cpufreq_policy *policy) | ||
413 | { | ||
414 | if (policy->cpu != 0) | ||
415 | return -EINVAL; | ||
416 | |||
417 | return 0; | ||
418 | } | ||
419 | |||
420 | #ifdef CONFIG_PM | ||
421 | static struct cpufreq_frequency_table suspend_pll; | ||
422 | static unsigned int suspend_freq; | ||
423 | |||
424 | static int s3c_cpufreq_suspend(struct cpufreq_policy *policy, pm_message_t pmsg) | ||
425 | { | ||
426 | suspend_pll.frequency = clk_get_rate(_clk_mpll); | ||
427 | suspend_pll.index = __raw_readl(S3C2410_MPLLCON); | ||
428 | suspend_freq = s3c_cpufreq_get(0) * 1000; | ||
429 | |||
430 | return 0; | ||
431 | } | ||
432 | |||
433 | static int s3c_cpufreq_resume(struct cpufreq_policy *policy) | ||
434 | { | ||
435 | int ret; | ||
436 | |||
437 | s3c_freq_dbg("%s: resuming with policy %p\n", __func__, policy); | ||
438 | |||
439 | last_target = ~0; /* invalidate last_target setting */ | ||
440 | |||
441 | /* first, find out what speed we resumed at. */ | ||
442 | s3c_cpufreq_resume_clocks(); | ||
443 | |||
444 | /* whilst we will be called later on, we try and re-set the | ||
445 | * cpu frequencies as soon as possible so that we do not end | ||
446 | * up resuming devices and then immediatley having to re-set | ||
447 | * a number of settings once these devices have restarted. | ||
448 | * | ||
449 | * as a note, it is expected devices are not used until they | ||
450 | * have been un-suspended and at that time they should have | ||
451 | * used the updated clock settings. | ||
452 | */ | ||
453 | |||
454 | ret = s3c_cpufreq_settarget(NULL, suspend_freq, &suspend_pll); | ||
455 | if (ret) { | ||
456 | printk(KERN_ERR "%s: failed to reset pll/freq\n", __func__); | ||
457 | return ret; | ||
458 | } | ||
459 | |||
460 | return 0; | ||
461 | } | ||
462 | #else | ||
463 | #define s3c_cpufreq_resume NULL | ||
464 | #define s3c_cpufreq_suspend NULL | ||
465 | #endif | ||
466 | |||
467 | static struct cpufreq_driver s3c24xx_driver = { | ||
468 | .flags = CPUFREQ_STICKY, | ||
469 | .verify = s3c_cpufreq_verify, | ||
470 | .target = s3c_cpufreq_target, | ||
471 | .get = s3c_cpufreq_get, | ||
472 | .init = s3c_cpufreq_init, | ||
473 | .suspend = s3c_cpufreq_suspend, | ||
474 | .resume = s3c_cpufreq_resume, | ||
475 | .name = "s3c24xx", | ||
476 | }; | ||
477 | |||
478 | |||
479 | int __init s3c_cpufreq_register(struct s3c_cpufreq_info *info) | ||
480 | { | ||
481 | if (!info || !info->name) { | ||
482 | printk(KERN_ERR "%s: failed to pass valid information\n", | ||
483 | __func__); | ||
484 | return -EINVAL; | ||
485 | } | ||
486 | |||
487 | printk(KERN_INFO "S3C24XX CPU Frequency driver, %s cpu support\n", | ||
488 | info->name); | ||
489 | |||
490 | /* check our driver info has valid data */ | ||
491 | |||
492 | BUG_ON(info->set_refresh == NULL); | ||
493 | BUG_ON(info->set_divs == NULL); | ||
494 | BUG_ON(info->calc_divs == NULL); | ||
495 | |||
496 | /* info->set_fvco is optional, depending on whether there | ||
497 | * is a need to set the clock code. */ | ||
498 | |||
499 | cpu_cur.info = info; | ||
500 | |||
501 | /* Note, driver registering should probably update locktime */ | ||
502 | |||
503 | return 0; | ||
504 | } | ||
505 | |||
506 | int __init s3c_cpufreq_setboard(struct s3c_cpufreq_board *board) | ||
507 | { | ||
508 | struct s3c_cpufreq_board *ours; | ||
509 | |||
510 | if (!board) { | ||
511 | printk(KERN_INFO "%s: no board data\n", __func__); | ||
512 | return -EINVAL; | ||
513 | } | ||
514 | |||
515 | /* Copy the board information so that each board can make this | ||
516 | * initdata. */ | ||
517 | |||
518 | ours = kzalloc(sizeof(struct s3c_cpufreq_board), GFP_KERNEL); | ||
519 | if (ours == NULL) { | ||
520 | printk(KERN_ERR "%s: no memory\n", __func__); | ||
521 | return -ENOMEM; | ||
522 | } | ||
523 | |||
524 | *ours = *board; | ||
525 | cpu_cur.board = ours; | ||
526 | |||
527 | return 0; | ||
528 | } | ||
529 | |||
530 | int __init s3c_cpufreq_auto_io(void) | ||
531 | { | ||
532 | int ret; | ||
533 | |||
534 | if (!cpu_cur.info->get_iotiming) { | ||
535 | printk(KERN_ERR "%s: get_iotiming undefined\n", __func__); | ||
536 | return -ENOENT; | ||
537 | } | ||
538 | |||
539 | printk(KERN_INFO "%s: working out IO settings\n", __func__); | ||
540 | |||
541 | ret = (cpu_cur.info->get_iotiming)(&cpu_cur, &s3c24xx_iotiming); | ||
542 | if (ret) | ||
543 | printk(KERN_ERR "%s: failed to get timings\n", __func__); | ||
544 | |||
545 | return ret; | ||
546 | } | ||
547 | |||
548 | /* if one or is zero, then return the other, otherwise return the min */ | ||
549 | #define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b)) | ||
550 | |||
551 | /** | ||
552 | * s3c_cpufreq_freq_min - find the minimum settings for the given freq. | ||
553 | * @dst: The destination structure | ||
554 | * @a: One argument. | ||
555 | * @b: The other argument. | ||
556 | * | ||
557 | * Create a minimum of each frequency entry in the 'struct s3c_freq', | ||
558 | * unless the entry is zero when it is ignored and the non-zero argument | ||
559 | * used. | ||
560 | */ | ||
561 | static void s3c_cpufreq_freq_min(struct s3c_freq *dst, | ||
562 | struct s3c_freq *a, struct s3c_freq *b) | ||
563 | { | ||
564 | dst->fclk = do_min(a->fclk, b->fclk); | ||
565 | dst->hclk = do_min(a->hclk, b->hclk); | ||
566 | dst->pclk = do_min(a->pclk, b->pclk); | ||
567 | dst->armclk = do_min(a->armclk, b->armclk); | ||
568 | } | ||
569 | |||
570 | static inline u32 calc_locktime(u32 freq, u32 time_us) | ||
571 | { | ||
572 | u32 result; | ||
573 | |||
574 | result = freq * time_us; | ||
575 | result = DIV_ROUND_UP(result, 1000 * 1000); | ||
576 | |||
577 | return result; | ||
578 | } | ||
579 | |||
580 | static void s3c_cpufreq_update_loctkime(void) | ||
581 | { | ||
582 | unsigned int bits = cpu_cur.info->locktime_bits; | ||
583 | u32 rate = (u32)clk_get_rate(_clk_xtal); | ||
584 | u32 val; | ||
585 | |||
586 | if (bits == 0) { | ||
587 | WARN_ON(1); | ||
588 | return; | ||
589 | } | ||
590 | |||
591 | val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits; | ||
592 | val |= calc_locktime(rate, cpu_cur.info->locktime_m); | ||
593 | |||
594 | printk(KERN_INFO "%s: new locktime is 0x%08x\n", __func__, val); | ||
595 | __raw_writel(val, S3C2410_LOCKTIME); | ||
596 | } | ||
597 | |||
598 | static int s3c_cpufreq_build_freq(void) | ||
599 | { | ||
600 | int size, ret; | ||
601 | |||
602 | if (!cpu_cur.info->calc_freqtable) | ||
603 | return -EINVAL; | ||
604 | |||
605 | kfree(ftab); | ||
606 | ftab = NULL; | ||
607 | |||
608 | size = cpu_cur.info->calc_freqtable(&cpu_cur, NULL, 0); | ||
609 | size++; | ||
610 | |||
611 | ftab = kmalloc(sizeof(struct cpufreq_frequency_table) * size, GFP_KERNEL); | ||
612 | if (!ftab) { | ||
613 | printk(KERN_ERR "%s: no memory for tables\n", __func__); | ||
614 | return -ENOMEM; | ||
615 | } | ||
616 | |||
617 | ftab_size = size; | ||
618 | |||
619 | ret = cpu_cur.info->calc_freqtable(&cpu_cur, ftab, size); | ||
620 | s3c_cpufreq_addfreq(ftab, ret, size, CPUFREQ_TABLE_END); | ||
621 | |||
622 | return 0; | ||
623 | } | ||
624 | |||
625 | static int __init s3c_cpufreq_initcall(void) | ||
626 | { | ||
627 | int ret = 0; | ||
628 | |||
629 | if (cpu_cur.info && cpu_cur.board) { | ||
630 | ret = s3c_cpufreq_initclks(); | ||
631 | if (ret) | ||
632 | goto out; | ||
633 | |||
634 | /* get current settings */ | ||
635 | s3c_cpufreq_getcur(&cpu_cur); | ||
636 | s3c_cpufreq_show("cur", &cpu_cur); | ||
637 | |||
638 | if (cpu_cur.board->auto_io) { | ||
639 | ret = s3c_cpufreq_auto_io(); | ||
640 | if (ret) { | ||
641 | printk(KERN_ERR "%s: failed to get io timing\n", | ||
642 | __func__); | ||
643 | goto out; | ||
644 | } | ||
645 | } | ||
646 | |||
647 | if (cpu_cur.board->need_io && !cpu_cur.info->set_iotiming) { | ||
648 | printk(KERN_ERR "%s: no IO support registered\n", | ||
649 | __func__); | ||
650 | ret = -EINVAL; | ||
651 | goto out; | ||
652 | } | ||
653 | |||
654 | if (!cpu_cur.info->need_pll) | ||
655 | cpu_cur.lock_pll = 1; | ||
656 | |||
657 | s3c_cpufreq_update_loctkime(); | ||
658 | |||
659 | s3c_cpufreq_freq_min(&cpu_cur.max, &cpu_cur.board->max, | ||
660 | &cpu_cur.info->max); | ||
661 | |||
662 | if (cpu_cur.info->calc_freqtable) | ||
663 | s3c_cpufreq_build_freq(); | ||
664 | |||
665 | ret = cpufreq_register_driver(&s3c24xx_driver); | ||
666 | } | ||
667 | |||
668 | out: | ||
669 | return ret; | ||
670 | } | ||
671 | |||
672 | late_initcall(s3c_cpufreq_initcall); | ||
673 | |||
674 | /** | ||
675 | * s3c_plltab_register - register CPU PLL table. | ||
676 | * @plls: The list of PLL entries. | ||
677 | * @plls_no: The size of the PLL entries @plls. | ||
678 | * | ||
679 | * Register the given set of PLLs with the system. | ||
680 | */ | ||
681 | int __init s3c_plltab_register(struct cpufreq_frequency_table *plls, | ||
682 | unsigned int plls_no) | ||
683 | { | ||
684 | struct cpufreq_frequency_table *vals; | ||
685 | unsigned int size; | ||
686 | |||
687 | size = sizeof(struct cpufreq_frequency_table) * (plls_no + 1); | ||
688 | |||
689 | vals = kmalloc(size, GFP_KERNEL); | ||
690 | if (vals) { | ||
691 | memcpy(vals, plls, size); | ||
692 | pll_reg = vals; | ||
693 | |||
694 | /* write a terminating entry, we don't store it in the | ||
695 | * table that is stored in the kernel */ | ||
696 | vals += plls_no; | ||
697 | vals->frequency = CPUFREQ_TABLE_END; | ||
698 | |||
699 | printk(KERN_INFO "cpufreq: %d PLL entries\n", plls_no); | ||
700 | } else | ||
701 | printk(KERN_ERR "cpufreq: no memory for PLL tables\n"); | ||
702 | |||
703 | return vals ? 0 : -ENOMEM; | ||
704 | } | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h new file mode 100644 index 000000000000..e078821b3605 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h | |||
@@ -0,0 +1,183 @@ | |||
1 | /* arch/arm/plat-s3c/include/plat/cpu-freq.h | ||
2 | * | ||
3 | * Copyright (c) 2006,2007,2009 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C CPU frequency scaling support - core support | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <plat/cpu-freq.h> | ||
15 | |||
16 | #define MAX_BANKS (8) | ||
17 | #define S3C2412_MAX_IO (8) | ||
18 | |||
19 | /** | ||
20 | * struct s3c2410_iobank_timing - IO bank timings for S3C2410 style timings | ||
21 | * @bankcon: The cached version of settings in this structure. | ||
22 | * @tacp: | ||
23 | * @tacs: Time from address valid to nCS asserted. | ||
24 | * @tcos: Time from nCS asserted to nOE or nWE asserted. | ||
25 | * @tacc: Time that nOE or nWE is asserted. | ||
26 | * @tcoh: Time nCS is held after nOE or nWE are released. | ||
27 | * @tcah: Time address is held for after | ||
28 | * @nwait_en: Whether nWAIT is enabled for this bank. | ||
29 | * | ||
30 | * This structure represents the IO timings for a S3C2410 style IO bank | ||
31 | * used by the CPU frequency support if it needs to change the settings | ||
32 | * of the IO. | ||
33 | */ | ||
34 | struct s3c2410_iobank_timing { | ||
35 | unsigned long bankcon; | ||
36 | unsigned int tacp; | ||
37 | unsigned int tacs; | ||
38 | unsigned int tcos; | ||
39 | unsigned int tacc; | ||
40 | unsigned int tcoh; /* nCS hold afrer nOE/nWE */ | ||
41 | unsigned int tcah; /* Address hold after nCS */ | ||
42 | unsigned char nwait_en; /* nWait enabled for bank. */ | ||
43 | }; | ||
44 | |||
45 | union s3c_iobank { | ||
46 | struct s3c2410_iobank_timing *io_2410; | ||
47 | }; | ||
48 | |||
49 | /** | ||
50 | * struct s3c_iotimings - Chip IO timings holder | ||
51 | * @bank: The timings for each IO bank. | ||
52 | */ | ||
53 | struct s3c_iotimings { | ||
54 | union s3c_iobank bank[MAX_BANKS]; | ||
55 | }; | ||
56 | |||
57 | /** | ||
58 | * struct s3c_plltab - PLL table information. | ||
59 | * @vals: List of PLL values. | ||
60 | * @size: Size of the PLL table @vals. | ||
61 | */ | ||
62 | struct s3c_plltab { | ||
63 | struct s3c_pllval *vals; | ||
64 | int size; | ||
65 | }; | ||
66 | |||
67 | /** | ||
68 | * struct s3c_cpufreq_info - Information for the CPU frequency driver. | ||
69 | * @name: The name of this implementation. | ||
70 | * @max: The maximum frequencies for the system. | ||
71 | * @latency: Transition latency to give to cpufreq. | ||
72 | * @locktime_m: The lock-time in uS for the MPLL. | ||
73 | * @locktime_u: The lock-time in uS for the UPLL. | ||
74 | * @locttime_bits: The number of bits each LOCKTIME field. | ||
75 | * @need_pll: Set if this driver needs to change the PLL values to acheive | ||
76 | * any frequency changes. This is really only need by devices like the | ||
77 | * S3C2410 where there is no or limited divider between the PLL and the | ||
78 | * ARMCLK. | ||
79 | * @resume_clocks: Update the clocks on resume. | ||
80 | * @get_iotiming: Get the current IO timing data, mainly for use at start. | ||
81 | * @set_iotiming: Update the IO timings from the cached copies calculated | ||
82 | * from the @calc_iotiming entry when changing the frequency. | ||
83 | * @calc_iotiming: Calculate and update the cached copies of the IO timings | ||
84 | * from the newly calculated frequencies. | ||
85 | * @calc_freqtable: Calculate (fill in) the given frequency table from the | ||
86 | * current frequency configuration. If the table passed in is NULL, | ||
87 | * then the return is the number of elements to be filled for allocation | ||
88 | * of the table. | ||
89 | * @set_refresh: Set the memory refresh configuration. | ||
90 | * @set_fvco: Set the PLL frequencies. | ||
91 | * @set_divs: Update the clock divisors. | ||
92 | * @calc_divs: Calculate the clock divisors. | ||
93 | */ | ||
94 | struct s3c_cpufreq_info { | ||
95 | const char *name; | ||
96 | struct s3c_freq max; | ||
97 | |||
98 | unsigned int latency; | ||
99 | |||
100 | unsigned int locktime_m; | ||
101 | unsigned int locktime_u; | ||
102 | unsigned char locktime_bits; | ||
103 | |||
104 | unsigned int need_pll:1; | ||
105 | |||
106 | /* driver routines */ | ||
107 | |||
108 | void (*resume_clocks)(void); | ||
109 | |||
110 | int (*get_iotiming)(struct s3c_cpufreq_config *cfg, | ||
111 | struct s3c_iotimings *timings); | ||
112 | |||
113 | void (*set_iotiming)(struct s3c_cpufreq_config *cfg, | ||
114 | struct s3c_iotimings *timings); | ||
115 | |||
116 | int (*calc_iotiming)(struct s3c_cpufreq_config *cfg, | ||
117 | struct s3c_iotimings *timings); | ||
118 | |||
119 | int (*calc_freqtable)(struct s3c_cpufreq_config *cfg, | ||
120 | struct cpufreq_frequency_table *t, | ||
121 | size_t table_size); | ||
122 | |||
123 | void (*set_refresh)(struct s3c_cpufreq_config *cfg); | ||
124 | void (*set_fvco)(struct s3c_cpufreq_config *cfg); | ||
125 | void (*set_divs)(struct s3c_cpufreq_config *cfg); | ||
126 | int (*calc_divs)(struct s3c_cpufreq_config *cfg); | ||
127 | }; | ||
128 | |||
129 | extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info); | ||
130 | |||
131 | extern int s3c_plltab_register(struct cpufreq_frequency_table *plls, unsigned int plls_no); | ||
132 | |||
133 | /* Useful utility functions. */ | ||
134 | |||
135 | extern struct clk *s3c_cpufreq_clk_get(struct device *, const char *); | ||
136 | |||
137 | /* S3C2410 and compatible exported functions */ | ||
138 | |||
139 | extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg); | ||
140 | |||
141 | extern int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg, | ||
142 | struct s3c_iotimings *iot); | ||
143 | |||
144 | extern int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg, | ||
145 | struct s3c_iotimings *timings); | ||
146 | |||
147 | extern void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg, | ||
148 | struct s3c_iotimings *iot); | ||
149 | |||
150 | extern void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg); | ||
151 | |||
152 | #ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUG | ||
153 | #define s3c_freq_dbg(x...) printk(KERN_INFO x) | ||
154 | #else | ||
155 | #define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0) | ||
156 | #endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUG */ | ||
157 | |||
158 | #ifdef CONFIG_CPU_FREQ_S3C24XX_IODEBUG | ||
159 | #define s3c_freq_iodbg(x...) printk(KERN_INFO x) | ||
160 | #else | ||
161 | #define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0) | ||
162 | #endif /* CONFIG_CPU_FREQ_S3C24XX_IODEBUG */ | ||
163 | |||
164 | static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table, | ||
165 | int index, size_t table_size, | ||
166 | unsigned int freq) | ||
167 | { | ||
168 | if (index < 0) | ||
169 | return index; | ||
170 | |||
171 | if (table) { | ||
172 | if (index >= table_size) | ||
173 | return -ENOMEM; | ||
174 | |||
175 | s3c_freq_dbg("%s: { %d = %u kHz }\n", | ||
176 | __func__, index, freq); | ||
177 | |||
178 | table[index].index = index; | ||
179 | table[index].frequency = freq; | ||
180 | } | ||
181 | |||
182 | return index + 1; | ||
183 | } | ||