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authorRajeshwari Shinde <rajeshwari.s@samsung.com>2011-10-24 11:05:58 -0400
committerKukjin Kim <kgene.kim@samsung.com>2011-12-22 20:09:16 -0500
commita361d10a2b490812b051433b1aad5b4351372597 (patch)
tree7132392c01d78d275d12313056803e15e97c5f6b /arch/arm/plat-s3c24xx
parenta60879e7ca17ea41bacd57e3cb2b56e48135f7a3 (diff)
ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names
Add support for lookup of sdhci-s3c controller clocks using generic names for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> [kgene.kim@samsung.com: fixed trailing whitespace] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/plat-s3c24xx')
-rw-r--r--arch/arm/plat-s3c24xx/s3c2443-clock.c16
1 files changed, 10 insertions, 6 deletions
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
index 4eab2cca2d92..95e68190d593 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -427,12 +427,6 @@ static struct clk init_clocks[] = {
427 .enable = s3c2443_clkcon_enable_h, 427 .enable = s3c2443_clkcon_enable_h,
428 .ctrlbit = S3C2443_HCLKCON_DMA5, 428 .ctrlbit = S3C2443_HCLKCON_DMA5,
429 }, { 429 }, {
430 .name = "hsmmc",
431 .devname = "s3c-sdhci.1",
432 .parent = &clk_h,
433 .enable = s3c2443_clkcon_enable_h,
434 .ctrlbit = S3C2443_HCLKCON_HSMMC,
435 }, {
436 .name = "gpio", 430 .name = "gpio",
437 .parent = &clk_p, 431 .parent = &clk_p,
438 .enable = s3c2443_clkcon_enable_p, 432 .enable = s3c2443_clkcon_enable_p,
@@ -514,6 +508,14 @@ static struct clk init_clocks[] = {
514 } 508 }
515}; 509};
516 510
511static struct clk hsmmc1_clk = {
512 .name = "hsmmc",
513 .devname = "s3c-sdhci.1",
514 .parent = &clk_h,
515 .enable = s3c2443_clkcon_enable_h,
516 .ctrlbit = S3C2443_HCLKCON_HSMMC,
517};
518
517static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0) 519static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
518{ 520{
519 clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK; 521 clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
@@ -579,6 +581,7 @@ static struct clk *clks[] __initdata = {
579 &clk_epll, 581 &clk_epll,
580 &clk_usb_bus, 582 &clk_usb_bus,
581 &clk_armdiv, 583 &clk_armdiv,
584 &hsmmc1_clk,
582}; 585};
583 586
584static struct clksrc_clk *clksrcs[] __initdata = { 587static struct clksrc_clk *clksrcs[] __initdata = {
@@ -595,6 +598,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = {
595 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), 598 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
596 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), 599 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
597 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk), 600 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
601 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
598}; 602};
599 603
600void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, 604void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,