diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-02-06 12:39:31 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-02-22 12:11:25 -0500 |
commit | 2e2f3d3792de5913897b6bb49ac13915b0b020d5 (patch) | |
tree | 02126d58ee15cf94c7335604ef8f9e8eb21d7378 /arch/arm/plat-s3c24xx | |
parent | 96c20015dae59e58d055c1e2e17a811e0d1f1d03 (diff) |
ARM: pm: convert samsung platforms to generic suspend/resume support
Tested-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/plat-s3c24xx')
-rw-r--r-- | arch/arm/plat-s3c24xx/sleep.S | 57 |
1 files changed, 4 insertions, 53 deletions
diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S index e73e3b6e88d2..fd7032f84ae7 100644 --- a/arch/arm/plat-s3c24xx/sleep.S +++ b/arch/arm/plat-s3c24xx/sleep.S | |||
@@ -44,23 +44,13 @@ | |||
44 | /* s3c_cpu_save | 44 | /* s3c_cpu_save |
45 | * | 45 | * |
46 | * entry: | 46 | * entry: |
47 | * r0 = save address (virtual addr of s3c_sleep_save_phys) | 47 | * r1 = v:p offset |
48 | */ | 48 | */ |
49 | 49 | ||
50 | ENTRY(s3c_cpu_save) | 50 | ENTRY(s3c_cpu_save) |
51 | stmfd sp!, { r4 - r12, lr } | 51 | stmfd sp!, { r4 - r12, lr } |
52 | 52 | ldr r3, =resume_with_mmu | |
53 | @@ store co-processor registers | 53 | bl cpu_suspend |
54 | |||
55 | mrc p15, 0, r4, c13, c0, 0 @ PID | ||
56 | mrc p15, 0, r5, c3, c0, 0 @ Domain ID | ||
57 | mrc p15, 0, r6, c2, c0, 0 @ translation table base address | ||
58 | mrc p15, 0, r7, c1, c0, 0 @ control register | ||
59 | |||
60 | stmia r0, { r4 - r13 } | ||
61 | |||
62 | @@ write our state back to RAM | ||
63 | bl s3c_pm_cb_flushcache | ||
64 | 54 | ||
65 | @@ jump to final code to send system to sleep | 55 | @@ jump to final code to send system to sleep |
66 | ldr r0, =pm_cpu_sleep | 56 | ldr r0, =pm_cpu_sleep |
@@ -76,20 +66,6 @@ resume_with_mmu: | |||
76 | 66 | ||
77 | .ltorg | 67 | .ltorg |
78 | 68 | ||
79 | @@ the next bits sit in the .data segment, even though they | ||
80 | @@ happen to be code... the s3c_sleep_save_phys needs to be | ||
81 | @@ accessed by the resume code before it can restore the MMU. | ||
82 | @@ This means that the variable has to be close enough for the | ||
83 | @@ code to read it... since the .text segment needs to be RO, | ||
84 | @@ the data segment can be the only place to put this code. | ||
85 | |||
86 | .data | ||
87 | |||
88 | .global s3c_sleep_save_phys | ||
89 | s3c_sleep_save_phys: | ||
90 | .word 0 | ||
91 | |||
92 | |||
93 | /* sleep magic, to allow the bootloader to check for an valid | 69 | /* sleep magic, to allow the bootloader to check for an valid |
94 | * image to resume to. Must be the first word before the | 70 | * image to resume to. Must be the first word before the |
95 | * s3c_cpu_resume entry. | 71 | * s3c_cpu_resume entry. |
@@ -100,10 +76,6 @@ s3c_sleep_save_phys: | |||
100 | /* s3c_cpu_resume | 76 | /* s3c_cpu_resume |
101 | * | 77 | * |
102 | * resume code entry for bootloader to call | 78 | * resume code entry for bootloader to call |
103 | * | ||
104 | * we must put this code here in the data segment as we have no | ||
105 | * other way of restoring the stack pointer after sleep, and we | ||
106 | * must not write to the code segment (code is read-only) | ||
107 | */ | 79 | */ |
108 | 80 | ||
109 | ENTRY(s3c_cpu_resume) | 81 | ENTRY(s3c_cpu_resume) |
@@ -134,25 +106,4 @@ ENTRY(s3c_cpu_resume) | |||
134 | beq 1001b | 106 | beq 1001b |
135 | #endif /* CONFIG_DEBUG_RESUME */ | 107 | #endif /* CONFIG_DEBUG_RESUME */ |
136 | 108 | ||
137 | mov r1, #0 | 109 | b cpu_resume |
138 | mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs | ||
139 | mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches | ||
140 | |||
141 | ldr r0, s3c_sleep_save_phys @ address of restore block | ||
142 | ldmia r0, { r4 - r13 } | ||
143 | |||
144 | mcr p15, 0, r4, c13, c0, 0 @ PID | ||
145 | mcr p15, 0, r5, c3, c0, 0 @ Domain ID | ||
146 | mcr p15, 0, r6, c2, c0, 0 @ translation table base | ||
147 | |||
148 | #ifdef CONFIG_DEBUG_RESUME | ||
149 | mov r3, #'R' | ||
150 | strb r3, [ r2, #S3C2410_UTXH ] | ||
151 | #endif | ||
152 | |||
153 | ldr r2, =resume_with_mmu | ||
154 | mcr p15, 0, r7, c1, c0, 0 @ turn on MMU, etc | ||
155 | nop @ second-to-last before mmu | ||
156 | mov pc, r2 @ go back to virtual address | ||
157 | |||
158 | .ltorg | ||