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authorBen Dooks <ben-linux@fluff.org>2008-11-21 05:36:05 -0500
committerBen Dooks <ben-linux@fluff.org>2008-12-16 05:13:02 -0500
commit9d325f23416d1525401d43442bafca2bb254ab74 (patch)
tree4b8e0ef7c121c263d2cbbea136c97d81d6be0463 /arch/arm/plat-s3c24xx
parentb09bcdd4c2f52b54115895c4d62ad82918f71431 (diff)
[ARM] S3C: Update time initialisation to fix S3C64XX time problems
The S3C64XX timer is running at the wrong rate due to the assumptions made in the timer initialisation about the way the pwm dividers work. This means that time on the S3C64XX runs twice as fast as it should. Fix the problem by moving to using the clk framework to setup the pwm timer clock muxes, as the pwm-clock code has all the necessary knowledge of how the timer clock inputs are routed. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c24xx')
-rw-r--r--arch/arm/plat-s3c24xx/s3c2410-clock.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c24xx/s3c2410-clock.c b/arch/arm/plat-s3c24xx/s3c2410-clock.c
index 4e07943c1e29..b61bdb793734 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2410-clock.c
@@ -272,5 +272,6 @@ int __init s3c2410_baseclk_add(void)
272 (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on", 272 (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
273 (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on"); 273 (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
274 274
275 s3c_pwmclk_init();
275 return 0; 276 return 0;
276} 277}