Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (91 commits)
  ARM: 6806/1: irq: introduce entry and exit functions for chained handlers
  ARM: 6781/1: Thumb-2: Work around buggy Thumb-2 short branch relocations in gas
  ARM: 6747/1: P2V: Thumb2 support
  ARM: 6798/1: aout-core: zero thread debug registers in a.out core dump
  ARM: 6796/1: Footbridge: Fix I/O mappings for NOMMU mode
  ARM: 6784/1: errata: no automatic Store Buffer drain on Cortex-A9
  ARM: 6772/1: errata: possible fault MMU translations following an ASID switch
  ARM: 6776/1: mach-ux500: activate fix for errata 753970
  ARM: 6794/1: SPEAr: Append UL to device address macros.
  ARM: 6793/1: SPEAr: Remove unused *_SIZE macros from spear*.h files
  ARM: 6792/1: SPEAr: Replace SIZE macro's with SZ_4K macros
  ARM: 6791/1: SPEAr3xx: Declare device structures after shirq code
  ARM: 6790/1: SPEAr: Clock Framework: Rename usbd clock and align apb_clk entry
  ARM: 6789/1: SPEAr3xx: Rename sdio to sdhci
  ARM: 6788/1: SPEAr: Include mach/hardware.h instead of mach/spear.h
  ARM: 6787/1: SPEAr: Reorder #includes in .h & .c files.
  ARM: 6681/1: SPEAr: add debugfs support to clk API
  ARM: 6703/1: SPEAr: update clk API support
  ARM: 6679/1: SPEAr: make clk API functions more generic
  ARM: 6737/1: SPEAr: formalized timer support
  ...

1 files changed, 4 insertions, 53 deletions

diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S
index e73e3b6e88d2..fd7032f84ae7 100644
--- a/arch/arm/plat-s3c24xx/sleep.S
+++ b/arch/arm/plat-s3c24xx/sleep.S
@@ -44,23 +44,13 @@
         /* s3c_cpu_save
          *
          * entry:
-         *      r0 = save address (virtual addr of s3c_sleep_save_phys)
+         *      r1 = v:p offset
         */
 
 ENTRY(s3c_cpu_save)
         stmfd   sp!, { r4 - r12, lr }
-
-        @@ store co-processor registers
-
-        mrc     p15, 0, r4, c13, c0, 0  @ PID
-        mrc     p15, 0, r5, c3, c0, 0   @ Domain ID
-        mrc     p15, 0, r6, c2, c0, 0   @ translation table base address
-        mrc     p15, 0, r7, c1, c0, 0   @ control register
-
-        stmia   r0, { r4 - r13 }
-
-        @@ write our state back to RAM
-        bl      s3c_pm_cb_flushcache
+        ldr     r3, =resume_with_mmu
+        bl      cpu_suspend
 
         @@ jump to final code to send system to sleep
         ldr     r0, =pm_cpu_sleep
@@ -76,20 +66,6 @@ resume_with_mmu:
 
         .ltorg
 
-        @@ the next bits sit in the .data segment, even though they
-        @@ happen to be code... the s3c_sleep_save_phys needs to be
-        @@ accessed by the resume code before it can restore the MMU.
-        @@ This means that the variable has to be close enough for the
-        @@ code to read it... since the .text segment needs to be RO,
-        @@ the data segment can be the only place to put this code.
-
-        .data
-
-        .global s3c_sleep_save_phys
-s3c_sleep_save_phys:
-        .word   0
-
-
         /* sleep magic, to allow the bootloader to check for an valid
          * image to resume to. Must be the first word before the
          * s3c_cpu_resume entry.
@@ -100,10 +76,6 @@ s3c_sleep_save_phys:
         /* s3c_cpu_resume
          *
          * resume code entry for bootloader to call
-         *
-         * we must put this code here in the data segment as we have no
-         * other way of restoring the stack pointer after sleep, and we
-         * must not write to the code segment (code is read-only)
         */
 
 ENTRY(s3c_cpu_resume)
@@ -134,25 +106,4 @@ ENTRY(s3c_cpu_resume)
         beq     1001b
 #endif /* CONFIG_DEBUG_RESUME */
 
-        mov     r1, #0
-        mcr     p15, 0, r1, c8, c7, 0           @@ invalidate I & D TLBs
-        mcr     p15, 0, r1, c7, c7, 0           @@ invalidate I & D caches
-
-        ldr     r0, s3c_sleep_save_phys         @ address of restore block
-        ldmia   r0, { r4 - r13 }
-
-        mcr     p15, 0, r4, c13, c0, 0          @ PID
-        mcr     p15, 0, r5, c3, c0, 0           @ Domain ID
-        mcr     p15, 0, r6, c2, c0, 0           @ translation table base
-
-#ifdef CONFIG_DEBUG_RESUME
-        mov     r3, #'R'
-        strb    r3, [ r2, #S3C2410_UTXH ]
-#endif
-
-        ldr     r2, =resume_with_mmu
-        mcr     p15, 0, r7, c1, c0, 0           @ turn on MMU, etc
-        nop                                     @ second-to-last before mmu
-        mov     pc, r2                          @ go back to virtual address
-
-        .ltorg
+        b       cpu_resume