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authorBen Dooks <ben-linux@fluff.org>2008-10-21 09:06:54 -0400
committerBen Dooks <ben-linux@fluff.org>2008-12-15 16:46:18 -0500
commitadbefaa5fdc6673bf389c00c3448b12d6125990b (patch)
treeabe2ab3a6c25e2f423437b3f2d30670dcf46382a /arch/arm/plat-s3c24xx
parentb915a125112b2500d5c6fd752948afc170a49cef (diff)
[ARM] S3C: Move core clock support to plat-s3c
Move the core clock registration and definitions in arch/arm/plat-s3c24xx/clock.c to arch/arm/plat-s3c to be shared with the S3C64XX implementations. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c24xx')
-rw-r--r--arch/arm/plat-s3c24xx/clock.c314
1 files changed, 0 insertions, 314 deletions
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c
index a4a0a67a3074..8474d05274bd 100644
--- a/arch/arm/plat-s3c24xx/clock.c
+++ b/arch/arm/plat-s3c24xx/clock.c
@@ -27,18 +27,8 @@
27*/ 27*/
28 28
29#include <linux/init.h> 29#include <linux/init.h>
30#include <linux/module.h>
31#include <linux/kernel.h> 30#include <linux/kernel.h>
32#include <linux/list.h>
33#include <linux/errno.h>
34#include <linux/err.h>
35#include <linux/platform_device.h>
36#include <linux/sysdev.h>
37#include <linux/interrupt.h>
38#include <linux/ioport.h>
39#include <linux/clk.h> 31#include <linux/clk.h>
40#include <linux/spinlock.h>
41#include <linux/delay.h>
42#include <linux/io.h> 32#include <linux/io.h>
43 33
44#include <mach/hardware.h> 34#include <mach/hardware.h>
@@ -53,280 +43,6 @@
53#include <plat/cpu.h> 43#include <plat/cpu.h>
54#include <plat/pll.h> 44#include <plat/pll.h>
55 45
56/* clock information */
57
58static LIST_HEAD(clocks);
59
60/* We originally used an mutex here, but some contexts (see resume)
61 * are calling functions such as clk_set_parent() with IRQs disabled
62 * causing an BUG to be triggered.
63 */
64DEFINE_SPINLOCK(clocks_lock);
65
66/* enable and disable calls for use with the clk struct */
67
68static int clk_null_enable(struct clk *clk, int enable)
69{
70 return 0;
71}
72
73/* Clock API calls */
74
75struct clk *clk_get(struct device *dev, const char *id)
76{
77 struct clk *p;
78 struct clk *clk = ERR_PTR(-ENOENT);
79 int idno;
80
81 if (dev == NULL || dev->bus != &platform_bus_type)
82 idno = -1;
83 else
84 idno = to_platform_device(dev)->id;
85
86 spin_lock(&clocks_lock);
87
88 list_for_each_entry(p, &clocks, list) {
89 if (p->id == idno &&
90 strcmp(id, p->name) == 0 &&
91 try_module_get(p->owner)) {
92 clk = p;
93 break;
94 }
95 }
96
97 /* check for the case where a device was supplied, but the
98 * clock that was being searched for is not device specific */
99
100 if (IS_ERR(clk)) {
101 list_for_each_entry(p, &clocks, list) {
102 if (p->id == -1 && strcmp(id, p->name) == 0 &&
103 try_module_get(p->owner)) {
104 clk = p;
105 break;
106 }
107 }
108 }
109
110 spin_unlock(&clocks_lock);
111 return clk;
112}
113
114void clk_put(struct clk *clk)
115{
116 module_put(clk->owner);
117}
118
119int clk_enable(struct clk *clk)
120{
121 if (IS_ERR(clk) || clk == NULL)
122 return -EINVAL;
123
124 clk_enable(clk->parent);
125
126 spin_lock(&clocks_lock);
127
128 if ((clk->usage++) == 0)
129 (clk->enable)(clk, 1);
130
131 spin_unlock(&clocks_lock);
132 return 0;
133}
134
135void clk_disable(struct clk *clk)
136{
137 if (IS_ERR(clk) || clk == NULL)
138 return;
139
140 spin_lock(&clocks_lock);
141
142 if ((--clk->usage) == 0)
143 (clk->enable)(clk, 0);
144
145 spin_unlock(&clocks_lock);
146 clk_disable(clk->parent);
147}
148
149
150unsigned long clk_get_rate(struct clk *clk)
151{
152 if (IS_ERR(clk))
153 return 0;
154
155 if (clk->rate != 0)
156 return clk->rate;
157
158 if (clk->get_rate != NULL)
159 return (clk->get_rate)(clk);
160
161 if (clk->parent != NULL)
162 return clk_get_rate(clk->parent);
163
164 return clk->rate;
165}
166
167long clk_round_rate(struct clk *clk, unsigned long rate)
168{
169 if (!IS_ERR(clk) && clk->round_rate)
170 return (clk->round_rate)(clk, rate);
171
172 return rate;
173}
174
175int clk_set_rate(struct clk *clk, unsigned long rate)
176{
177 int ret;
178
179 if (IS_ERR(clk))
180 return -EINVAL;
181
182 /* We do not default just do a clk->rate = rate as
183 * the clock may have been made this way by choice.
184 */
185
186 WARN_ON(clk->set_rate == NULL);
187
188 if (clk->set_rate == NULL)
189 return -EINVAL;
190
191 spin_lock(&clocks_lock);
192 ret = (clk->set_rate)(clk, rate);
193 spin_unlock(&clocks_lock);
194
195 return ret;
196}
197
198struct clk *clk_get_parent(struct clk *clk)
199{
200 return clk->parent;
201}
202
203int clk_set_parent(struct clk *clk, struct clk *parent)
204{
205 int ret = 0;
206
207 if (IS_ERR(clk))
208 return -EINVAL;
209
210 spin_lock(&clocks_lock);
211
212 if (clk->set_parent)
213 ret = (clk->set_parent)(clk, parent);
214
215 spin_unlock(&clocks_lock);
216
217 return ret;
218}
219
220EXPORT_SYMBOL(clk_get);
221EXPORT_SYMBOL(clk_put);
222EXPORT_SYMBOL(clk_enable);
223EXPORT_SYMBOL(clk_disable);
224EXPORT_SYMBOL(clk_get_rate);
225EXPORT_SYMBOL(clk_round_rate);
226EXPORT_SYMBOL(clk_set_rate);
227EXPORT_SYMBOL(clk_get_parent);
228EXPORT_SYMBOL(clk_set_parent);
229
230/* base clocks */
231
232static int clk_default_setrate(struct clk *clk, unsigned long rate)
233{
234 clk->rate = rate;
235 return 0;
236}
237
238struct clk clk_xtal = {
239 .name = "xtal",
240 .id = -1,
241 .rate = 0,
242 .parent = NULL,
243 .ctrlbit = 0,
244};
245
246struct clk clk_mpll = {
247 .name = "mpll",
248 .id = -1,
249 .set_rate = clk_default_setrate,
250};
251
252struct clk clk_upll = {
253 .name = "upll",
254 .id = -1,
255 .parent = NULL,
256 .ctrlbit = 0,
257};
258
259struct clk clk_f = {
260 .name = "fclk",
261 .id = -1,
262 .rate = 0,
263 .parent = &clk_mpll,
264 .ctrlbit = 0,
265 .set_rate = clk_default_setrate,
266};
267
268struct clk clk_h = {
269 .name = "hclk",
270 .id = -1,
271 .rate = 0,
272 .parent = NULL,
273 .ctrlbit = 0,
274 .set_rate = clk_default_setrate,
275};
276
277struct clk clk_p = {
278 .name = "pclk",
279 .id = -1,
280 .rate = 0,
281 .parent = NULL,
282 .ctrlbit = 0,
283 .set_rate = clk_default_setrate,
284};
285
286struct clk clk_usb_bus = {
287 .name = "usb-bus",
288 .id = -1,
289 .rate = 0,
290 .parent = &clk_upll,
291};
292
293
294
295struct clk s3c24xx_uclk = {
296 .name = "uclk",
297 .id = -1,
298};
299
300/* initialise the clock system */
301
302int s3c24xx_register_clock(struct clk *clk)
303{
304 clk->owner = THIS_MODULE;
305
306 if (clk->enable == NULL)
307 clk->enable = clk_null_enable;
308
309 /* add to the list of available clocks */
310
311 spin_lock(&clocks_lock);
312 list_add(&clk->list, &clocks);
313 spin_unlock(&clocks_lock);
314
315 return 0;
316}
317
318int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
319{
320 int fails = 0;
321
322 for (; nr_clks > 0; nr_clks--, clks++) {
323 if (s3c24xx_register_clock(*clks) < 0)
324 fails++;
325 }
326
327 return fails;
328}
329
330/* initalise all the clocks */ 46/* initalise all the clocks */
331 47
332void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk, 48void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
@@ -341,33 +57,3 @@ void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
341 clk_p.rate = pclk; 57 clk_p.rate = pclk;
342 clk_f.rate = fclk; 58 clk_f.rate = fclk;
343} 59}
344
345int __init s3c24xx_register_baseclocks(unsigned long xtal)
346{
347 printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n");
348
349 clk_xtal.rate = xtal;
350
351 /* register our clocks */
352
353 if (s3c24xx_register_clock(&clk_xtal) < 0)
354 printk(KERN_ERR "failed to register master xtal\n");
355
356 if (s3c24xx_register_clock(&clk_mpll) < 0)
357 printk(KERN_ERR "failed to register mpll clock\n");
358
359 if (s3c24xx_register_clock(&clk_upll) < 0)
360 printk(KERN_ERR "failed to register upll clock\n");
361
362 if (s3c24xx_register_clock(&clk_f) < 0)
363 printk(KERN_ERR "failed to register cpu fclk\n");
364
365 if (s3c24xx_register_clock(&clk_h) < 0)
366 printk(KERN_ERR "failed to register cpu hclk\n");
367
368 if (s3c24xx_register_clock(&clk_p) < 0)
369 printk(KERN_ERR "failed to register cpu pclk\n");
370
371 return 0;
372}
373