diff options
author | Thomas Abraham <thomas.ab@samsung.com> | 2011-06-14 06:12:26 -0400 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-07-20 06:11:29 -0400 |
commit | e83626f2fd48fa53ece85760c7e0b4ec4a996a91 (patch) | |
tree | 8f89557b9e9f1e39314d9eabda7454b34a15b8a1 /arch/arm/plat-s3c24xx/s3c2443-clock.c | |
parent | f86c6660927614fcda257e083569bfb252fcf85e (diff) |
ARM: S3C24XX: Add clkdev support
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/plat-s3c24xx/s3c2443-clock.c')
-rw-r--r-- | arch/arm/plat-s3c24xx/s3c2443-clock.c | 39 |
1 files changed, 4 insertions, 35 deletions
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c index 82f2d4a39291..59552c0ea5fb 100644 --- a/arch/arm/plat-s3c24xx/s3c2443-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c | |||
@@ -56,7 +56,6 @@ int s3c2443_clkcon_enable_s(struct clk *clk, int enable) | |||
56 | struct clk clk_mpllref = { | 56 | struct clk clk_mpllref = { |
57 | .name = "mpllref", | 57 | .name = "mpllref", |
58 | .parent = &clk_xtal, | 58 | .parent = &clk_xtal, |
59 | .id = -1, | ||
60 | }; | 59 | }; |
61 | 60 | ||
62 | static struct clk *clk_epllref_sources[] = { | 61 | static struct clk *clk_epllref_sources[] = { |
@@ -69,7 +68,6 @@ static struct clk *clk_epllref_sources[] = { | |||
69 | struct clksrc_clk clk_epllref = { | 68 | struct clksrc_clk clk_epllref = { |
70 | .clk = { | 69 | .clk = { |
71 | .name = "epllref", | 70 | .name = "epllref", |
72 | .id = -1, | ||
73 | }, | 71 | }, |
74 | .sources = &(struct clksrc_sources) { | 72 | .sources = &(struct clksrc_sources) { |
75 | .sources = clk_epllref_sources, | 73 | .sources = clk_epllref_sources, |
@@ -92,7 +90,6 @@ struct clksrc_clk clk_esysclk = { | |||
92 | .clk = { | 90 | .clk = { |
93 | .name = "esysclk", | 91 | .name = "esysclk", |
94 | .parent = &clk_epll, | 92 | .parent = &clk_epll, |
95 | .id = -1, | ||
96 | }, | 93 | }, |
97 | .sources = &(struct clksrc_sources) { | 94 | .sources = &(struct clksrc_sources) { |
98 | .sources = clk_sysclk_sources, | 95 | .sources = clk_sysclk_sources, |
@@ -115,7 +112,6 @@ static unsigned long s3c2443_getrate_mdivclk(struct clk *clk) | |||
115 | static struct clk clk_mdivclk = { | 112 | static struct clk clk_mdivclk = { |
116 | .name = "mdivclk", | 113 | .name = "mdivclk", |
117 | .parent = &clk_mpllref, | 114 | .parent = &clk_mpllref, |
118 | .id = -1, | ||
119 | .ops = &(struct clk_ops) { | 115 | .ops = &(struct clk_ops) { |
120 | .get_rate = s3c2443_getrate_mdivclk, | 116 | .get_rate = s3c2443_getrate_mdivclk, |
121 | }, | 117 | }, |
@@ -132,7 +128,6 @@ struct clksrc_clk clk_msysclk = { | |||
132 | .clk = { | 128 | .clk = { |
133 | .name = "msysclk", | 129 | .name = "msysclk", |
134 | .parent = &clk_xtal, | 130 | .parent = &clk_xtal, |
135 | .id = -1, | ||
136 | }, | 131 | }, |
137 | .sources = &(struct clksrc_sources) { | 132 | .sources = &(struct clksrc_sources) { |
138 | .sources = clk_msysclk_sources, | 133 | .sources = clk_msysclk_sources, |
@@ -159,7 +154,6 @@ static unsigned long s3c2443_prediv_getrate(struct clk *clk) | |||
159 | 154 | ||
160 | static struct clk clk_prediv = { | 155 | static struct clk clk_prediv = { |
161 | .name = "prediv", | 156 | .name = "prediv", |
162 | .id = -1, | ||
163 | .parent = &clk_msysclk.clk, | 157 | .parent = &clk_msysclk.clk, |
164 | .ops = &(struct clk_ops) { | 158 | .ops = &(struct clk_ops) { |
165 | .get_rate = s3c2443_prediv_getrate, | 159 | .get_rate = s3c2443_prediv_getrate, |
@@ -174,7 +168,6 @@ static struct clk clk_prediv = { | |||
174 | static struct clksrc_clk clk_usb_bus_host = { | 168 | static struct clksrc_clk clk_usb_bus_host = { |
175 | .clk = { | 169 | .clk = { |
176 | .name = "usb-bus-host-parent", | 170 | .name = "usb-bus-host-parent", |
177 | .id = -1, | ||
178 | .parent = &clk_esysclk.clk, | 171 | .parent = &clk_esysclk.clk, |
179 | .ctrlbit = S3C2443_SCLKCON_USBHOST, | 172 | .ctrlbit = S3C2443_SCLKCON_USBHOST, |
180 | .enable = s3c2443_clkcon_enable_s, | 173 | .enable = s3c2443_clkcon_enable_s, |
@@ -189,7 +182,6 @@ static struct clksrc_clk clksrc_clks[] = { | |||
189 | /* ART baud-rate clock sourced from esysclk via a divisor */ | 182 | /* ART baud-rate clock sourced from esysclk via a divisor */ |
190 | .clk = { | 183 | .clk = { |
191 | .name = "uartclk", | 184 | .name = "uartclk", |
192 | .id = -1, | ||
193 | .parent = &clk_esysclk.clk, | 185 | .parent = &clk_esysclk.clk, |
194 | }, | 186 | }, |
195 | .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 }, | 187 | .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 }, |
@@ -197,7 +189,6 @@ static struct clksrc_clk clksrc_clks[] = { | |||
197 | /* camera interface bus-clock, divided down from esysclk */ | 189 | /* camera interface bus-clock, divided down from esysclk */ |
198 | .clk = { | 190 | .clk = { |
199 | .name = "camif-upll", /* same as 2440 name */ | 191 | .name = "camif-upll", /* same as 2440 name */ |
200 | .id = -1, | ||
201 | .parent = &clk_esysclk.clk, | 192 | .parent = &clk_esysclk.clk, |
202 | .ctrlbit = S3C2443_SCLKCON_CAMCLK, | 193 | .ctrlbit = S3C2443_SCLKCON_CAMCLK, |
203 | .enable = s3c2443_clkcon_enable_s, | 194 | .enable = s3c2443_clkcon_enable_s, |
@@ -206,7 +197,6 @@ static struct clksrc_clk clksrc_clks[] = { | |||
206 | }, { | 197 | }, { |
207 | .clk = { | 198 | .clk = { |
208 | .name = "display-if", | 199 | .name = "display-if", |
209 | .id = -1, | ||
210 | .parent = &clk_esysclk.clk, | 200 | .parent = &clk_esysclk.clk, |
211 | .ctrlbit = S3C2443_SCLKCON_DISPCLK, | 201 | .ctrlbit = S3C2443_SCLKCON_DISPCLK, |
212 | .enable = s3c2443_clkcon_enable_s, | 202 | .enable = s3c2443_clkcon_enable_s, |
@@ -219,13 +209,11 @@ static struct clksrc_clk clksrc_clks[] = { | |||
219 | static struct clk init_clocks_off[] = { | 209 | static struct clk init_clocks_off[] = { |
220 | { | 210 | { |
221 | .name = "adc", | 211 | .name = "adc", |
222 | .id = -1, | ||
223 | .parent = &clk_p, | 212 | .parent = &clk_p, |
224 | .enable = s3c2443_clkcon_enable_p, | 213 | .enable = s3c2443_clkcon_enable_p, |
225 | .ctrlbit = S3C2443_PCLKCON_ADC, | 214 | .ctrlbit = S3C2443_PCLKCON_ADC, |
226 | }, { | 215 | }, { |
227 | .name = "i2c", | 216 | .name = "i2c", |
228 | .id = -1, | ||
229 | .parent = &clk_p, | 217 | .parent = &clk_p, |
230 | .enable = s3c2443_clkcon_enable_p, | 218 | .enable = s3c2443_clkcon_enable_p, |
231 | .ctrlbit = S3C2443_PCLKCON_IIC, | 219 | .ctrlbit = S3C2443_PCLKCON_IIC, |
@@ -235,136 +223,117 @@ static struct clk init_clocks_off[] = { | |||
235 | static struct clk init_clocks[] = { | 223 | static struct clk init_clocks[] = { |
236 | { | 224 | { |
237 | .name = "dma", | 225 | .name = "dma", |
238 | .id = 0, | ||
239 | .parent = &clk_h, | 226 | .parent = &clk_h, |
240 | .enable = s3c2443_clkcon_enable_h, | 227 | .enable = s3c2443_clkcon_enable_h, |
241 | .ctrlbit = S3C2443_HCLKCON_DMA0, | 228 | .ctrlbit = S3C2443_HCLKCON_DMA0, |
242 | }, { | 229 | }, { |
243 | .name = "dma", | 230 | .name = "dma", |
244 | .id = 1, | ||
245 | .parent = &clk_h, | 231 | .parent = &clk_h, |
246 | .enable = s3c2443_clkcon_enable_h, | 232 | .enable = s3c2443_clkcon_enable_h, |
247 | .ctrlbit = S3C2443_HCLKCON_DMA1, | 233 | .ctrlbit = S3C2443_HCLKCON_DMA1, |
248 | }, { | 234 | }, { |
249 | .name = "dma", | 235 | .name = "dma", |
250 | .id = 2, | ||
251 | .parent = &clk_h, | 236 | .parent = &clk_h, |
252 | .enable = s3c2443_clkcon_enable_h, | 237 | .enable = s3c2443_clkcon_enable_h, |
253 | .ctrlbit = S3C2443_HCLKCON_DMA2, | 238 | .ctrlbit = S3C2443_HCLKCON_DMA2, |
254 | }, { | 239 | }, { |
255 | .name = "dma", | 240 | .name = "dma", |
256 | .id = 3, | ||
257 | .parent = &clk_h, | 241 | .parent = &clk_h, |
258 | .enable = s3c2443_clkcon_enable_h, | 242 | .enable = s3c2443_clkcon_enable_h, |
259 | .ctrlbit = S3C2443_HCLKCON_DMA3, | 243 | .ctrlbit = S3C2443_HCLKCON_DMA3, |
260 | }, { | 244 | }, { |
261 | .name = "dma", | 245 | .name = "dma", |
262 | .id = 4, | ||
263 | .parent = &clk_h, | 246 | .parent = &clk_h, |
264 | .enable = s3c2443_clkcon_enable_h, | 247 | .enable = s3c2443_clkcon_enable_h, |
265 | .ctrlbit = S3C2443_HCLKCON_DMA4, | 248 | .ctrlbit = S3C2443_HCLKCON_DMA4, |
266 | }, { | 249 | }, { |
267 | .name = "dma", | 250 | .name = "dma", |
268 | .id = 5, | ||
269 | .parent = &clk_h, | 251 | .parent = &clk_h, |
270 | .enable = s3c2443_clkcon_enable_h, | 252 | .enable = s3c2443_clkcon_enable_h, |
271 | .ctrlbit = S3C2443_HCLKCON_DMA5, | 253 | .ctrlbit = S3C2443_HCLKCON_DMA5, |
272 | }, { | 254 | }, { |
273 | .name = "hsmmc", | 255 | .name = "hsmmc", |
274 | .id = 1, | ||
275 | .parent = &clk_h, | 256 | .parent = &clk_h, |
276 | .enable = s3c2443_clkcon_enable_h, | 257 | .enable = s3c2443_clkcon_enable_h, |
277 | .ctrlbit = S3C2443_HCLKCON_HSMMC, | 258 | .ctrlbit = S3C2443_HCLKCON_HSMMC, |
278 | }, { | 259 | }, { |
279 | .name = "gpio", | 260 | .name = "gpio", |
280 | .id = -1, | ||
281 | .parent = &clk_p, | 261 | .parent = &clk_p, |
282 | .enable = s3c2443_clkcon_enable_p, | 262 | .enable = s3c2443_clkcon_enable_p, |
283 | .ctrlbit = S3C2443_PCLKCON_GPIO, | 263 | .ctrlbit = S3C2443_PCLKCON_GPIO, |
284 | }, { | 264 | }, { |
285 | .name = "usb-host", | 265 | .name = "usb-host", |
286 | .id = -1, | ||
287 | .parent = &clk_h, | 266 | .parent = &clk_h, |
288 | .enable = s3c2443_clkcon_enable_h, | 267 | .enable = s3c2443_clkcon_enable_h, |
289 | .ctrlbit = S3C2443_HCLKCON_USBH, | 268 | .ctrlbit = S3C2443_HCLKCON_USBH, |
290 | }, { | 269 | }, { |
291 | .name = "usb-device", | 270 | .name = "usb-device", |
292 | .id = -1, | ||
293 | .parent = &clk_h, | 271 | .parent = &clk_h, |
294 | .enable = s3c2443_clkcon_enable_h, | 272 | .enable = s3c2443_clkcon_enable_h, |
295 | .ctrlbit = S3C2443_HCLKCON_USBD, | 273 | .ctrlbit = S3C2443_HCLKCON_USBD, |
296 | }, { | 274 | }, { |
297 | .name = "lcd", | 275 | .name = "lcd", |
298 | .id = -1, | ||
299 | .parent = &clk_h, | 276 | .parent = &clk_h, |
300 | .enable = s3c2443_clkcon_enable_h, | 277 | .enable = s3c2443_clkcon_enable_h, |
301 | .ctrlbit = S3C2443_HCLKCON_LCDC, | 278 | .ctrlbit = S3C2443_HCLKCON_LCDC, |
302 | 279 | ||
303 | }, { | 280 | }, { |
304 | .name = "timers", | 281 | .name = "timers", |
305 | .id = -1, | ||
306 | .parent = &clk_p, | 282 | .parent = &clk_p, |
307 | .enable = s3c2443_clkcon_enable_p, | 283 | .enable = s3c2443_clkcon_enable_p, |
308 | .ctrlbit = S3C2443_PCLKCON_PWMT, | 284 | .ctrlbit = S3C2443_PCLKCON_PWMT, |
309 | }, { | 285 | }, { |
310 | .name = "cfc", | 286 | .name = "cfc", |
311 | .id = -1, | ||
312 | .parent = &clk_h, | 287 | .parent = &clk_h, |
313 | .enable = s3c2443_clkcon_enable_h, | 288 | .enable = s3c2443_clkcon_enable_h, |
314 | .ctrlbit = S3C2443_HCLKCON_CFC, | 289 | .ctrlbit = S3C2443_HCLKCON_CFC, |
315 | }, { | 290 | }, { |
316 | .name = "ssmc", | 291 | .name = "ssmc", |
317 | .id = -1, | ||
318 | .parent = &clk_h, | 292 | .parent = &clk_h, |
319 | .enable = s3c2443_clkcon_enable_h, | 293 | .enable = s3c2443_clkcon_enable_h, |
320 | .ctrlbit = S3C2443_HCLKCON_SSMC, | 294 | .ctrlbit = S3C2443_HCLKCON_SSMC, |
321 | }, { | 295 | }, { |
322 | .name = "uart", | 296 | .name = "uart", |
323 | .id = 0, | 297 | .devname = "s3c2440-uart.0", |
324 | .parent = &clk_p, | 298 | .parent = &clk_p, |
325 | .enable = s3c2443_clkcon_enable_p, | 299 | .enable = s3c2443_clkcon_enable_p, |
326 | .ctrlbit = S3C2443_PCLKCON_UART0, | 300 | .ctrlbit = S3C2443_PCLKCON_UART0, |
327 | }, { | 301 | }, { |
328 | .name = "uart", | 302 | .name = "uart", |
329 | .id = 1, | 303 | .devname = "s3c2440-uart.1", |
330 | .parent = &clk_p, | 304 | .parent = &clk_p, |
331 | .enable = s3c2443_clkcon_enable_p, | 305 | .enable = s3c2443_clkcon_enable_p, |
332 | .ctrlbit = S3C2443_PCLKCON_UART1, | 306 | .ctrlbit = S3C2443_PCLKCON_UART1, |
333 | }, { | 307 | }, { |
334 | .name = "uart", | 308 | .name = "uart", |
335 | .id = 2, | 309 | .devname = "s3c2440-uart.2", |
336 | .parent = &clk_p, | 310 | .parent = &clk_p, |
337 | .enable = s3c2443_clkcon_enable_p, | 311 | .enable = s3c2443_clkcon_enable_p, |
338 | .ctrlbit = S3C2443_PCLKCON_UART2, | 312 | .ctrlbit = S3C2443_PCLKCON_UART2, |
339 | }, { | 313 | }, { |
340 | .name = "uart", | 314 | .name = "uart", |
341 | .id = 3, | 315 | .devname = "s3c2440-uart.3", |
342 | .parent = &clk_p, | 316 | .parent = &clk_p, |
343 | .enable = s3c2443_clkcon_enable_p, | 317 | .enable = s3c2443_clkcon_enable_p, |
344 | .ctrlbit = S3C2443_PCLKCON_UART3, | 318 | .ctrlbit = S3C2443_PCLKCON_UART3, |
345 | }, { | 319 | }, { |
346 | .name = "rtc", | 320 | .name = "rtc", |
347 | .id = -1, | ||
348 | .parent = &clk_p, | 321 | .parent = &clk_p, |
349 | .enable = s3c2443_clkcon_enable_p, | 322 | .enable = s3c2443_clkcon_enable_p, |
350 | .ctrlbit = S3C2443_PCLKCON_RTC, | 323 | .ctrlbit = S3C2443_PCLKCON_RTC, |
351 | }, { | 324 | }, { |
352 | .name = "watchdog", | 325 | .name = "watchdog", |
353 | .id = -1, | ||
354 | .parent = &clk_p, | 326 | .parent = &clk_p, |
355 | .ctrlbit = S3C2443_PCLKCON_WDT, | 327 | .ctrlbit = S3C2443_PCLKCON_WDT, |
356 | }, { | 328 | }, { |
357 | .name = "ac97", | 329 | .name = "ac97", |
358 | .id = -1, | ||
359 | .parent = &clk_p, | 330 | .parent = &clk_p, |
360 | .ctrlbit = S3C2443_PCLKCON_AC97, | 331 | .ctrlbit = S3C2443_PCLKCON_AC97, |
361 | }, { | 332 | }, { |
362 | .name = "nand", | 333 | .name = "nand", |
363 | .id = -1, | ||
364 | .parent = &clk_h, | 334 | .parent = &clk_h, |
365 | }, { | 335 | }, { |
366 | .name = "usb-bus-host", | 336 | .name = "usb-bus-host", |
367 | .id = -1, | ||
368 | .parent = &clk_usb_bus_host.clk, | 337 | .parent = &clk_usb_bus_host.clk, |
369 | } | 338 | } |
370 | }; | 339 | }; |