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authorDmitry Torokhov <dmitry.torokhov@gmail.com>2009-08-28 01:00:20 -0400
committerDmitry Torokhov <dmitry.torokhov@gmail.com>2009-08-28 01:00:20 -0400
commit4b61bb575b1fb42ab1df228ae7812e5135f656da (patch)
tree03456466e6f678456ea462a7da4b352d1aa03aa3 /arch/arm/plat-s3c24xx/clock-dclk.c
parent805423e84e900e56c834aadee61a020b0d5092c3 (diff)
parent326ba5010a5429a5a528b268b36a5900d4ab0eba (diff)
Merge commit 'v2.6.31-rc8' into next
Diffstat (limited to 'arch/arm/plat-s3c24xx/clock-dclk.c')
-rw-r--r--arch/arm/plat-s3c24xx/clock-dclk.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c
index 5b75a797b5ab..0afb217a775e 100644
--- a/arch/arm/plat-s3c24xx/clock-dclk.c
+++ b/arch/arm/plat-s3c24xx/clock-dclk.c
@@ -129,7 +129,7 @@ static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
129 129
130 /* calculate the MISCCR setting for the clock */ 130 /* calculate the MISCCR setting for the clock */
131 131
132 if (parent == &clk_xtal) 132 if (parent == &clk_mpll)
133 source = S3C2410_MISCCR_CLK0_MPLL; 133 source = S3C2410_MISCCR_CLK0_MPLL;
134 else if (parent == &clk_upll) 134 else if (parent == &clk_upll)
135 source = S3C2410_MISCCR_CLK0_UPLL; 135 source = S3C2410_MISCCR_CLK0_UPLL;