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authorPawel Osciak <p.osciak@samsung.com>2009-11-17 02:41:18 -0500
committerBen Dooks <ben-linux@fluff.org>2009-11-30 20:33:15 -0500
commitd7ab33a0b3511e3d738a7b52f20ee83daede4465 (patch)
tree3820fa14be72d6704390162e4635cc5d12aa8ad4 /arch/arm/plat-s3c/include/plat/regs-fb-v4.h
parentc3fcf5d1a43cc27393f77d07b1323232095173de (diff)
ARM: S3C: Prepare s3c64xx-specific s3c-fb register definition for reuse
S5PC1xx Samsung SOC series has very similar frame buffer hardware, so a lot of the code can be shared. Moved s3c64xx-specific s3c-fb register definitions from mach-s3c6400 to common platform directory as regs-fb-v4.h. The new v4 file will be common for S3C6400, S3C6410, S5PC100 and possibly others. Some s3c64xx series specific defines (palette handling) were left in s3c-6400/mach/regs-fb.h, because it is handled differently in S5PC1xx series. Signed-off-by: Pawel Osciak <p.osciak@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c/include/plat/regs-fb-v4.h')
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-fb-v4.h235
1 files changed, 235 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c/include/plat/regs-fb-v4.h b/arch/arm/plat-s3c/include/plat/regs-fb-v4.h
new file mode 100644
index 000000000000..a60ed0d06c94
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-fb-v4.h
@@ -0,0 +1,235 @@
1/* arch/arm/plat-s3c/include/plat/regs-fb-v4.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - new-style framebuffer register definitions
9 *
10 * This is the register set for the new style framebuffer interface
11 * found from the S3C2443 onwards and specifically the S3C64XX series
12 * S3C6400 and S3C6410.
13 *
14 * The file contains the cpu specific items which change between whichever
15 * architecture is selected. See <plat/regs-fb.h> for the core definitions
16 * that are the same.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21*/
22
23/* include the core definitions here, in case we really do need to
24 * override them at a later date.
25*/
26
27#include <plat/regs-fb.h>
28
29#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
30#define VIDCON1_FSTATUS_EVEN (1 << 15)
31
32/* Video timing controls */
33#define VIDTCON0 (0x10)
34#define VIDTCON1 (0x14)
35#define VIDTCON2 (0x18)
36
37/* Window position controls */
38
39#define WINCON(_win) (0x20 + ((_win) * 4))
40
41/* OSD1 and OSD4 do not have register D */
42
43#define VIDOSD_A(_win) (0x40 + ((_win) * 16))
44#define VIDOSD_B(_win) (0x44 + ((_win) * 16))
45#define VIDOSD_C(_win) (0x48 + ((_win) * 16))
46#define VIDOSD_D(_win) (0x4C + ((_win) * 16))
47
48
49#define VIDINTCON0 (0x130)
50
51#define WxKEYCONy(_win, _con) ((0x140 + ((_win) * 8)) + ((_con) * 4))
52
53/* WINCONx */
54
55#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
56#define WINCONx_CSCWIDTH_SHIFT (26)
57#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
58#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
59
60#define WINCONx_ENLOCAL (1 << 22)
61#define WINCONx_BUFSTATUS (1 << 21)
62#define WINCONx_BUFSEL (1 << 20)
63#define WINCONx_BUFAUTOEN (1 << 19)
64#define WINCONx_YCbCr (1 << 13)
65
66#define WINCON1_LOCALSEL_CAMIF (1 << 23)
67
68#define WINCON2_LOCALSEL_CAMIF (1 << 23)
69#define WINCON2_BLD_PIX (1 << 6)
70
71#define WINCON2_ALPHA_SEL (1 << 1)
72#define WINCON2_BPPMODE_MASK (0xf << 2)
73#define WINCON2_BPPMODE_SHIFT (2)
74#define WINCON2_BPPMODE_1BPP (0x0 << 2)
75#define WINCON2_BPPMODE_2BPP (0x1 << 2)
76#define WINCON2_BPPMODE_4BPP (0x2 << 2)
77#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
78#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
79#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
80#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
81#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
82#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
83#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
84#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
85#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
86#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
87#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
88
89#define WINCON3_BLD_PIX (1 << 6)
90
91#define WINCON3_ALPHA_SEL (1 << 1)
92#define WINCON3_BPPMODE_MASK (0xf << 2)
93#define WINCON3_BPPMODE_SHIFT (2)
94#define WINCON3_BPPMODE_1BPP (0x0 << 2)
95#define WINCON3_BPPMODE_2BPP (0x1 << 2)
96#define WINCON3_BPPMODE_4BPP (0x2 << 2)
97#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
98#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
99#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
100#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
101#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
102#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
103#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
104#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
105#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
106#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
107
108#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
109#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
110#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
111
112#define DITHMODE (0x170)
113#define WINxMAP(_win) (0x180 + ((_win) * 4))
114
115
116#define DITHMODE_R_POS_MASK (0x3 << 5)
117#define DITHMODE_R_POS_SHIFT (5)
118#define DITHMODE_R_POS_8BIT (0x0 << 5)
119#define DITHMODE_R_POS_6BIT (0x1 << 5)
120#define DITHMODE_R_POS_5BIT (0x2 << 5)
121
122#define DITHMODE_G_POS_MASK (0x3 << 3)
123#define DITHMODE_G_POS_SHIFT (3)
124#define DITHMODE_G_POS_8BIT (0x0 << 3)
125#define DITHMODE_G_POS_6BIT (0x1 << 3)
126#define DITHMODE_G_POS_5BIT (0x2 << 3)
127
128#define DITHMODE_B_POS_MASK (0x3 << 1)
129#define DITHMODE_B_POS_SHIFT (1)
130#define DITHMODE_B_POS_8BIT (0x0 << 1)
131#define DITHMODE_B_POS_6BIT (0x1 << 1)
132#define DITHMODE_B_POS_5BIT (0x2 << 1)
133
134#define DITHMODE_DITH_EN (1 << 0)
135
136#define WPALCON (0x1A0)
137
138/* Palette control */
139/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
140 * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
141#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
142#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
143#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
144
145
146/* system specific implementation code for palette sizes, and other
147 * information that changes depending on which architecture is being
148 * compiled.
149*/
150
151/* return true if window _win has OSD register D */
152#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0)
153
154static inline unsigned int s3c_fb_win_pal_size(unsigned int win)
155{
156 if (win < 2)
157 return 256;
158 if (win < 4)
159 return 16;
160 if (win == 4)
161 return 4;
162
163 BUG(); /* shouldn't get here */
164}
165
166static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp)
167{
168 /* all windows can do 1/2 bpp */
169
170 if ((bpp == 25 || bpp == 19) && win == 0)
171 return 0; /* win 0 does not have 19 or 25bpp modes */
172
173 if (bpp == 4 && win == 4)
174 return 0;
175
176 if (bpp == 8 && (win >= 3))
177 return 0; /* win 3/4 cannot do 8bpp in any mode */
178
179 return 1;
180}
181
182static inline int s3c_fb_pal_is16(unsigned int window)
183{
184 return window > 1;
185}
186
187struct s3c_fb_palette {
188 struct fb_bitfield r;
189 struct fb_bitfield g;
190 struct fb_bitfield b;
191 struct fb_bitfield a;
192};
193
194static inline void s3c_fb_init_palette(unsigned int window,
195 struct s3c_fb_palette *palette)
196{
197 if (window < 2) {
198 /* Windows 0/1 are 8/8/8 or A/8/8/8 */
199 palette->r.offset = 16;
200 palette->r.length = 8;
201 palette->g.offset = 8;
202 palette->g.length = 8;
203 palette->b.offset = 0;
204 palette->b.length = 8;
205 } else {
206 /* currently we assume RGB 5/6/5 */
207 palette->r.offset = 11;
208 palette->r.length = 5;
209 palette->g.offset = 5;
210 palette->g.length = 6;
211 palette->b.offset = 0;
212 palette->b.length = 5;
213 }
214}
215
216/* Notes on per-window bpp settings
217 *
218 * Value Win0 Win1 Win2 Win3 Win 4
219 * 0000 1(P) 1(P) 1(P) 1(P) 1(P)
220 * 0001 2(P) 2(P) 2(P) 2(P) 2(P)
221 * 0010 4(P) 4(P) 4(P) 4(P) -none-
222 * 0011 8(P) 8(P) -none- -none- -none-
223 * 0100 -none- 8(A232) 8(A232) -none- -none-
224 * 0101 16(565) 16(565) 16(565) 16(565) 16(565)
225 * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
226 * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
227 * 1000 18(666) 18(666) 18(666) 18(666) 18(666)
228 * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
229 * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
230 * 1011 24(888) 24(888) 24(888) 24(888) 24(888)
231 * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
232 * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
233 * 1110 -none- -none- -none- -none- -none-
234 * 1111 -none- -none- -none- -none- -none-
235*/
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