diff options
author | Ben Dooks <ben-linux@fluff.org> | 2009-11-30 20:24:37 -0500 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2010-01-15 03:10:10 -0500 |
commit | b3bf41be06634d69959a68a2b53e1ffc92f0d103 (patch) | |
tree | 7575fc3d60e9a2f99e74b2862e1b3a43b7df1f92 /arch/arm/plat-s3c/clock.c | |
parent | 13bbd88504bfa0d205fa4121322869d8d7e083d0 (diff) |
ARM: SAMSUNG: Reduce size of struct clk.
Reduce the size of struct clk by 12 bytes and make defining clocks with
common implementation functions easier by moving the set_rate, get_rate,
round_rate and set_parent calls into a new structure called 'struct clk_ops'
and using that instead.
This change does make a few clocks larger as they need their own clk_ops,
but this is outweighed by the number of clocks with either no ops or having
a common set of ops.
Update all the users of this.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c/clock.c')
-rw-r--r-- | arch/arm/plat-s3c/clock.c | 31 |
1 files changed, 17 insertions, 14 deletions
diff --git a/arch/arm/plat-s3c/clock.c b/arch/arm/plat-s3c/clock.c index 619cfa82dcab..fa91125c7e0e 100644 --- a/arch/arm/plat-s3c/clock.c +++ b/arch/arm/plat-s3c/clock.c | |||
@@ -150,8 +150,8 @@ unsigned long clk_get_rate(struct clk *clk) | |||
150 | if (clk->rate != 0) | 150 | if (clk->rate != 0) |
151 | return clk->rate; | 151 | return clk->rate; |
152 | 152 | ||
153 | if (clk->get_rate != NULL) | 153 | if (clk->ops != NULL && clk->ops->get_rate != NULL) |
154 | return (clk->get_rate)(clk); | 154 | return (clk->ops->get_rate)(clk); |
155 | 155 | ||
156 | if (clk->parent != NULL) | 156 | if (clk->parent != NULL) |
157 | return clk_get_rate(clk->parent); | 157 | return clk_get_rate(clk->parent); |
@@ -161,8 +161,8 @@ unsigned long clk_get_rate(struct clk *clk) | |||
161 | 161 | ||
162 | long clk_round_rate(struct clk *clk, unsigned long rate) | 162 | long clk_round_rate(struct clk *clk, unsigned long rate) |
163 | { | 163 | { |
164 | if (!IS_ERR(clk) && clk->round_rate) | 164 | if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate) |
165 | return (clk->round_rate)(clk, rate); | 165 | return (clk->ops->round_rate)(clk, rate); |
166 | 166 | ||
167 | return rate; | 167 | return rate; |
168 | } | 168 | } |
@@ -178,13 +178,14 @@ int clk_set_rate(struct clk *clk, unsigned long rate) | |||
178 | * the clock may have been made this way by choice. | 178 | * the clock may have been made this way by choice. |
179 | */ | 179 | */ |
180 | 180 | ||
181 | WARN_ON(clk->set_rate == NULL); | 181 | WARN_ON(clk->ops == NULL); |
182 | WARN_ON(clk->ops && clk->ops->set_rate == NULL); | ||
182 | 183 | ||
183 | if (clk->set_rate == NULL) | 184 | if (clk->ops == NULL || clk->ops->set_rate == NULL) |
184 | return -EINVAL; | 185 | return -EINVAL; |
185 | 186 | ||
186 | spin_lock(&clocks_lock); | 187 | spin_lock(&clocks_lock); |
187 | ret = (clk->set_rate)(clk, rate); | 188 | ret = (clk->ops->set_rate)(clk, rate); |
188 | spin_unlock(&clocks_lock); | 189 | spin_unlock(&clocks_lock); |
189 | 190 | ||
190 | return ret; | 191 | return ret; |
@@ -204,8 +205,8 @@ int clk_set_parent(struct clk *clk, struct clk *parent) | |||
204 | 205 | ||
205 | spin_lock(&clocks_lock); | 206 | spin_lock(&clocks_lock); |
206 | 207 | ||
207 | if (clk->set_parent) | 208 | if (clk->ops && clk->ops->set_parent) |
208 | ret = (clk->set_parent)(clk, parent); | 209 | ret = (clk->ops->set_parent)(clk, parent); |
209 | 210 | ||
210 | spin_unlock(&clocks_lock); | 211 | spin_unlock(&clocks_lock); |
211 | 212 | ||
@@ -230,6 +231,10 @@ static int clk_default_setrate(struct clk *clk, unsigned long rate) | |||
230 | return 0; | 231 | return 0; |
231 | } | 232 | } |
232 | 233 | ||
234 | static struct clk_ops clk_ops_def_setrate = { | ||
235 | .set_rate = clk_default_setrate, | ||
236 | }; | ||
237 | |||
233 | struct clk clk_xtal = { | 238 | struct clk clk_xtal = { |
234 | .name = "xtal", | 239 | .name = "xtal", |
235 | .id = -1, | 240 | .id = -1, |
@@ -251,7 +256,7 @@ struct clk clk_epll = { | |||
251 | struct clk clk_mpll = { | 256 | struct clk clk_mpll = { |
252 | .name = "mpll", | 257 | .name = "mpll", |
253 | .id = -1, | 258 | .id = -1, |
254 | .set_rate = clk_default_setrate, | 259 | .ops = &clk_ops_def_setrate, |
255 | }; | 260 | }; |
256 | 261 | ||
257 | struct clk clk_upll = { | 262 | struct clk clk_upll = { |
@@ -267,7 +272,6 @@ struct clk clk_f = { | |||
267 | .rate = 0, | 272 | .rate = 0, |
268 | .parent = &clk_mpll, | 273 | .parent = &clk_mpll, |
269 | .ctrlbit = 0, | 274 | .ctrlbit = 0, |
270 | .set_rate = clk_default_setrate, | ||
271 | }; | 275 | }; |
272 | 276 | ||
273 | struct clk clk_h = { | 277 | struct clk clk_h = { |
@@ -276,7 +280,7 @@ struct clk clk_h = { | |||
276 | .rate = 0, | 280 | .rate = 0, |
277 | .parent = NULL, | 281 | .parent = NULL, |
278 | .ctrlbit = 0, | 282 | .ctrlbit = 0, |
279 | .set_rate = clk_default_setrate, | 283 | .ops = &clk_ops_def_setrate, |
280 | }; | 284 | }; |
281 | 285 | ||
282 | struct clk clk_p = { | 286 | struct clk clk_p = { |
@@ -285,7 +289,7 @@ struct clk clk_p = { | |||
285 | .rate = 0, | 289 | .rate = 0, |
286 | .parent = NULL, | 290 | .parent = NULL, |
287 | .ctrlbit = 0, | 291 | .ctrlbit = 0, |
288 | .set_rate = clk_default_setrate, | 292 | .ops = &clk_ops_def_setrate, |
289 | }; | 293 | }; |
290 | 294 | ||
291 | struct clk clk_usb_bus = { | 295 | struct clk clk_usb_bus = { |
@@ -296,7 +300,6 @@ struct clk clk_usb_bus = { | |||
296 | }; | 300 | }; |
297 | 301 | ||
298 | 302 | ||
299 | |||
300 | struct clk s3c24xx_uclk = { | 303 | struct clk s3c24xx_uclk = { |
301 | .name = "uclk", | 304 | .name = "uclk", |
302 | .id = -1, | 305 | .id = -1, |