[ARM] pxa: introduce plat-pxa for PXA common code and add DMA support

1. introduce folder of 'arch/arm/plat-pxa' for common code across different
   PXA processor families

2. initially moved DMA code into plat-pxa

3. common code in <mach/dma.h> moved into <plat/dma.h>, new processors
   should implement its own <mach/dma.h>, provide the following required
   definitions and '#include <plat/dma.h>' in the end:

   - DMAC_REGS_VIRT for mapped virtual address of the DMA registers'
     physical I/O memory

Signed-off-by: Eric Miao <eric.miao@marvell.com>

4 files changed, 238 insertions, 0 deletions

diff --git a/arch/arm/plat-pxa/Kconfig b/arch/arm/plat-pxa/Kconfig
new file mode 100644
index 000000000000..b158e98038ed
--- /dev/null
+++ b/arch/arm/plat-pxa/Kconfig
@@ -0,0 +1,3 @@
+if PLAT_PXA
+
+endif
diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile
new file mode 100644
index 000000000000..dcc3ceaf717f
--- /dev/null
+++ b/arch/arm/plat-pxa/Makefile
@@ -0,0 +1,6 @@
+#
+# Makefile for code common across different PXA processor families
+#
+
+obj-y   := dma.o
+
diff --git a/arch/arm/plat-pxa/dma.c b/arch/arm/plat-pxa/dma.c
new file mode 100644
index 000000000000..70aeee407f7d
--- /dev/null
+++ b/arch/arm/plat-pxa/dma.c
@@ -0,0 +1,144 @@
+/*
+ *  linux/arch/arm/plat-pxa/dma.c
+ *
+ *  PXA DMA registration and IRQ dispatching
+ *
+ *  Author:     Nicolas Pitre
+ *  Created:    Nov 15, 2001
+ *  Copyright:  MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <mach/hardware.h>
+#include <mach/dma.h>
+
+struct dma_channel {
+        char *name;
+        pxa_dma_prio prio;
+        void (*irq_handler)(int, void *);
+        void *data;
+};
+
+static struct dma_channel *dma_channels;
+static int num_dma_channels;
+
+int pxa_request_dma (char *name, pxa_dma_prio prio,
+                        void (*irq_handler)(int, void *),
+                        void *data)
+{
+        unsigned long flags;
+        int i, found = 0;
+
+        /* basic sanity checks */
+        if (!name || !irq_handler)
+                return -EINVAL;
+
+        local_irq_save(flags);
+
+        do {
+                /* try grabbing a DMA channel with the requested priority */
+                for (i = 0; i < num_dma_channels; i++) {
+                        if ((dma_channels[i].prio == prio) &&
+                            !dma_channels[i].name) {
+                                found = 1;
+                                break;
+                        }
+                }
+                /* if requested prio group is full, try a hier priority */
+        } while (!found && prio--);
+
+        if (found) {
+                DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
+                dma_channels[i].name = name;
+                dma_channels[i].irq_handler = irq_handler;
+                dma_channels[i].data = data;
+        } else {
+                printk (KERN_WARNING "No more available DMA channels for %s\n", name);
+                i = -ENODEV;
+        }
+
+        local_irq_restore(flags);
+        return i;
+}
+
+void pxa_free_dma (int dma_ch)
+{
+        unsigned long flags;
+
+        if (!dma_channels[dma_ch].name) {
+                printk (KERN_CRIT
+                        "%s: trying to free channel %d which is already freed\n",
+                        __func__, dma_ch);
+                return;
+        }
+
+        local_irq_save(flags);
+        DCSR(dma_ch) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
+        dma_channels[dma_ch].name = NULL;
+        local_irq_restore(flags);
+}
+
+static irqreturn_t dma_irq_handler(int irq, void *dev_id)
+{
+        int i, dint = DINT;
+
+        for (i = 0; i < num_dma_channels; i++) {
+                if (dint & (1 << i)) {
+                        struct dma_channel *channel = &dma_channels[i];
+                        if (channel->name && channel->irq_handler) {
+                                channel->irq_handler(i, channel->data);
+                        } else {
+                                /*
+                                 * IRQ for an unregistered DMA channel:
+                                 * let's clear the interrupts and disable it.
+                                 */
+                                printk (KERN_WARNING "spurious IRQ for DMA channel %d\n", i);
+                                DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
+                        }
+                }
+        }
+        return IRQ_HANDLED;
+}
+
+int __init pxa_init_dma(int irq, int num_ch)
+{
+        int i, ret;
+
+        dma_channels = kzalloc(sizeof(struct dma_channel) * num_ch, GFP_KERNEL);
+        if (dma_channels == NULL)
+                return -ENOMEM;
+
+        /* dma channel priorities on pxa2xx processors:
+         * ch 0 - 3,  16 - 19  <--> (0) DMA_PRIO_HIGH
+         * ch 4 - 7,  20 - 23  <--> (1) DMA_PRIO_MEDIUM
+         * ch 8 - 15, 24 - 31  <--> (2) DMA_PRIO_LOW
+         */
+        for (i = 0; i < num_ch; i++) {
+                DCSR(i) = 0;
+                dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW);
+        }
+
+        ret = request_irq(irq, dma_irq_handler, IRQF_DISABLED, "DMA", NULL);
+        if (ret) {
+                printk (KERN_CRIT "Wow!  Can't register IRQ for DMA\n");
+                kfree(dma_channels);
+                return ret;
+        }
+
+        num_dma_channels = num_ch;
+        return 0;
+}
+
+EXPORT_SYMBOL(pxa_request_dma);
+EXPORT_SYMBOL(pxa_free_dma);
diff --git a/arch/arm/plat-pxa/include/plat/dma.h b/arch/arm/plat-pxa/include/plat/dma.h
new file mode 100644
index 000000000000..a7b91dc06852
--- /dev/null
+++ b/arch/arm/plat-pxa/include/plat/dma.h
@@ -0,0 +1,85 @@
+#ifndef __PLAT_DMA_H
+#define __PLAT_DMA_H
+
+#define DMAC_REG(x)     (*((volatile u32 *)(DMAC_REGS_VIRT + (x))))
+
+#define DCSR(n)         DMAC_REG((n) << 2)
+#define DALGN           DMAC_REG(0x00a0)  /* DMA Alignment Register */
+#define DINT            DMAC_REG(0x00f0)  /* DMA Interrupt Register */
+#define DDADR(n)        DMAC_REG(0x0200 + ((n) << 4))
+#define DSADR(n)        DMAC_REG(0x0204 + ((n) << 4))
+#define DTADR(n)        DMAC_REG(0x0208 + ((n) << 4))
+#define DCMD(n)         DMAC_REG(0x020c + ((n) << 4))
+#define DRCMR(n)        DMAC_REG((((n) < 64) ? 0x0100 : 0x1100) + \
+                                 (((n) & 0x3f) << 2))
+
+#define DCSR_RUN        (1 << 31)       /* Run Bit (read / write) */
+#define DCSR_NODESC     (1 << 30)       /* No-Descriptor Fetch (read / write) */
+#define DCSR_STOPIRQEN  (1 << 29)       /* Stop Interrupt Enable (read / write) */
+#define DCSR_REQPEND    (1 << 8)        /* Request Pending (read-only) */
+#define DCSR_STOPSTATE  (1 << 3)        /* Stop State (read-only) */
+#define DCSR_ENDINTR    (1 << 2)        /* End Interrupt (read / write) */
+#define DCSR_STARTINTR  (1 << 1)        /* Start Interrupt (read / write) */
+#define DCSR_BUSERR     (1 << 0)        /* Bus Error Interrupt (read / write) */
+
+#define DCSR_EORIRQEN   (1 << 28)       /* End of Receive Interrupt Enable (R/W) */
+#define DCSR_EORJMPEN   (1 << 27)       /* Jump to next descriptor on EOR */
+#define DCSR_EORSTOPEN  (1 << 26)       /* STOP on an EOR */
+#define DCSR_SETCMPST   (1 << 25)       /* Set Descriptor Compare Status */
+#define DCSR_CLRCMPST   (1 << 24)       /* Clear Descriptor Compare Status */
+#define DCSR_CMPST      (1 << 10)       /* The Descriptor Compare Status */
+#define DCSR_EORINTR    (1 << 9)        /* The end of Receive */
+
+#define DRCMR_MAPVLD    (1 << 7)        /* Map Valid (read / write) */
+#define DRCMR_CHLNUM    0x1f            /* mask for Channel Number (read / write) */
+
+#define DDADR_DESCADDR  0xfffffff0      /* Address of next descriptor (mask) */
+#define DDADR_STOP      (1 << 0)        /* Stop (read / write) */
+
+#define DCMD_INCSRCADDR (1 << 31)       /* Source Address Increment Setting. */
+#define DCMD_INCTRGADDR (1 << 30)       /* Target Address Increment Setting. */
+#define DCMD_FLOWSRC    (1 << 29)       /* Flow Control by the source. */
+#define DCMD_FLOWTRG    (1 << 28)       /* Flow Control by the target. */
+#define DCMD_STARTIRQEN (1 << 22)       /* Start Interrupt Enable */
+#define DCMD_ENDIRQEN   (1 << 21)       /* End Interrupt Enable */
+#define DCMD_ENDIAN     (1 << 18)       /* Device Endian-ness. */
+#define DCMD_BURST8     (1 << 16)       /* 8 byte burst */
+#define DCMD_BURST16    (2 << 16)       /* 16 byte burst */
+#define DCMD_BURST32    (3 << 16)       /* 32 byte burst */
+#define DCMD_WIDTH1     (1 << 14)       /* 1 byte width */
+#define DCMD_WIDTH2     (2 << 14)       /* 2 byte width (HalfWord) */
+#define DCMD_WIDTH4     (3 << 14)       /* 4 byte width (Word) */
+#define DCMD_LENGTH     0x01fff         /* length mask (max = 8K - 1) */
+
+/*
+ * Descriptor structure for PXA's DMA engine
+ * Note: this structure must always be aligned to a 16-byte boundary.
+ */
+
+typedef struct pxa_dma_desc {
+        volatile u32 ddadr;     /* Points to the next descriptor + flags */
+        volatile u32 dsadr;     /* DSADR value for the current transfer */
+        volatile u32 dtadr;     /* DTADR value for the current transfer */
+        volatile u32 dcmd;      /* DCMD value for the current transfer */
+} pxa_dma_desc;
+
+typedef enum {
+        DMA_PRIO_HIGH = 0,
+        DMA_PRIO_MEDIUM = 1,
+        DMA_PRIO_LOW = 2
+} pxa_dma_prio;
+
+/*
+ * DMA registration
+ */
+
+int __init pxa_init_dma(int irq, int num_ch);
+
+int pxa_request_dma (char *name,
+                         pxa_dma_prio prio,
+                         void (*irq_handler)(int, void *),
+                         void *data);
+
+void pxa_free_dma (int dma_ch);
+
+#endif /* __PLAT_DMA_H */