[ARM] pxa: move ssp into common plat-pxa

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>

4 files changed, 425 insertions, 0 deletions

diff --git a/arch/arm/plat-pxa/Kconfig b/arch/arm/plat-pxa/Kconfig
index b158e98038ed..da53395a17c6 100644
--- a/arch/arm/plat-pxa/Kconfig
+++ b/arch/arm/plat-pxa/Kconfig
@@ -1,3 +1,8 @@
 if PLAT_PXA
 
+config PXA_SSP
+        tristate
+        help
+          Enable support for PXA2xx SSP ports
+
 endif
diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile
index 0264bfb0ca4f..4aacdd12c9cc 100644
--- a/arch/arm/plat-pxa/Makefile
+++ b/arch/arm/plat-pxa/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_PXA3xx)		+= mfp.o
 obj-$(CONFIG_ARCH_MMP)          += mfp.o
 
 obj-$(CONFIG_HAVE_PWM)          += pwm.o
+obj-$(CONFIG_PXA_SSP)           += ssp.o
diff --git a/arch/arm/plat-pxa/include/plat/ssp.h b/arch/arm/plat-pxa/include/plat/ssp.h
new file mode 100644
index 000000000000..4c4ce62390d0
--- /dev/null
+++ b/arch/arm/plat-pxa/include/plat/ssp.h
@@ -0,0 +1,196 @@
+/*
+ *  ssp.h
+ *
+ *  Copyright (C) 2003 Russell King, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This driver supports the following PXA CPU/SSP ports:-
+ *
+ *       PXA250     SSP
+ *       PXA255     SSP, NSSP
+ *       PXA26x     SSP, NSSP, ASSP
+ *       PXA27x     SSP1, SSP2, SSP3
+ *       PXA3xx     SSP1, SSP2, SSP3, SSP4
+ */
+
+#ifndef __ASM_ARCH_SSP_H
+#define __ASM_ARCH_SSP_H
+
+#include <linux/list.h>
+#include <linux/io.h>
+
+/*
+ * SSP Serial Port Registers
+ * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
+ * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
+ */
+
+#define SSCR0           (0x00)  /* SSP Control Register 0 */
+#define SSCR1           (0x04)  /* SSP Control Register 1 */
+#define SSSR            (0x08)  /* SSP Status Register */
+#define SSITR           (0x0C)  /* SSP Interrupt Test Register */
+#define SSDR            (0x10)  /* SSP Data Write/Data Read Register */
+
+#define SSTO            (0x28)  /* SSP Time Out Register */
+#define SSPSP           (0x2C)  /* SSP Programmable Serial Protocol */
+#define SSTSA           (0x30)  /* SSP Tx Timeslot Active */
+#define SSRSA           (0x34)  /* SSP Rx Timeslot Active */
+#define SSTSS           (0x38)  /* SSP Timeslot Status */
+#define SSACD           (0x3C)  /* SSP Audio Clock Divider */
+
+#if defined(CONFIG_PXA3xx)
+#define SSACDD          (0x40)  /* SSP Audio Clock Dither Divider */
+#endif
+
+/* Common PXA2xx bits first */
+#define SSCR0_DSS       (0x0000000f)    /* Data Size Select (mask) */
+#define SSCR0_DataSize(x)  ((x) - 1)    /* Data Size Select [4..16] */
+#define SSCR0_FRF       (0x00000030)    /* FRame Format (mask) */
+#define SSCR0_Motorola  (0x0 << 4)      /* Motorola's Serial Peripheral Interface (SPI) */
+#define SSCR0_TI        (0x1 << 4)      /* Texas Instruments' Synchronous Serial Protocol (SSP) */
+#define SSCR0_National  (0x2 << 4)      /* National Microwire */
+#define SSCR0_ECS       (1 << 6)        /* External clock select */
+#define SSCR0_SSE       (1 << 7)        /* Synchronous Serial Port Enable */
+#define SSCR0_SCR(x)    ((x) << 8)      /* Serial Clock Rate (mask) */
+
+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
+#define SSCR0_EDSS      (1 << 20)       /* Extended data size select */
+#define SSCR0_NCS       (1 << 21)       /* Network clock select */
+#define SSCR0_RIM       (1 << 22)       /* Receive FIFO overrrun interrupt mask */
+#define SSCR0_TUM       (1 << 23)       /* Transmit FIFO underrun interrupt mask */
+#define SSCR0_FRDC      (0x07000000)    /* Frame rate divider control (mask) */
+#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24)  /* Time slots per frame [1..8] */
+#define SSCR0_ACS       (1 << 30)       /* Audio clock select */
+#define SSCR0_MOD       (1 << 31)       /* Mode (normal or network) */
+#endif
+
+#if defined(CONFIG_PXA3xx)
+#define SSCR0_FPCKE     (1 << 29)       /* FIFO packing enable */
+#endif
+
+#define SSCR1_RIE       (1 << 0)        /* Receive FIFO Interrupt Enable */
+#define SSCR1_TIE       (1 << 1)        /* Transmit FIFO Interrupt Enable */
+#define SSCR1_LBM       (1 << 2)        /* Loop-Back Mode */
+#define SSCR1_SPO       (1 << 3)        /* Motorola SPI SSPSCLK polarity setting */
+#define SSCR1_SPH       (1 << 4)        /* Motorola SPI SSPSCLK phase setting */
+#define SSCR1_MWDS      (1 << 5)        /* Microwire Transmit Data Size */
+#define SSCR1_TFT       (0x000003c0)    /* Transmit FIFO Threshold (mask) */
+#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
+#define SSCR1_RFT       (0x00003c00)    /* Receive FIFO Threshold (mask) */
+#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
+
+#define SSSR_TNF        (1 << 2)        /* Transmit FIFO Not Full */
+#define SSSR_RNE        (1 << 3)        /* Receive FIFO Not Empty */
+#define SSSR_BSY        (1 << 4)        /* SSP Busy */
+#define SSSR_TFS        (1 << 5)        /* Transmit FIFO Service Request */
+#define SSSR_RFS        (1 << 6)        /* Receive FIFO Service Request */
+#define SSSR_ROR        (1 << 7)        /* Receive FIFO Overrun */
+
+#define SSCR0_TIM               (1 << 23)       /* Transmit FIFO Under Run Interrupt Mask */
+#define SSCR0_RIM               (1 << 22)       /* Receive FIFO Over Run interrupt Mask */
+#define SSCR0_NCS               (1 << 21)       /* Network Clock Select */
+#define SSCR0_EDSS              (1 << 20)       /* Extended Data Size Select */
+
+/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
+#define SSCR0_TISSP             (1 << 4)        /* TI Sync Serial Protocol */
+#define SSCR0_PSP               (3 << 4)        /* PSP - Programmable Serial Protocol */
+#define SSCR1_TTELP             (1 << 31)       /* TXD Tristate Enable Last Phase */
+#define SSCR1_TTE               (1 << 30)       /* TXD Tristate Enable */
+#define SSCR1_EBCEI             (1 << 29)       /* Enable Bit Count Error interrupt */
+#define SSCR1_SCFR              (1 << 28)       /* Slave Clock free Running */
+#define SSCR1_ECRA              (1 << 27)       /* Enable Clock Request A */
+#define SSCR1_ECRB              (1 << 26)       /* Enable Clock request B */
+#define SSCR1_SCLKDIR           (1 << 25)       /* Serial Bit Rate Clock Direction */
+#define SSCR1_SFRMDIR           (1 << 24)       /* Frame Direction */
+#define SSCR1_RWOT              (1 << 23)       /* Receive Without Transmit */
+#define SSCR1_TRAIL             (1 << 22)       /* Trailing Byte */
+#define SSCR1_TSRE              (1 << 21)       /* Transmit Service Request Enable */
+#define SSCR1_RSRE              (1 << 20)       /* Receive Service Request Enable */
+#define SSCR1_TINTE             (1 << 19)       /* Receiver Time-out Interrupt enable */
+#define SSCR1_PINTE             (1 << 18)       /* Peripheral Trailing Byte Interupt Enable */
+#define SSCR1_IFS               (1 << 16)       /* Invert Frame Signal */
+#define SSCR1_STRF              (1 << 15)       /* Select FIFO or EFWR */
+#define SSCR1_EFWR              (1 << 14)       /* Enable FIFO Write/Read */
+
+#define SSSR_BCE                (1 << 23)       /* Bit Count Error */
+#define SSSR_CSS                (1 << 22)       /* Clock Synchronisation Status */
+#define SSSR_TUR                (1 << 21)       /* Transmit FIFO Under Run */
+#define SSSR_EOC                (1 << 20)       /* End Of Chain */
+#define SSSR_TINT               (1 << 19)       /* Receiver Time-out Interrupt */
+#define SSSR_PINT               (1 << 18)       /* Peripheral Trailing Byte Interrupt */
+
+#if defined(CONFIG_PXA3xx)
+#define SSPSP_EDMYSTOP(x)       ((x) << 28)     /* Extended Dummy Stop */
+#define SSPSP_EDMYSTRT(x)       ((x) << 26)     /* Extended Dummy Start */
+#endif
+
+#define SSPSP_FSRT              (1 << 25)       /* Frame Sync Relative Timing */
+#define SSPSP_DMYSTOP(x)        ((x) << 23)     /* Dummy Stop */
+#define SSPSP_SFRMWDTH(x)       ((x) << 16)     /* Serial Frame Width */
+#define SSPSP_SFRMDLY(x)        ((x) << 9)      /* Serial Frame Delay */
+#define SSPSP_DMYSTRT(x)        ((x) << 7)      /* Dummy Start */
+#define SSPSP_STRTDLY(x)        ((x) << 4)      /* Start Delay */
+#define SSPSP_ETDS              (1 << 3)        /* End of Transfer data State */
+#define SSPSP_SFRMP             (1 << 2)        /* Serial Frame Polarity */
+#define SSPSP_SCMODE(x)         ((x) << 0)      /* Serial Bit Rate Clock Mode */
+
+#define SSACD_SCDB              (1 << 3)        /* SSPSYSCLK Divider Bypass */
+#define SSACD_ACPS(x)           ((x) << 4)      /* Audio clock PLL select */
+#define SSACD_ACDS(x)           ((x) << 0)      /* Audio clock divider select */
+#if defined(CONFIG_PXA3xx)
+#define SSACD_SCDX8             (1 << 7)        /* SYSCLK division ratio select */
+#endif
+
+enum pxa_ssp_type {
+        SSP_UNDEFINED = 0,
+        PXA25x_SSP,  /* pxa 210, 250, 255, 26x */
+        PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
+        PXA27x_SSP,
+};
+
+struct ssp_device {
+        struct platform_device *pdev;
+        struct list_head        node;
+
+        struct clk      *clk;
+        void __iomem    *mmio_base;
+        unsigned long   phys_base;
+
+        const char      *label;
+        int             port_id;
+        int             type;
+        int             use_count;
+        int             irq;
+        int             drcmr_rx;
+        int             drcmr_tx;
+};
+
+/**
+ * ssp_write_reg - Write to a SSP register
+ *
+ * @dev: SSP device to access
+ * @reg: Register to write to
+ * @val: Value to be written.
+ */
+static inline void ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val)
+{
+        __raw_writel(val, dev->mmio_base + reg);
+}
+
+/**
+ * ssp_read_reg - Read from a SSP register
+ *
+ * @dev: SSP device to access
+ * @reg: Register to read from
+ */
+static inline u32 ssp_read_reg(struct ssp_device *dev, u32 reg)
+{
+        return __raw_readl(dev->mmio_base + reg);
+}
+
+struct ssp_device *ssp_request(int port, const char *label);
+void ssp_free(struct ssp_device *);
+#endif /* __ASM_ARCH_SSP_H */
diff --git a/arch/arm/plat-pxa/ssp.c b/arch/arm/plat-pxa/ssp.c
new file mode 100644
index 000000000000..5fe230178f0a
--- /dev/null
+++ b/arch/arm/plat-pxa/ssp.c
@@ -0,0 +1,223 @@
+/*
+ *  linux/arch/arm/mach-pxa/ssp.c
+ *
+ *  based on linux/arch/arm/mach-sa1100/ssp.c by Russell King
+ *
+ *  Copyright (C) 2003 Russell King.
+ *  Copyright (C) 2003 Wolfson Microelectronics PLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  PXA2xx SSP driver.  This provides the generic core for simple
+ *  IO-based SSP applications and allows easy port setup for DMA access.
+ *
+ *  Author: Liam Girdwood <liam.girdwood@wolfsonmicro.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/mutex.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <asm/irq.h>
+#include <mach/hardware.h>
+#include <plat/ssp.h>
+
+static DEFINE_MUTEX(ssp_lock);
+static LIST_HEAD(ssp_list);
+
+struct ssp_device *ssp_request(int port, const char *label)
+{
+        struct ssp_device *ssp = NULL;
+
+        mutex_lock(&ssp_lock);
+
+        list_for_each_entry(ssp, &ssp_list, node) {
+                if (ssp->port_id == port && ssp->use_count == 0) {
+                        ssp->use_count++;
+                        ssp->label = label;
+                        break;
+                }
+        }
+
+        mutex_unlock(&ssp_lock);
+
+        if (&ssp->node == &ssp_list)
+                return NULL;
+
+        return ssp;
+}
+EXPORT_SYMBOL(ssp_request);
+
+void ssp_free(struct ssp_device *ssp)
+{
+        mutex_lock(&ssp_lock);
+        if (ssp->use_count) {
+                ssp->use_count--;
+                ssp->label = NULL;
+        } else
+                dev_err(&ssp->pdev->dev, "device already free\n");
+        mutex_unlock(&ssp_lock);
+}
+EXPORT_SYMBOL(ssp_free);
+
+static int __devinit ssp_probe(struct platform_device *pdev)
+{
+        const struct platform_device_id *id = platform_get_device_id(pdev);
+        struct resource *res;
+        struct ssp_device *ssp;
+        int ret = 0;
+
+        ssp = kzalloc(sizeof(struct ssp_device), GFP_KERNEL);
+        if (ssp == NULL) {
+                dev_err(&pdev->dev, "failed to allocate memory");
+                return -ENOMEM;
+        }
+        ssp->pdev = pdev;
+
+        ssp->clk = clk_get(&pdev->dev, NULL);
+        if (IS_ERR(ssp->clk)) {
+                ret = PTR_ERR(ssp->clk);
+                goto err_free;
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (res == NULL) {
+                dev_err(&pdev->dev, "no memory resource defined\n");
+                ret = -ENODEV;
+                goto err_free_clk;
+        }
+
+        res = request_mem_region(res->start, res->end - res->start + 1,
+                        pdev->name);
+        if (res == NULL) {
+                dev_err(&pdev->dev, "failed to request memory resource\n");
+                ret = -EBUSY;
+                goto err_free_clk;
+        }
+
+        ssp->phys_base = res->start;
+
+        ssp->mmio_base = ioremap(res->start, res->end - res->start + 1);
+        if (ssp->mmio_base == NULL) {
+                dev_err(&pdev->dev, "failed to ioremap() registers\n");
+                ret = -ENODEV;
+                goto err_free_mem;
+        }
+
+        ssp->irq = platform_get_irq(pdev, 0);
+        if (ssp->irq < 0) {
+                dev_err(&pdev->dev, "no IRQ resource defined\n");
+                ret = -ENODEV;
+                goto err_free_io;
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
+        if (res == NULL) {
+                dev_err(&pdev->dev, "no SSP RX DRCMR defined\n");
+                ret = -ENODEV;
+                goto err_free_io;
+        }
+        ssp->drcmr_rx = res->start;
+
+        res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
+        if (res == NULL) {
+                dev_err(&pdev->dev, "no SSP TX DRCMR defined\n");
+                ret = -ENODEV;
+                goto err_free_io;
+        }
+        ssp->drcmr_tx = res->start;
+
+        /* PXA2xx/3xx SSP ports starts from 1 and the internal pdev->id
+         * starts from 0, do a translation here
+         */
+        ssp->port_id = pdev->id + 1;
+        ssp->use_count = 0;
+        ssp->type = (int)id->driver_data;
+
+        mutex_lock(&ssp_lock);
+        list_add(&ssp->node, &ssp_list);
+        mutex_unlock(&ssp_lock);
+
+        platform_set_drvdata(pdev, ssp);
+        return 0;
+
+err_free_io:
+        iounmap(ssp->mmio_base);
+err_free_mem:
+        release_mem_region(res->start, res->end - res->start + 1);
+err_free_clk:
+        clk_put(ssp->clk);
+err_free:
+        kfree(ssp);
+        return ret;
+}
+
+static int __devexit ssp_remove(struct platform_device *pdev)
+{
+        struct resource *res;
+        struct ssp_device *ssp;
+
+        ssp = platform_get_drvdata(pdev);
+        if (ssp == NULL)
+                return -ENODEV;
+
+        iounmap(ssp->mmio_base);
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        release_mem_region(res->start, res->end - res->start + 1);
+
+        clk_put(ssp->clk);
+
+        mutex_lock(&ssp_lock);
+        list_del(&ssp->node);
+        mutex_unlock(&ssp_lock);
+
+        kfree(ssp);
+        return 0;
+}
+
+static const struct platform_device_id ssp_id_table[] = {
+        { "pxa25x-ssp",         PXA25x_SSP },
+        { "pxa25x-nssp",        PXA25x_NSSP },
+        { "pxa27x-ssp",         PXA27x_SSP },
+        { },
+};
+
+static struct platform_driver ssp_driver = {
+        .probe          = ssp_probe,
+        .remove         = __devexit_p(ssp_remove),
+        .driver         = {
+                .owner  = THIS_MODULE,
+                .name   = "pxa2xx-ssp",
+        },
+        .id_table       = ssp_id_table,
+};
+
+static int __init pxa_ssp_init(void)
+{
+        return platform_driver_register(&ssp_driver);
+}
+
+static void __exit pxa_ssp_exit(void)
+{
+        platform_driver_unregister(&ssp_driver);
+}
+
+arch_initcall(pxa_ssp_init);
+module_exit(pxa_ssp_exit);
+
+MODULE_DESCRIPTION("PXA SSP driver");
+MODULE_AUTHOR("Liam Girdwood");
+MODULE_LICENSE("GPL");