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authorArnd Bergmann <arnd@arndb.de>2011-10-31 17:44:18 -0400
committerArnd Bergmann <arnd@arndb.de>2011-10-31 17:44:18 -0400
commit43872fa788060eef91ae437957e0a5e39f1c56fd (patch)
treedba464da61167d84b4f7470edebd5a769a78f9ee /arch/arm/plat-pxa
parent91fed558d0f33c74477569f50ed883fe6d430f1f (diff)
parentf55be1bf52aad524dc1bf556ae26c90262c87825 (diff)
Merge branch 'depends/rmk/gpio' into next/fixes
This sorts out merge conflicts with the arm/gpio branch that already got merged into mainline Linux. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/plat-pxa')
-rw-r--r--arch/arm/plat-pxa/Makefile1
-rw-r--r--arch/arm/plat-pxa/gpio.c338
-rw-r--r--arch/arm/plat-pxa/include/plat/gpio-pxa.h44
-rw-r--r--arch/arm/plat-pxa/include/plat/gpio.h40
4 files changed, 47 insertions, 376 deletions
diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile
index 3aca5ba0f876..f302d048392d 100644
--- a/arch/arm/plat-pxa/Makefile
+++ b/arch/arm/plat-pxa/Makefile
@@ -4,7 +4,6 @@
4 4
5obj-y := dma.o 5obj-y := dma.o
6 6
7obj-$(CONFIG_GENERIC_GPIO) += gpio.o
8obj-$(CONFIG_PXA3xx) += mfp.o 7obj-$(CONFIG_PXA3xx) += mfp.o
9obj-$(CONFIG_PXA95x) += mfp.o 8obj-$(CONFIG_PXA95x) += mfp.o
10obj-$(CONFIG_ARCH_MMP) += mfp.o 9obj-$(CONFIG_ARCH_MMP) += mfp.o
diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c
deleted file mode 100644
index 0db7615c2cf0..000000000000
--- a/arch/arm/plat-pxa/gpio.c
+++ /dev/null
@@ -1,338 +0,0 @@
1/*
2 * linux/arch/arm/plat-pxa/gpio.c
3 *
4 * Generic PXA GPIO handling
5 *
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/irq.h>
17#include <linux/io.h>
18#include <linux/syscore_ops.h>
19#include <linux/slab.h>
20
21#include <mach/gpio.h>
22
23int pxa_last_gpio;
24
25struct pxa_gpio_chip {
26 struct gpio_chip chip;
27 void __iomem *regbase;
28 char label[10];
29
30 unsigned long irq_mask;
31 unsigned long irq_edge_rise;
32 unsigned long irq_edge_fall;
33
34#ifdef CONFIG_PM
35 unsigned long saved_gplr;
36 unsigned long saved_gpdr;
37 unsigned long saved_grer;
38 unsigned long saved_gfer;
39#endif
40};
41
42static DEFINE_SPINLOCK(gpio_lock);
43static struct pxa_gpio_chip *pxa_gpio_chips;
44
45#define for_each_gpio_chip(i, c) \
46 for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
47
48static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
49{
50 return container_of(c, struct pxa_gpio_chip, chip)->regbase;
51}
52
53static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
54{
55 return &pxa_gpio_chips[gpio_to_bank(gpio)];
56}
57
58static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
59{
60 void __iomem *base = gpio_chip_base(chip);
61 uint32_t value, mask = 1 << offset;
62 unsigned long flags;
63
64 spin_lock_irqsave(&gpio_lock, flags);
65
66 value = __raw_readl(base + GPDR_OFFSET);
67 if (__gpio_is_inverted(chip->base + offset))
68 value |= mask;
69 else
70 value &= ~mask;
71 __raw_writel(value, base + GPDR_OFFSET);
72
73 spin_unlock_irqrestore(&gpio_lock, flags);
74 return 0;
75}
76
77static int pxa_gpio_direction_output(struct gpio_chip *chip,
78 unsigned offset, int value)
79{
80 void __iomem *base = gpio_chip_base(chip);
81 uint32_t tmp, mask = 1 << offset;
82 unsigned long flags;
83
84 __raw_writel(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
85
86 spin_lock_irqsave(&gpio_lock, flags);
87
88 tmp = __raw_readl(base + GPDR_OFFSET);
89 if (__gpio_is_inverted(chip->base + offset))
90 tmp &= ~mask;
91 else
92 tmp |= mask;
93 __raw_writel(tmp, base + GPDR_OFFSET);
94
95 spin_unlock_irqrestore(&gpio_lock, flags);
96 return 0;
97}
98
99static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
100{
101 return __raw_readl(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
102}
103
104static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
105{
106 __raw_writel(1 << offset, gpio_chip_base(chip) +
107 (value ? GPSR_OFFSET : GPCR_OFFSET));
108}
109
110static int __init pxa_init_gpio_chip(int gpio_end)
111{
112 int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
113 struct pxa_gpio_chip *chips;
114
115 chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
116 if (chips == NULL) {
117 pr_err("%s: failed to allocate GPIO chips\n", __func__);
118 return -ENOMEM;
119 }
120
121 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
122 struct gpio_chip *c = &chips[i].chip;
123
124 sprintf(chips[i].label, "gpio-%d", i);
125 chips[i].regbase = GPIO_BANK(i);
126
127 c->base = gpio;
128 c->label = chips[i].label;
129
130 c->direction_input = pxa_gpio_direction_input;
131 c->direction_output = pxa_gpio_direction_output;
132 c->get = pxa_gpio_get;
133 c->set = pxa_gpio_set;
134
135 /* number of GPIOs on last bank may be less than 32 */
136 c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
137 gpiochip_add(c);
138 }
139 pxa_gpio_chips = chips;
140 return 0;
141}
142
143/* Update only those GRERx and GFERx edge detection register bits if those
144 * bits are set in c->irq_mask
145 */
146static inline void update_edge_detect(struct pxa_gpio_chip *c)
147{
148 uint32_t grer, gfer;
149
150 grer = __raw_readl(c->regbase + GRER_OFFSET) & ~c->irq_mask;
151 gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~c->irq_mask;
152 grer |= c->irq_edge_rise & c->irq_mask;
153 gfer |= c->irq_edge_fall & c->irq_mask;
154 __raw_writel(grer, c->regbase + GRER_OFFSET);
155 __raw_writel(gfer, c->regbase + GFER_OFFSET);
156}
157
158static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
159{
160 struct pxa_gpio_chip *c;
161 int gpio = irq_to_gpio(d->irq);
162 unsigned long gpdr, mask = GPIO_bit(gpio);
163
164 c = gpio_to_pxachip(gpio);
165
166 if (type == IRQ_TYPE_PROBE) {
167 /* Don't mess with enabled GPIOs using preconfigured edges or
168 * GPIOs set to alternate function or to output during probe
169 */
170 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
171 return 0;
172
173 if (__gpio_is_occupied(gpio))
174 return 0;
175
176 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
177 }
178
179 gpdr = __raw_readl(c->regbase + GPDR_OFFSET);
180
181 if (__gpio_is_inverted(gpio))
182 __raw_writel(gpdr | mask, c->regbase + GPDR_OFFSET);
183 else
184 __raw_writel(gpdr & ~mask, c->regbase + GPDR_OFFSET);
185
186 if (type & IRQ_TYPE_EDGE_RISING)
187 c->irq_edge_rise |= mask;
188 else
189 c->irq_edge_rise &= ~mask;
190
191 if (type & IRQ_TYPE_EDGE_FALLING)
192 c->irq_edge_fall |= mask;
193 else
194 c->irq_edge_fall &= ~mask;
195
196 update_edge_detect(c);
197
198 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
199 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
200 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
201 return 0;
202}
203
204static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
205{
206 struct pxa_gpio_chip *c;
207 int loop, gpio, gpio_base, n;
208 unsigned long gedr;
209
210 do {
211 loop = 0;
212 for_each_gpio_chip(gpio, c) {
213 gpio_base = c->chip.base;
214
215 gedr = __raw_readl(c->regbase + GEDR_OFFSET);
216 gedr = gedr & c->irq_mask;
217 __raw_writel(gedr, c->regbase + GEDR_OFFSET);
218
219 n = find_first_bit(&gedr, BITS_PER_LONG);
220 while (n < BITS_PER_LONG) {
221 loop = 1;
222
223 generic_handle_irq(gpio_to_irq(gpio_base + n));
224 n = find_next_bit(&gedr, BITS_PER_LONG, n + 1);
225 }
226 }
227 } while (loop);
228}
229
230static void pxa_ack_muxed_gpio(struct irq_data *d)
231{
232 int gpio = irq_to_gpio(d->irq);
233 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
234
235 __raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
236}
237
238static void pxa_mask_muxed_gpio(struct irq_data *d)
239{
240 int gpio = irq_to_gpio(d->irq);
241 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
242 uint32_t grer, gfer;
243
244 c->irq_mask &= ~GPIO_bit(gpio);
245
246 grer = __raw_readl(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
247 gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
248 __raw_writel(grer, c->regbase + GRER_OFFSET);
249 __raw_writel(gfer, c->regbase + GFER_OFFSET);
250}
251
252static void pxa_unmask_muxed_gpio(struct irq_data *d)
253{
254 int gpio = irq_to_gpio(d->irq);
255 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
256
257 c->irq_mask |= GPIO_bit(gpio);
258 update_edge_detect(c);
259}
260
261static struct irq_chip pxa_muxed_gpio_chip = {
262 .name = "GPIO",
263 .irq_ack = pxa_ack_muxed_gpio,
264 .irq_mask = pxa_mask_muxed_gpio,
265 .irq_unmask = pxa_unmask_muxed_gpio,
266 .irq_set_type = pxa_gpio_irq_type,
267};
268
269void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn)
270{
271 struct pxa_gpio_chip *c;
272 int gpio, irq;
273
274 pxa_last_gpio = end;
275
276 /* Initialize GPIO chips */
277 pxa_init_gpio_chip(end);
278
279 /* clear all GPIO edge detects */
280 for_each_gpio_chip(gpio, c) {
281 __raw_writel(0, c->regbase + GFER_OFFSET);
282 __raw_writel(0, c->regbase + GRER_OFFSET);
283 __raw_writel(~0,c->regbase + GEDR_OFFSET);
284 }
285
286 for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) {
287 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
288 handle_edge_irq);
289 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
290 }
291
292 /* Install handler for GPIO>=2 edge detect interrupts */
293 irq_set_chained_handler(mux_irq, pxa_gpio_demux_handler);
294 pxa_muxed_gpio_chip.irq_set_wake = fn;
295}
296
297#ifdef CONFIG_PM
298static int pxa_gpio_suspend(void)
299{
300 struct pxa_gpio_chip *c;
301 int gpio;
302
303 for_each_gpio_chip(gpio, c) {
304 c->saved_gplr = __raw_readl(c->regbase + GPLR_OFFSET);
305 c->saved_gpdr = __raw_readl(c->regbase + GPDR_OFFSET);
306 c->saved_grer = __raw_readl(c->regbase + GRER_OFFSET);
307 c->saved_gfer = __raw_readl(c->regbase + GFER_OFFSET);
308
309 /* Clear GPIO transition detect bits */
310 __raw_writel(0xffffffff, c->regbase + GEDR_OFFSET);
311 }
312 return 0;
313}
314
315static void pxa_gpio_resume(void)
316{
317 struct pxa_gpio_chip *c;
318 int gpio;
319
320 for_each_gpio_chip(gpio, c) {
321 /* restore level with set/clear */
322 __raw_writel( c->saved_gplr, c->regbase + GPSR_OFFSET);
323 __raw_writel(~c->saved_gplr, c->regbase + GPCR_OFFSET);
324
325 __raw_writel(c->saved_grer, c->regbase + GRER_OFFSET);
326 __raw_writel(c->saved_gfer, c->regbase + GFER_OFFSET);
327 __raw_writel(c->saved_gpdr, c->regbase + GPDR_OFFSET);
328 }
329}
330#else
331#define pxa_gpio_suspend NULL
332#define pxa_gpio_resume NULL
333#endif
334
335struct syscore_ops pxa_gpio_syscore_ops = {
336 .suspend = pxa_gpio_suspend,
337 .resume = pxa_gpio_resume,
338};
diff --git a/arch/arm/plat-pxa/include/plat/gpio-pxa.h b/arch/arm/plat-pxa/include/plat/gpio-pxa.h
new file mode 100644
index 000000000000..b6390beff323
--- /dev/null
+++ b/arch/arm/plat-pxa/include/plat/gpio-pxa.h
@@ -0,0 +1,44 @@
1#ifndef __PLAT_PXA_GPIO_H
2#define __PLAT_PXA_GPIO_H
3
4struct irq_data;
5
6/*
7 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
8 * one set of registers. The register offsets are organized below:
9 *
10 * GPLR GPDR GPSR GPCR GRER GFER GEDR
11 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
12 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
13 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
14 *
15 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
16 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
17 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
18 *
19 * NOTE:
20 * BANK 3 is only available on PXA27x and later processors.
21 * BANK 4 and 5 are only available on PXA935
22 */
23
24#define GPIO_BANK(n) (GPIO_REGS_VIRT + BANK_OFF(n))
25
26#define GPLR_OFFSET 0x00
27#define GPDR_OFFSET 0x0C
28#define GPSR_OFFSET 0x18
29#define GPCR_OFFSET 0x24
30#define GRER_OFFSET 0x30
31#define GFER_OFFSET 0x3C
32#define GEDR_OFFSET 0x48
33
34/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
35 * Those cases currently cause holes in the GPIO number space, the
36 * actual number of the last GPIO is recorded by 'pxa_last_gpio'.
37 */
38extern int pxa_last_gpio;
39
40typedef int (*set_wake_t)(struct irq_data *d, unsigned int on);
41
42extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn);
43
44#endif /* __PLAT_PXA_GPIO_H */
diff --git a/arch/arm/plat-pxa/include/plat/gpio.h b/arch/arm/plat-pxa/include/plat/gpio.h
index 1ddd2b97a729..258f77210b02 100644
--- a/arch/arm/plat-pxa/include/plat/gpio.h
+++ b/arch/arm/plat-pxa/include/plat/gpio.h
@@ -1,35 +1,10 @@
1#ifndef __PLAT_GPIO_H 1#ifndef __PLAT_GPIO_H
2#define __PLAT_GPIO_H 2#define __PLAT_GPIO_H
3 3
4struct irq_data; 4#define __ARM_GPIOLIB_COMPLEX
5 5
6/* 6/* The individual machine provides register offsets and NR_BUILTIN_GPIO */
7 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with 7#include <mach/gpio-pxa.h>
8 * one set of registers. The register offsets are organized below:
9 *
10 * GPLR GPDR GPSR GPCR GRER GFER GEDR
11 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
12 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
13 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
14 *
15 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
16 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
17 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
18 *
19 * NOTE:
20 * BANK 3 is only available on PXA27x and later processors.
21 * BANK 4 and 5 are only available on PXA935
22 */
23
24#define GPIO_BANK(n) (GPIO_REGS_VIRT + BANK_OFF(n))
25
26#define GPLR_OFFSET 0x00
27#define GPDR_OFFSET 0x0C
28#define GPSR_OFFSET 0x18
29#define GPCR_OFFSET 0x24
30#define GRER_OFFSET 0x30
31#define GFER_OFFSET 0x3C
32#define GEDR_OFFSET 0x48
33 8
34static inline int gpio_get_value(unsigned gpio) 9static inline int gpio_get_value(unsigned gpio)
35{ 10{
@@ -52,13 +27,4 @@ static inline void gpio_set_value(unsigned gpio, int value)
52 27
53#define gpio_cansleep __gpio_cansleep 28#define gpio_cansleep __gpio_cansleep
54 29
55/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
56 * Those cases currently cause holes in the GPIO number space, the
57 * actual number of the last GPIO is recorded by 'pxa_last_gpio'.
58 */
59extern int pxa_last_gpio;
60
61typedef int (*set_wake_t)(struct irq_data *d, unsigned int on);
62
63extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn);
64#endif /* __PLAT_GPIO_H */ 30#endif /* __PLAT_GPIO_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-22 19:33:03 -0500