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authorLinus Walleij <linus.walleij@linaro.org>2011-09-28 04:11:30 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-10-01 18:45:34 -0400
commitf55be1bf52aad524dc1bf556ae26c90262c87825 (patch)
treede61131bfac6985902a66ce0b29909ad0519acf9 /arch/arm/plat-pxa/include
parent354bf8010ffea1ca5accd9fae26b7373df96bcb7 (diff)
ARM: 7104/1: plat-pxa: break out GPIO driver specifics
The <mach/gpio.h> file is included from upper directories and deal with generic GPIO and gpiolib stuff. Break out the platform and driver specific defines and functions into its own header file. Cc: Eric Miao <eric.y.miao@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/plat-pxa/include')
-rw-r--r--arch/arm/plat-pxa/include/plat/gpio-pxa.h44
-rw-r--r--arch/arm/plat-pxa/include/plat/gpio.h40
2 files changed, 46 insertions, 38 deletions
diff --git a/arch/arm/plat-pxa/include/plat/gpio-pxa.h b/arch/arm/plat-pxa/include/plat/gpio-pxa.h
new file mode 100644
index 000000000000..b6390beff323
--- /dev/null
+++ b/arch/arm/plat-pxa/include/plat/gpio-pxa.h
@@ -0,0 +1,44 @@
1#ifndef __PLAT_PXA_GPIO_H
2#define __PLAT_PXA_GPIO_H
3
4struct irq_data;
5
6/*
7 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
8 * one set of registers. The register offsets are organized below:
9 *
10 * GPLR GPDR GPSR GPCR GRER GFER GEDR
11 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
12 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
13 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
14 *
15 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
16 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
17 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
18 *
19 * NOTE:
20 * BANK 3 is only available on PXA27x and later processors.
21 * BANK 4 and 5 are only available on PXA935
22 */
23
24#define GPIO_BANK(n) (GPIO_REGS_VIRT + BANK_OFF(n))
25
26#define GPLR_OFFSET 0x00
27#define GPDR_OFFSET 0x0C
28#define GPSR_OFFSET 0x18
29#define GPCR_OFFSET 0x24
30#define GRER_OFFSET 0x30
31#define GFER_OFFSET 0x3C
32#define GEDR_OFFSET 0x48
33
34/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
35 * Those cases currently cause holes in the GPIO number space, the
36 * actual number of the last GPIO is recorded by 'pxa_last_gpio'.
37 */
38extern int pxa_last_gpio;
39
40typedef int (*set_wake_t)(struct irq_data *d, unsigned int on);
41
42extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn);
43
44#endif /* __PLAT_PXA_GPIO_H */
diff --git a/arch/arm/plat-pxa/include/plat/gpio.h b/arch/arm/plat-pxa/include/plat/gpio.h
index 6fc41db93e1c..258f77210b02 100644
--- a/arch/arm/plat-pxa/include/plat/gpio.h
+++ b/arch/arm/plat-pxa/include/plat/gpio.h
@@ -3,35 +3,8 @@
3 3
4#define __ARM_GPIOLIB_COMPLEX 4#define __ARM_GPIOLIB_COMPLEX
5 5
6struct irq_data; 6/* The individual machine provides register offsets and NR_BUILTIN_GPIO */
7 7#include <mach/gpio-pxa.h>
8/*
9 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
10 * one set of registers. The register offsets are organized below:
11 *
12 * GPLR GPDR GPSR GPCR GRER GFER GEDR
13 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
14 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
15 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
16 *
17 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
18 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
19 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
20 *
21 * NOTE:
22 * BANK 3 is only available on PXA27x and later processors.
23 * BANK 4 and 5 are only available on PXA935
24 */
25
26#define GPIO_BANK(n) (GPIO_REGS_VIRT + BANK_OFF(n))
27
28#define GPLR_OFFSET 0x00
29#define GPDR_OFFSET 0x0C
30#define GPSR_OFFSET 0x18
31#define GPCR_OFFSET 0x24
32#define GRER_OFFSET 0x30
33#define GFER_OFFSET 0x3C
34#define GEDR_OFFSET 0x48
35 8
36static inline int gpio_get_value(unsigned gpio) 9static inline int gpio_get_value(unsigned gpio)
37{ 10{
@@ -54,13 +27,4 @@ static inline void gpio_set_value(unsigned gpio, int value)
54 27
55#define gpio_cansleep __gpio_cansleep 28#define gpio_cansleep __gpio_cansleep
56 29
57/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
58 * Those cases currently cause holes in the GPIO number space, the
59 * actual number of the last GPIO is recorded by 'pxa_last_gpio'.
60 */
61extern int pxa_last_gpio;
62
63typedef int (*set_wake_t)(struct irq_data *d, unsigned int on);
64
65extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn);
66#endif /* __PLAT_GPIO_H */ 30#endif /* __PLAT_GPIO_H */