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authorLennert Buytenhek <buytenh@wantstofly.org>2008-10-19 19:51:03 -0400
committerNicolas Pitre <nico@cam.org>2008-12-20 12:24:05 -0500
commit07332318f33da6acd88abb762a8b6febdfc560a3 (patch)
tree911c34bb215427f1f8771a52e7c3d4433397ab83 /arch/arm/plat-orion
parent9569dae75f6f6987e79fa26cf6da3fc24006c996 (diff)
[ARM] Orion: share GPIO IRQ handling code
Split off Orion GPIO IRQ handling code into plat-orion/. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm/plat-orion')
-rw-r--r--arch/arm/plat-orion/gpio.c176
-rw-r--r--arch/arm/plat-orion/include/plat/gpio.h7
2 files changed, 183 insertions, 0 deletions
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index d86fc085e489..967186425ca1 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -10,6 +10,7 @@
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/irq.h>
13#include <linux/module.h> 14#include <linux/module.h>
14#include <linux/spinlock.h> 15#include <linux/spinlock.h>
15#include <linux/bitops.h> 16#include <linux/bitops.h>
@@ -237,3 +238,178 @@ void orion_gpio_set_blink(unsigned pin, int blink)
237 spin_unlock_irqrestore(&gpio_lock, flags); 238 spin_unlock_irqrestore(&gpio_lock, flags);
238} 239}
239EXPORT_SYMBOL(orion_gpio_set_blink); 240EXPORT_SYMBOL(orion_gpio_set_blink);
241
242
243/*****************************************************************************
244 * Orion GPIO IRQ
245 *
246 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
247 * value of the line or the opposite value.
248 *
249 * Level IRQ handlers: DATA_IN is used directly as cause register.
250 * Interrupt are masked by LEVEL_MASK registers.
251 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
252 * Interrupt are masked by EDGE_MASK registers.
253 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
254 * the polarity to catch the next line transaction.
255 * This is a race condition that might not perfectly
256 * work on some use cases.
257 *
258 * Every eight GPIO lines are grouped (OR'ed) before going up to main
259 * cause register.
260 *
261 * EDGE cause mask
262 * data-in /--------| |-----| |----\
263 * -----| |----- ---- to main cause reg
264 * X \----------------| |----/
265 * polarity LEVEL mask
266 *
267 ****************************************************************************/
268static void gpio_irq_edge_ack(u32 irq)
269{
270 int pin = irq_to_gpio(irq);
271
272 writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin));
273}
274
275static void gpio_irq_edge_mask(u32 irq)
276{
277 int pin = irq_to_gpio(irq);
278 u32 u;
279
280 u = readl(GPIO_EDGE_MASK(pin));
281 u &= ~(1 << (pin & 31));
282 writel(u, GPIO_EDGE_MASK(pin));
283}
284
285static void gpio_irq_edge_unmask(u32 irq)
286{
287 int pin = irq_to_gpio(irq);
288 u32 u;
289
290 u = readl(GPIO_EDGE_MASK(pin));
291 u |= 1 << (pin & 31);
292 writel(u, GPIO_EDGE_MASK(pin));
293}
294
295static void gpio_irq_level_mask(u32 irq)
296{
297 int pin = irq_to_gpio(irq);
298 u32 u;
299
300 u = readl(GPIO_LEVEL_MASK(pin));
301 u &= ~(1 << (pin & 31));
302 writel(u, GPIO_LEVEL_MASK(pin));
303}
304
305static void gpio_irq_level_unmask(u32 irq)
306{
307 int pin = irq_to_gpio(irq);
308 u32 u;
309
310 u = readl(GPIO_LEVEL_MASK(pin));
311 u |= 1 << (pin & 31);
312 writel(u, GPIO_LEVEL_MASK(pin));
313}
314
315static int gpio_irq_set_type(u32 irq, u32 type)
316{
317 int pin = irq_to_gpio(irq);
318 struct irq_desc *desc;
319 u32 u;
320
321 u = readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31));
322 if (!u) {
323 printk(KERN_ERR "orion gpio_irq_set_type failed "
324 "(irq %d, pin %d).\n", irq, pin);
325 return -EINVAL;
326 }
327
328 desc = irq_desc + irq;
329
330 /*
331 * Set edge/level type.
332 */
333 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
334 desc->chip = &orion_gpio_irq_edge_chip;
335 } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
336 desc->chip = &orion_gpio_irq_level_chip;
337 } else {
338 printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
339 return -EINVAL;
340 }
341
342 /*
343 * Configure interrupt polarity.
344 */
345 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
346 u = readl(GPIO_IN_POL(pin));
347 u &= ~(1 << (pin & 31));
348 writel(u, GPIO_IN_POL(pin));
349 } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
350 u = readl(GPIO_IN_POL(pin));
351 u |= 1 << (pin & 31);
352 writel(u, GPIO_IN_POL(pin));
353 } else if (type == IRQ_TYPE_EDGE_BOTH) {
354 u32 v;
355
356 v = readl(GPIO_IN_POL(pin)) ^ readl(GPIO_DATA_IN(pin));
357
358 /*
359 * set initial polarity based on current input level
360 */
361 u = readl(GPIO_IN_POL(pin));
362 if (v & (1 << (pin & 31)))
363 u |= 1 << (pin & 31); /* falling */
364 else
365 u &= ~(1 << (pin & 31)); /* rising */
366 writel(u, GPIO_IN_POL(pin));
367 }
368
369 desc->status = (desc->status & ~IRQ_TYPE_SENSE_MASK) | type;
370
371 return 0;
372}
373
374struct irq_chip orion_gpio_irq_edge_chip = {
375 .name = "orion_gpio_irq_edge",
376 .ack = gpio_irq_edge_ack,
377 .mask = gpio_irq_edge_mask,
378 .unmask = gpio_irq_edge_unmask,
379 .set_type = gpio_irq_set_type,
380};
381
382struct irq_chip orion_gpio_irq_level_chip = {
383 .name = "orion_gpio_irq_level",
384 .mask = gpio_irq_level_mask,
385 .mask_ack = gpio_irq_level_mask,
386 .unmask = gpio_irq_level_unmask,
387 .set_type = gpio_irq_set_type,
388};
389
390void orion_gpio_irq_handler(int pinoff)
391{
392 u32 cause;
393 int pin;
394
395 cause = readl(GPIO_DATA_IN(pinoff)) & readl(GPIO_LEVEL_MASK(pinoff));
396 cause |= readl(GPIO_EDGE_CAUSE(pinoff)) & readl(GPIO_EDGE_MASK(pinoff));
397
398 for (pin = pinoff; pin < pinoff + 8; pin++) {
399 int irq = gpio_to_irq(pin);
400 struct irq_desc *desc = irq_desc + irq;
401
402 if (!(cause & (1 << (pin & 31))))
403 continue;
404
405 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
406 /* Swap polarity (race with GPIO line) */
407 u32 polarity;
408
409 polarity = readl(GPIO_IN_POL(pin));
410 polarity ^= 1 << (pin & 31);
411 writel(polarity, GPIO_IN_POL(pin));
412 }
413 desc_handle_irq(irq, desc);
414 }
415}
diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h
index 956658df269f..54deaf274b52 100644
--- a/arch/arm/plat-orion/include/plat/gpio.h
+++ b/arch/arm/plat-orion/include/plat/gpio.h
@@ -28,5 +28,12 @@ void orion_gpio_set_unused(unsigned pin);
28void orion_gpio_set_valid(unsigned pin, int valid); 28void orion_gpio_set_valid(unsigned pin, int valid);
29void orion_gpio_set_blink(unsigned pin, int blink); 29void orion_gpio_set_blink(unsigned pin, int blink);
30 30
31/*
32 * GPIO interrupt handling.
33 */
34extern struct irq_chip orion_gpio_irq_edge_chip;
35extern struct irq_chip orion_gpio_irq_level_chip;
36void orion_gpio_irq_handler(int irqoff);
37
31 38
32#endif 39#endif