diff options
author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2013-03-06 11:59:57 -0500 |
---|---|---|
committer | Jason Cooper <jason@lakedaemon.net> | 2013-03-17 14:03:44 -0400 |
commit | 59f16137b2a09b2fba7e4d00088f99ce0ea9a6de (patch) | |
tree | eba5e1a91fbd602f143c5cf4c6ef678edd2e1936 /arch/arm/plat-orion | |
parent | efaaa98d306d5bc52d4856c3758d44585d6abcc1 (diff) |
arm: plat-orion: use mv_mbus_dram_info() in PCIe code
The PCIe code was directly accessing the orion_mbus_dram_info
structure to get access to a description of the SDRAM chip selects in
order to configure the PCIe -> SDRAM address decoding
windows.
However, with the introduction of the orion-mbus driver, we are going
to remove this global structure and instead leave only the exported
mv_mbus_dram_info() function to access this description of the SDRAM
chip selects. Therefore, we simply switch to using this API.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/plat-orion')
-rw-r--r-- | arch/arm/plat-orion/pcie.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c index f20a321088a2..8b8c06d2e9c4 100644 --- a/arch/arm/plat-orion/pcie.c +++ b/arch/arm/plat-orion/pcie.c | |||
@@ -120,12 +120,14 @@ void __init orion_pcie_reset(void __iomem *base) | |||
120 | * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks | 120 | * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks |
121 | * WIN[0-3] -> DRAM bank[0-3] | 121 | * WIN[0-3] -> DRAM bank[0-3] |
122 | */ | 122 | */ |
123 | static void __init orion_pcie_setup_wins(void __iomem *base, | 123 | static void __init orion_pcie_setup_wins(void __iomem *base) |
124 | struct mbus_dram_target_info *dram) | ||
125 | { | 124 | { |
125 | const struct mbus_dram_target_info *dram; | ||
126 | u32 size; | 126 | u32 size; |
127 | int i; | 127 | int i; |
128 | 128 | ||
129 | dram = mv_mbus_dram_info(); | ||
130 | |||
129 | /* | 131 | /* |
130 | * First, disable and clear BARs and windows. | 132 | * First, disable and clear BARs and windows. |
131 | */ | 133 | */ |
@@ -150,7 +152,7 @@ static void __init orion_pcie_setup_wins(void __iomem *base, | |||
150 | */ | 152 | */ |
151 | size = 0; | 153 | size = 0; |
152 | for (i = 0; i < dram->num_cs; i++) { | 154 | for (i = 0; i < dram->num_cs; i++) { |
153 | struct mbus_dram_window *cs = dram->cs + i; | 155 | const struct mbus_dram_window *cs = dram->cs + i; |
154 | 156 | ||
155 | writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); | 157 | writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); |
156 | writel(0, base + PCIE_WIN04_REMAP_OFF(i)); | 158 | writel(0, base + PCIE_WIN04_REMAP_OFF(i)); |
@@ -184,7 +186,7 @@ void __init orion_pcie_setup(void __iomem *base) | |||
184 | /* | 186 | /* |
185 | * Point PCIe unit MBUS decode windows to DRAM space. | 187 | * Point PCIe unit MBUS decode windows to DRAM space. |
186 | */ | 188 | */ |
187 | orion_pcie_setup_wins(base, &orion_mbus_dram_info); | 189 | orion_pcie_setup_wins(base); |
188 | 190 | ||
189 | /* | 191 | /* |
190 | * Master + slave enable. | 192 | * Master + slave enable. |