[ARM] 5401/1: Orion: fix edge triggered GPIO interrupt support

The GPIO interrupts can be configured as either level triggered or edge
triggered, with a default of level triggered.  When an edge triggered
interrupt is requested, the gpio_irq_set_type method is called which
currently switches the given IRQ descriptor between two struct irq_chip
instances: orion_gpio_irq_level_chip and orion_gpio_irq_edge_chip. This
happens via __setup_irq() which also calls irq_chip_set_defaults() to
assign default methods to uninitialized ones.  The problem is that
irq_chip_set_defaults() is called before the irq_chip reference is
switched, leaving the new irq_chip (orion_gpio_irq_edge_chip in this
case) with uninitialized methods such as chip->startup() causing a kernel
oops.

Many solutions are possible, such as making irq_chip_set_defaults() global
and calling it from gpio_irq_set_type(), or calling __irq_set_trigger()
before irq_chip_set_defaults() in __setup_irq().  But those require
modifications to the generic IRQ code which might have adverse effect on
other architectures, and that would still be a fragile arrangement.
Manually copying the missing methods from within gpio_irq_set_type()
would be really ugly and it would break again the day new methods with
automatic defaults are added.

A better solution is to have a single irq_chip instance which can deal
with both edge and level triggered interrupts.  It is also a good idea
to switch the IRQ handler instead, as the edge IRQ handler allows for
one edge IRQ event to be queued as the IRQ is actually masked only when
that second IRQ is received, at which point the hardware can queue an
additional IRQ event, making edge triggered interrupts a bit more
reliable.

Tested-by: Martin Michlmayr <tbm@cyrius.com>

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 25 insertions, 48 deletions

diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index 967186425ca1..0d12c2164766 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -265,51 +265,36 @@ EXPORT_SYMBOL(orion_gpio_set_blink);
  *        polarity    LEVEL          mask
  *
  ****************************************************************************/
-static void gpio_irq_edge_ack(u32 irq)
-{
-        int pin = irq_to_gpio(irq);
-
-        writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin));
-}
-
-static void gpio_irq_edge_mask(u32 irq)
-{
-        int pin = irq_to_gpio(irq);
-        u32 u;
-
-        u = readl(GPIO_EDGE_MASK(pin));
-        u &= ~(1 << (pin & 31));
-        writel(u, GPIO_EDGE_MASK(pin));
-}
 
-static void gpio_irq_edge_unmask(u32 irq)
+static void gpio_irq_ack(u32 irq)
 {
-        int pin = irq_to_gpio(irq);
-        u32 u;
-
-        u = readl(GPIO_EDGE_MASK(pin));
-        u |= 1 << (pin & 31);
-        writel(u, GPIO_EDGE_MASK(pin));
+        int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
+        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
+                int pin = irq_to_gpio(irq);
+                writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin));
+        }
 }
 
-static void gpio_irq_level_mask(u32 irq)
+static void gpio_irq_mask(u32 irq)
 {
         int pin = irq_to_gpio(irq);
-        u32 u;
-
-        u = readl(GPIO_LEVEL_MASK(pin));
+        int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
+        u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
+                GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
+        u32 u = readl(reg);
         u &= ~(1 << (pin & 31));
-        writel(u, GPIO_LEVEL_MASK(pin));
+        writel(u, reg);
 }
 
-static void gpio_irq_level_unmask(u32 irq)
+static void gpio_irq_unmask(u32 irq)
 {
         int pin = irq_to_gpio(irq);
-        u32 u;
-
-        u = readl(GPIO_LEVEL_MASK(pin));
+        int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
+        u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
+                GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
+        u32 u = readl(reg);
         u |= 1 << (pin & 31);
-        writel(u, GPIO_LEVEL_MASK(pin));
+        writel(u, reg);
 }
 
 static int gpio_irq_set_type(u32 irq, u32 type)
@@ -331,9 +316,9 @@ static int gpio_irq_set_type(u32 irq, u32 type)
          * Set edge/level type.
          */
         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
-                desc->chip = &orion_gpio_irq_edge_chip;
+                desc->handle_irq = handle_edge_irq;
         } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
-                desc->chip = &orion_gpio_irq_level_chip;
+                desc->handle_irq = handle_level_irq;
         } else {
                 printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
                 return -EINVAL;
@@ -371,19 +356,11 @@ static int gpio_irq_set_type(u32 irq, u32 type)
         return 0;
 }
 
-struct irq_chip orion_gpio_irq_edge_chip = {
-        .name           = "orion_gpio_irq_edge",
-        .ack            = gpio_irq_edge_ack,
-        .mask           = gpio_irq_edge_mask,
-        .unmask         = gpio_irq_edge_unmask,
-        .set_type       = gpio_irq_set_type,
-};
-
-struct irq_chip orion_gpio_irq_level_chip = {
-        .name           = "orion_gpio_irq_level",
-        .mask           = gpio_irq_level_mask,
-        .mask_ack       = gpio_irq_level_mask,
-        .unmask         = gpio_irq_level_unmask,
+struct irq_chip orion_gpio_irq_chip = {
+        .name           = "orion_gpio",
+        .ack            = gpio_irq_ack,
+        .mask           = gpio_irq_mask,
+        .unmask         = gpio_irq_unmask,
         .set_type       = gpio_irq_set_type,
 };