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authorTony Lindgren <tony@atomide.com>2010-02-12 15:26:46 -0500
committerTony Lindgren <tony@atomide.com>2010-02-15 12:26:56 -0500
commit882c0518e5317a41834d0fceee07ae6ada2d7429 (patch)
treea0fa29b25af62fd142bba80bd39618792a48fa00 /arch/arm/plat-omap
parent56213ca4e440c0b6e56a48f5901c55c4ce3cf1ba (diff)
omap: Fix dmtimer.c for multi-omap boot
Fix dmtimer.c for multi-omap boot. Also remove legacy clk_enable/disable wrappers that are no longer needed. Note that the clock handling should be further improved to make use of the clock aliases. Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r--arch/arm/plat-omap/dmtimer.c90
1 files changed, 39 insertions, 51 deletions
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 08ccf8922520..c588cdf35db1 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -163,20 +163,9 @@ struct omap_dm_timer {
163 unsigned posted:1; 163 unsigned posted:1;
164}; 164};
165 165
166#ifdef CONFIG_ARCH_OMAP1 166static int dm_timer_count;
167
168#define omap_dm_clk_enable(x)
169#define omap_dm_clk_disable(x)
170#define omap2_dm_timers NULL
171#define omap2_dm_source_names NULL
172#define omap2_dm_source_clocks NULL
173#define omap3_dm_timers NULL
174#define omap3_dm_source_names NULL
175#define omap3_dm_source_clocks NULL
176#define omap4_dm_timers NULL
177#define omap4_dm_source_names NULL
178#define omap4_dm_source_clocks NULL
179 167
168#ifdef CONFIG_ARCH_OMAP1
180static struct omap_dm_timer omap1_dm_timers[] = { 169static struct omap_dm_timer omap1_dm_timers[] = {
181 { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 }, 170 { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
182 { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 }, 171 { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
@@ -188,20 +177,14 @@ static struct omap_dm_timer omap1_dm_timers[] = {
188 { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 }, 177 { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 },
189}; 178};
190 179
191static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers); 180static const int omap1_dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
192
193#elif defined(CONFIG_ARCH_OMAP2)
194 181
195#define omap_dm_clk_enable(x) clk_enable(x) 182#else
196#define omap_dm_clk_disable(x) clk_disable(x)
197#define omap1_dm_timers NULL 183#define omap1_dm_timers NULL
198#define omap3_dm_timers NULL 184#define omap1_dm_timer_count 0
199#define omap3_dm_source_names NULL 185#endif /* CONFIG_ARCH_OMAP1 */
200#define omap3_dm_source_clocks NULL
201#define omap4_dm_timers NULL
202#define omap4_dm_source_names NULL
203#define omap4_dm_source_clocks NULL
204 186
187#ifdef CONFIG_ARCH_OMAP2
205static struct omap_dm_timer omap2_dm_timers[] = { 188static struct omap_dm_timer omap2_dm_timers[] = {
206 { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 }, 189 { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
207 { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 }, 190 { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
@@ -225,20 +208,16 @@ static const char *omap2_dm_source_names[] __initdata = {
225}; 208};
226 209
227static struct clk *omap2_dm_source_clocks[3]; 210static struct clk *omap2_dm_source_clocks[3];
228static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers); 211static const int omap2_dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
229
230#elif defined(CONFIG_ARCH_OMAP3)
231 212
232#define omap_dm_clk_enable(x) clk_enable(x) 213#else
233#define omap_dm_clk_disable(x) clk_disable(x)
234#define omap1_dm_timers NULL
235#define omap2_dm_timers NULL 214#define omap2_dm_timers NULL
215#define omap2_dm_timer_count 0
236#define omap2_dm_source_names NULL 216#define omap2_dm_source_names NULL
237#define omap2_dm_source_clocks NULL 217#define omap2_dm_source_clocks NULL
238#define omap4_dm_timers NULL 218#endif /* CONFIG_ARCH_OMAP2 */
239#define omap4_dm_source_names NULL
240#define omap4_dm_source_clocks NULL
241 219
220#ifdef CONFIG_ARCH_OMAP3
242static struct omap_dm_timer omap3_dm_timers[] = { 221static struct omap_dm_timer omap3_dm_timers[] = {
243 { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 }, 222 { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 },
244 { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 }, 223 { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 },
@@ -261,20 +240,16 @@ static const char *omap3_dm_source_names[] __initdata = {
261}; 240};
262 241
263static struct clk *omap3_dm_source_clocks[2]; 242static struct clk *omap3_dm_source_clocks[2];
264static const int dm_timer_count = ARRAY_SIZE(omap3_dm_timers); 243static const int omap3_dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
265
266#elif defined(CONFIG_ARCH_OMAP4)
267 244
268#define omap_dm_clk_enable(x) clk_enable(x) 245#else
269#define omap_dm_clk_disable(x) clk_disable(x)
270#define omap1_dm_timers NULL
271#define omap2_dm_timers NULL
272#define omap2_dm_source_names NULL
273#define omap2_dm_source_clocks NULL
274#define omap3_dm_timers NULL 246#define omap3_dm_timers NULL
247#define omap3_dm_timer_count 0
275#define omap3_dm_source_names NULL 248#define omap3_dm_source_names NULL
276#define omap3_dm_source_clocks NULL 249#define omap3_dm_source_clocks NULL
250#endif /* CONFIG_ARCH_OMAP3 */
277 251
252#ifdef CONFIG_ARCH_OMAP4
278static struct omap_dm_timer omap4_dm_timers[] = { 253static struct omap_dm_timer omap4_dm_timers[] = {
279 { .phys_base = 0x4a318000, .irq = INT_44XX_GPTIMER1 }, 254 { .phys_base = 0x4a318000, .irq = INT_44XX_GPTIMER1 },
280 { .phys_base = 0x48032000, .irq = INT_44XX_GPTIMER2 }, 255 { .phys_base = 0x48032000, .irq = INT_44XX_GPTIMER2 },
@@ -295,13 +270,14 @@ static const char *omap4_dm_source_names[] __initdata = {
295 NULL 270 NULL
296}; 271};
297static struct clk *omap4_dm_source_clocks[2]; 272static struct clk *omap4_dm_source_clocks[2];
298static const int dm_timer_count = ARRAY_SIZE(omap4_dm_timers); 273static const int omap4_dm_timer_count = ARRAY_SIZE(omap4_dm_timers);
299 274
300#else 275#else
301 276#define omap4_dm_timers NULL
302#error OMAP architecture not supported! 277#define omap4_dm_timer_count 0
303 278#define omap4_dm_source_names NULL
304#endif 279#define omap4_dm_source_clocks NULL
280#endif /* CONFIG_ARCH_OMAP4 */
305 281
306static struct omap_dm_timer *dm_timers; 282static struct omap_dm_timer *dm_timers;
307static const char **dm_source_names; 283static const char **dm_source_names;
@@ -450,8 +426,12 @@ void omap_dm_timer_enable(struct omap_dm_timer *timer)
450 if (timer->enabled) 426 if (timer->enabled)
451 return; 427 return;
452 428
453 omap_dm_clk_enable(timer->fclk); 429#ifdef CONFIG_ARCH_OMAP2PLUS
454 omap_dm_clk_enable(timer->iclk); 430 if (cpu_class_is_omap2()) {
431 clk_enable(timer->fclk);
432 clk_enable(timer->iclk);
433 }
434#endif
455 435
456 timer->enabled = 1; 436 timer->enabled = 1;
457} 437}
@@ -462,8 +442,12 @@ void omap_dm_timer_disable(struct omap_dm_timer *timer)
462 if (!timer->enabled) 442 if (!timer->enabled)
463 return; 443 return;
464 444
465 omap_dm_clk_disable(timer->iclk); 445#ifdef CONFIG_ARCH_OMAP2PLUS
466 omap_dm_clk_disable(timer->fclk); 446 if (cpu_class_is_omap2()) {
447 clk_disable(timer->iclk);
448 clk_disable(timer->fclk);
449 }
450#endif
467 451
468 timer->enabled = 0; 452 timer->enabled = 0;
469} 453}
@@ -764,17 +748,21 @@ int __init omap_dm_timer_init(void)
764 748
765 if (cpu_class_is_omap1()) { 749 if (cpu_class_is_omap1()) {
766 dm_timers = omap1_dm_timers; 750 dm_timers = omap1_dm_timers;
751 dm_timer_count = omap1_dm_timer_count;
767 map_size = SZ_2K; 752 map_size = SZ_2K;
768 } else if (cpu_is_omap24xx()) { 753 } else if (cpu_is_omap24xx()) {
769 dm_timers = omap2_dm_timers; 754 dm_timers = omap2_dm_timers;
755 dm_timer_count = omap2_dm_timer_count;
770 dm_source_names = omap2_dm_source_names; 756 dm_source_names = omap2_dm_source_names;
771 dm_source_clocks = omap2_dm_source_clocks; 757 dm_source_clocks = omap2_dm_source_clocks;
772 } else if (cpu_is_omap34xx()) { 758 } else if (cpu_is_omap34xx()) {
773 dm_timers = omap3_dm_timers; 759 dm_timers = omap3_dm_timers;
760 dm_timer_count = omap3_dm_timer_count;
774 dm_source_names = omap3_dm_source_names; 761 dm_source_names = omap3_dm_source_names;
775 dm_source_clocks = omap3_dm_source_clocks; 762 dm_source_clocks = omap3_dm_source_clocks;
776 } else if (cpu_is_omap44xx()) { 763 } else if (cpu_is_omap44xx()) {
777 dm_timers = omap4_dm_timers; 764 dm_timers = omap4_dm_timers;
765 dm_timer_count = omap4_dm_timer_count;
778 dm_source_names = omap4_dm_source_names; 766 dm_source_names = omap4_dm_source_names;
779 dm_source_clocks = omap4_dm_source_clocks; 767 dm_source_clocks = omap4_dm_source_clocks;
780 } 768 }