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authorSantosh Shilimkar <santosh.shilimkar@ti.com>2009-03-23 21:07:49 -0400
committerTony Lindgren <tony@atomide.com>2009-03-23 21:51:20 -0400
commit52176e70837d56cd238d6edc04cc403f1ffa86c6 (patch)
tree2904080fdc840989a0cea9c9dff340398b6e24cb /arch/arm/plat-omap
parent2263f0222e836c7b2c144e0546a2701661e2f517 (diff)
ARM: OMAP: Dispatch only relevant DMA interrupts
This fixes the spurious interrupt issue on a DMA channel. In OMAP sDMA, contrast to the SDMA.DMA4_CSRi registers, the SDMA.DMA4_IRQSTATUS_Lj registers are updated regardless of the corresponding bits in the SDMA.DMA4_IRQENABLE_Lj registers. Since there are four sDMA interrupt lines and if more than one line is actively used by two concurrently running sDMA softwares modules,then the spurious interrupt can be observed on the other lines. Fix in this patch will only dispatch the relevant and enabled interrupts on a particular line thus perevting spurious IRQ. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Nishant Kamat <nskamat@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r--arch/arm/plat-omap/dma.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index b1d3c7991ffd..21cc0142b97a 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1901,7 +1901,7 @@ static int omap2_dma_handle_ch(int ch)
1901/* STATUS register count is from 1-32 while our is 0-31 */ 1901/* STATUS register count is from 1-32 while our is 0-31 */
1902static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) 1902static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1903{ 1903{
1904 u32 val; 1904 u32 val, enable_reg;
1905 int i; 1905 int i;
1906 1906
1907 val = dma_read(IRQSTATUS_L0); 1907 val = dma_read(IRQSTATUS_L0);
@@ -1910,6 +1910,8 @@ static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1910 printk(KERN_WARNING "Spurious DMA IRQ\n"); 1910 printk(KERN_WARNING "Spurious DMA IRQ\n");
1911 return IRQ_HANDLED; 1911 return IRQ_HANDLED;
1912 } 1912 }
1913 enable_reg = dma_read(IRQENABLE_L0);
1914 val &= enable_reg; /* Dispatch only relevant interrupts */
1913 for (i = 0; i < dma_lch_count && val != 0; i++) { 1915 for (i = 0; i < dma_lch_count && val != 0; i++) {
1914 if (val & 1) 1916 if (val & 1)
1915 omap2_dma_handle_ch(i); 1917 omap2_dma_handle_ch(i);