diff options
author | Kevin Hilman <khilman@mvista.com> | 2007-11-13 02:24:02 -0500 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2008-04-14 12:57:12 -0400 |
commit | 5a3a388fbefac3705dfcde16c93fc81e6fd9378f (patch) | |
tree | cb32a3a40650dfa2ae72b0aefffef30b3d566ec0 /arch/arm/plat-omap | |
parent | 225dfda1d676b70acf1e696ace68c23297926ce0 (diff) |
ARM: OMAP: Timer32K: Re-organize duplicated 32k-timer code
On OMAP2/3, the gp-timer code can be used for a 32kHz timer simply by
setting the source to be the 32k clock instead of sys_clk.
This patch uses the mach-omap2/timer-gp.c code for 32kHz timer on
OMAP2, moving the logic into mach-omap2/timer-gp.c, and not using
plat-omap/timer32k.c which, for OMAP2, is redundant with the timer-gp
code.
Also, if CONFIG_OMAP_32K_TIMER is enabled, the gptimer-based
clocksource is not used. Instead the default 32k sync counter is used
as the clocksource (see the clocksource in plat-omap/common.c.) This
is important for sleep/suspend so there is a valid counter during
sleep. Note that the suspend/sleep code needs fixing to check for
overflows of this counter.
In addition, the OMAP2/3 details are removed from timer32k.c leaving
that with only OMAP1 specifics. A follow-up patch will move it from
plat-omap common code to mach-omap1.
Signed-off-by: Kevin Hilman <khilman@mvista.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r-- | arch/arm/plat-omap/Makefile | 2 | ||||
-rw-r--r-- | arch/arm/plat-omap/timer32k.c | 44 |
2 files changed, 3 insertions, 43 deletions
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index 8f56c255d1ee..d91424edf576 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile | |||
@@ -9,7 +9,9 @@ obj-m := | |||
9 | obj-n := | 9 | obj-n := |
10 | obj- := | 10 | obj- := |
11 | 11 | ||
12 | ifeq ($(CONFIG_ARCH_OMAP1),y) | ||
12 | obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o | 13 | obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o |
14 | endif | ||
13 | 15 | ||
14 | # OCPI interconnect support for 1710, 1610 and 5912 | 16 | # OCPI interconnect support for 1710, 1610 and 5912 |
15 | obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o | 17 | obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o |
diff --git a/arch/arm/plat-omap/timer32k.c b/arch/arm/plat-omap/timer32k.c index ea76f1979a3d..ce034dc59d41 100644 --- a/arch/arm/plat-omap/timer32k.c +++ b/arch/arm/plat-omap/timer32k.c | |||
@@ -40,6 +40,7 @@ | |||
40 | #include <linux/interrupt.h> | 40 | #include <linux/interrupt.h> |
41 | #include <linux/sched.h> | 41 | #include <linux/sched.h> |
42 | #include <linux/spinlock.h> | 42 | #include <linux/spinlock.h> |
43 | |||
43 | #include <linux/err.h> | 44 | #include <linux/err.h> |
44 | #include <linux/clk.h> | 45 | #include <linux/clk.h> |
45 | #include <linux/clocksource.h> | 46 | #include <linux/clocksource.h> |
@@ -93,8 +94,6 @@ struct sys_timer omap_timer; | |||
93 | #define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \ | 94 | #define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \ |
94 | (((nr_jiffies) * (clock_rate)) / HZ) | 95 | (((nr_jiffies) * (clock_rate)) / HZ) |
95 | 96 | ||
96 | #if defined(CONFIG_ARCH_OMAP1) | ||
97 | |||
98 | static inline void omap_32k_timer_write(int val, int reg) | 97 | static inline void omap_32k_timer_write(int val, int reg) |
99 | { | 98 | { |
100 | omap_writew(val, OMAP1_32K_TIMER_BASE + reg); | 99 | omap_writew(val, OMAP1_32K_TIMER_BASE + reg); |
@@ -120,30 +119,6 @@ static inline void omap_32k_timer_stop(void) | |||
120 | 119 | ||
121 | #define omap_32k_timer_ack_irq() | 120 | #define omap_32k_timer_ack_irq() |
122 | 121 | ||
123 | #elif defined(CONFIG_ARCH_OMAP2) | ||
124 | |||
125 | static struct omap_dm_timer *gptimer; | ||
126 | |||
127 | static inline void omap_32k_timer_start(unsigned long load_val) | ||
128 | { | ||
129 | omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val); | ||
130 | omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW); | ||
131 | omap_dm_timer_start(gptimer); | ||
132 | } | ||
133 | |||
134 | static inline void omap_32k_timer_stop(void) | ||
135 | { | ||
136 | omap_dm_timer_stop(gptimer); | ||
137 | } | ||
138 | |||
139 | static inline void omap_32k_timer_ack_irq(void) | ||
140 | { | ||
141 | u32 status = omap_dm_timer_read_status(gptimer); | ||
142 | omap_dm_timer_write_status(gptimer, status); | ||
143 | } | ||
144 | |||
145 | #endif | ||
146 | |||
147 | static void omap_32k_timer_set_mode(enum clock_event_mode mode, | 122 | static void omap_32k_timer_set_mode(enum clock_event_mode mode, |
148 | struct clock_event_device *evt) | 123 | struct clock_event_device *evt) |
149 | { | 124 | { |
@@ -222,23 +197,6 @@ static struct irqaction omap_32k_timer_irq = { | |||
222 | 197 | ||
223 | static __init void omap_init_32k_timer(void) | 198 | static __init void omap_init_32k_timer(void) |
224 | { | 199 | { |
225 | if (cpu_class_is_omap1()) | ||
226 | setup_irq(INT_OS_TIMER, &omap_32k_timer_irq); | ||
227 | |||
228 | #ifdef CONFIG_ARCH_OMAP2 | ||
229 | /* REVISIT: Check 24xx TIOCP_CFG settings after idle works */ | ||
230 | if (cpu_is_omap24xx()) { | ||
231 | gptimer = omap_dm_timer_request_specific(1); | ||
232 | BUG_ON(gptimer == NULL); | ||
233 | |||
234 | omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ); | ||
235 | setup_irq(omap_dm_timer_get_irq(gptimer), &omap_32k_timer_irq); | ||
236 | omap_dm_timer_set_int_enable(gptimer, | ||
237 | OMAP_TIMER_INT_CAPTURE | OMAP_TIMER_INT_OVERFLOW | | ||
238 | OMAP_TIMER_INT_MATCH); | ||
239 | } | ||
240 | #endif | ||
241 | |||
242 | clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC, | 200 | clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC, |
243 | NSEC_PER_SEC, | 201 | NSEC_PER_SEC, |
244 | clockevent_32k_timer.shift); | 202 | clockevent_32k_timer.shift); |