Merge branch 'omap3-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 into devel

13 files changed, 219 insertions, 185 deletions

diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c
index e31154b15d9e..f6684832ca8f 100644
--- a/arch/arm/plat-omap/debug-devices.c
+++ b/arch/arm/plat-omap/debug-devices.c
@@ -69,15 +69,15 @@ int __init debug_card_init(u32 addr, unsigned gpio)
         smc91x_resources[0].start = addr + 0x300;
         smc91x_resources[0].end   = addr + 0x30f;
 
-        smc91x_resources[1].start = OMAP_GPIO_IRQ(gpio);
-        smc91x_resources[1].end   = OMAP_GPIO_IRQ(gpio);
+        smc91x_resources[1].start = gpio_to_irq(gpio);
+        smc91x_resources[1].end   = gpio_to_irq(gpio);
 
-        status = omap_request_gpio(gpio);
+        status = gpio_request(gpio, "SMC91x irq");
         if (status < 0) {
                 printk(KERN_ERR "GPIO%d unavailable for smc91x IRQ\n", gpio);
                 return status;
         }
-        omap_set_gpio_direction(gpio, 1);
+        gpio_direction_input(gpio);
 
         led_resources[0].start = addr;
         led_resources[0].end   = addr + SZ_4K - 1;
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index 2f4c0cabfd34..be4eefda4767 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -83,8 +83,8 @@ static void h2p2_dbg_leds_event(led_event_t evt)
                 /* all leds off during suspend or shutdown */
 
                 if (!(machine_is_omap_perseus2() || machine_is_omap_h4())) {
-                        omap_set_gpio_dataout(GPIO_TIMER, 0);
-                        omap_set_gpio_dataout(GPIO_IDLE, 0);
+                        gpio_set_value(GPIO_TIMER, 0);
+                        gpio_set_value(GPIO_IDLE, 0);
                 }
 
                 __raw_writew(~0, &fpga->leds);
@@ -107,7 +107,7 @@ static void h2p2_dbg_leds_event(led_event_t evt)
                 if (machine_is_omap_perseus2() || machine_is_omap_h4())
                         hw_led_state ^= H2P2_DBG_FPGA_P2_LED_TIMER;
                 else {
-                        omap_set_gpio_dataout(GPIO_TIMER,
+                        gpio_set_value(GPIO_TIMER,
                                         led_state & LED_TIMER_ON);
                         goto done;
                 }
@@ -121,7 +121,7 @@ static void h2p2_dbg_leds_event(led_event_t evt)
                 if (machine_is_omap_perseus2() || machine_is_omap_h4())
                         hw_led_state &= ~H2P2_DBG_FPGA_P2_LED_IDLE;
                 else {
-                        omap_set_gpio_dataout(GPIO_IDLE, 1);
+                        gpio_set_value(GPIO_IDLE, 1);
                         goto done;
                 }
 
@@ -131,7 +131,7 @@ static void h2p2_dbg_leds_event(led_event_t evt)
                 if (machine_is_omap_perseus2() || machine_is_omap_h4())
                         hw_led_state |= H2P2_DBG_FPGA_P2_LED_IDLE;
                 else {
-                        omap_set_gpio_dataout(GPIO_IDLE, 0);
+                        gpio_set_value(GPIO_IDLE, 0);
                         goto done;
                 }
 
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 7686b9fa53f2..692d2b495af3 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1848,9 +1848,22 @@ static int omap2_dma_handle_ch(int ch)
                 printk(KERN_INFO
                        "DMA synchronization event drop occurred with device "
                        "%d\n", dma_chan[ch].dev_id);
-        if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ))
+        if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
                 printk(KERN_INFO "DMA transaction error with device %d\n",
                        dma_chan[ch].dev_id);
+                if (cpu_class_is_omap2()) {
+                        /* Errata: sDMA Channel is not disabled
+                         * after a transaction error. So we explicitely
+                         * disable the channel
+                         */
+                        u32 ccr;
+
+                        ccr = dma_read(CCR(ch));
+                        ccr &= ~OMAP_DMA_CCR_EN;
+                        dma_write(ccr, CCR(ch));
+                        dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
+                }
+        }
         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
                 printk(KERN_INFO "DMA secure error with device %d\n",
                        dma_chan[ch].dev_id);
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 963c31cd1541..e4f0ce04ba92 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -539,10 +539,6 @@ void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
         omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
 
-        /* REVISIT: hw feature, ttgr overtaking tldr? */
-        while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff)))
-                cpu_relax();
-
         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 }
 
@@ -553,14 +549,15 @@ void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
         u32 l;
 
         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
-        if (autoreload)
+        if (autoreload) {
                 l |= OMAP_TIMER_CTRL_AR;
-        else
+                omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
+        } else {
                 l &= ~OMAP_TIMER_CTRL_AR;
+        }
         l |= OMAP_TIMER_CTRL_ST;
 
         omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load);
-        omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 }
 
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 424049d83fbe..07b6968a7d16 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -152,6 +152,7 @@ struct gpio_bank {
         u32 level_mask;
         spinlock_t lock;
         struct gpio_chip chip;
+        struct clk *dbck;
 };
 
 #define METHOD_MPUIO            0
@@ -244,6 +245,8 @@ static inline struct gpio_bank *get_gpio_bank(int gpio)
                 return &gpio_bank[gpio >> 5];
         if (cpu_is_omap34xx())
                 return &gpio_bank[gpio >> 5];
+        BUG();
+        return NULL;
 }
 
 static inline int get_gpio_index(int gpio)
@@ -332,19 +335,6 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
         __raw_writel(l, reg);
 }
 
-void omap_set_gpio_direction(int gpio, int is_input)
-{
-        struct gpio_bank *bank;
-        unsigned long flags;
-
-        if (check_gpio(gpio) < 0)
-                return;
-        bank = get_gpio_bank(gpio);
-        spin_lock_irqsave(&bank->lock, flags);
-        _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
-        spin_unlock_irqrestore(&bank->lock, flags);
-}
-
 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
 {
         void __iomem *reg = bank->base;
@@ -406,20 +396,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
         __raw_writel(l, reg);
 }
 
-void omap_set_gpio_dataout(int gpio, int enable)
-{
-        struct gpio_bank *bank;
-        unsigned long flags;
-
-        if (check_gpio(gpio) < 0)
-                return;
-        bank = get_gpio_bank(gpio);
-        spin_lock_irqsave(&bank->lock, flags);
-        _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
-        spin_unlock_irqrestore(&bank->lock, flags);
-}
-
-int omap_get_gpio_datain(int gpio)
+static int __omap_get_gpio_datain(int gpio)
 {
         struct gpio_bank *bank;
         void __iomem *reg;
@@ -473,6 +450,7 @@ void omap_set_gpio_debounce(int gpio, int enable)
 {
         struct gpio_bank *bank;
         void __iomem *reg;
+        unsigned long flags;
         u32 val, l = 1 << get_gpio_index(gpio);
 
         if (cpu_class_is_omap1())
@@ -480,16 +458,28 @@ void omap_set_gpio_debounce(int gpio, int enable)
 
         bank = get_gpio_bank(gpio);
         reg = bank->base;
-
         reg += OMAP24XX_GPIO_DEBOUNCE_EN;
+
+        spin_lock_irqsave(&bank->lock, flags);
         val = __raw_readl(reg);
 
-        if (enable)
+        if (enable && !(val & l))
                 val |= l;
-        else
+        else if (!enable && (val & l))
                 val &= ~l;
+        else
+                goto done;
+
+        if (cpu_is_omap34xx()) {
+                if (enable)
+                        clk_enable(bank->dbck);
+                else
+                        clk_disable(bank->dbck);
+        }
 
         __raw_writel(val, reg);
+done:
+        spin_unlock_irqrestore(&bank->lock, flags);
 }
 EXPORT_SYMBOL(omap_set_gpio_debounce);
 
@@ -906,26 +896,17 @@ static int gpio_wake_enable(unsigned int irq, unsigned int enable)
         return retval;
 }
 
-int omap_request_gpio(int gpio)
+static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
 {
-        struct gpio_bank *bank;
+        struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
         unsigned long flags;
-        int status;
-
-        if (check_gpio(gpio) < 0)
-                return -EINVAL;
 
-        status = gpio_request(gpio, NULL);
-        if (status < 0)
-                return status;
-
-        bank = get_gpio_bank(gpio);
         spin_lock_irqsave(&bank->lock, flags);
 
         /* Set trigger to none. You need to enable the desired trigger with
          * request_irq() or set_irq_type().
          */
-        _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
+        _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
 
 #ifdef CONFIG_ARCH_OMAP15XX
         if (bank->method == METHOD_GPIO_1510) {
@@ -933,7 +914,7 @@ int omap_request_gpio(int gpio)
 
                 /* Claim the pin for MPU */
                 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
-                __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
+                __raw_writel(__raw_readl(reg) | (1 << offset), reg);
         }
 #endif
         spin_unlock_irqrestore(&bank->lock, flags);
@@ -941,39 +922,28 @@ int omap_request_gpio(int gpio)
         return 0;
 }
 
-void omap_free_gpio(int gpio)
+static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
 {
-        struct gpio_bank *bank;
+        struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
         unsigned long flags;
 
-        if (check_gpio(gpio) < 0)
-                return;
-        bank = get_gpio_bank(gpio);
         spin_lock_irqsave(&bank->lock, flags);
-        if (unlikely(!gpiochip_is_requested(&bank->chip,
-                                get_gpio_index(gpio)))) {
-                spin_unlock_irqrestore(&bank->lock, flags);
-                printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
-                dump_stack();
-                return;
-        }
 #ifdef CONFIG_ARCH_OMAP16XX
         if (bank->method == METHOD_GPIO_1610) {
                 /* Disable wake-up during idle for dynamic tick */
                 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
-                __raw_writel(1 << get_gpio_index(gpio), reg);
+                __raw_writel(1 << offset, reg);
         }
 #endif
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         if (bank->method == METHOD_GPIO_24XX) {
                 /* Disable wake-up during idle for dynamic tick */
                 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
-                __raw_writel(1 << get_gpio_index(gpio), reg);
+                __raw_writel(1 << offset, reg);
         }
 #endif
-        _reset_gpio(bank, gpio);
+        _reset_gpio(bank, bank->chip.base + offset);
         spin_unlock_irqrestore(&bank->lock, flags);
-        gpio_free(gpio);
 }
 
 /*
@@ -1252,7 +1222,7 @@ static int gpio_input(struct gpio_chip *chip, unsigned offset)
 
 static int gpio_get(struct gpio_chip *chip, unsigned offset)
 {
-        return omap_get_gpio_datain(chip->base + offset);
+        return __omap_get_gpio_datain(chip->base + offset);
 }
 
 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
@@ -1279,6 +1249,14 @@ static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
         spin_unlock_irqrestore(&bank->lock, flags);
 }
 
+static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
+{
+        struct gpio_bank *bank;
+
+        bank = container_of(chip, struct gpio_bank, chip);
+        return bank->virtual_irq_start + offset;
+}
+
 /*---------------------------------------------------------------------*/
 
 static int initialized;
@@ -1296,7 +1274,6 @@ static struct clk * gpio5_fck;
 #endif
 
 #if defined(CONFIG_ARCH_OMAP3)
-static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
 #endif
 
@@ -1310,9 +1287,7 @@ static int __init _omap_gpio_init(void)
         int i;
         int gpio = 0;
         struct gpio_bank *bank;
-#if defined(CONFIG_ARCH_OMAP3)
         char clk_name[11];
-#endif
 
         initialized = 1;
 
@@ -1367,12 +1342,6 @@ static int __init _omap_gpio_init(void)
                                 printk(KERN_ERR "Could not get %s\n", clk_name);
                         else
                                 clk_enable(gpio_iclks[i]);
-                        sprintf(clk_name, "gpio%d_fck", i + 1);
-                        gpio_fclks[i] = clk_get(NULL, clk_name);
-                        if (IS_ERR(gpio_fclks[i]))
-                                printk(KERN_ERR "Could not get %s\n", clk_name);
-                        else
-                                clk_enable(gpio_fclks[i]);
                 }
         }
 #endif
@@ -1479,10 +1448,13 @@ static int __init _omap_gpio_init(void)
                 /* REVISIT eventually switch from OMAP-specific gpio structs
                  * over to the generic ones
                  */
+                bank->chip.request = omap_gpio_request;
+                bank->chip.free = omap_gpio_free;
                 bank->chip.direction_input = gpio_input;
                 bank->chip.get = gpio_get;
                 bank->chip.direction_output = gpio_output;
                 bank->chip.set = gpio_set;
+                bank->chip.to_irq = gpio_2irq;
                 if (bank_is_mpuio(bank)) {
                         bank->chip.label = "mpuio";
 #ifdef CONFIG_ARCH_OMAP16XX
@@ -1511,6 +1483,13 @@ static int __init _omap_gpio_init(void)
                 }
                 set_irq_chained_handler(bank->irq, gpio_irq_handler);
                 set_irq_data(bank->irq, bank);
+
+                if (cpu_is_omap34xx()) {
+                        sprintf(clk_name, "gpio%d_dbck", i + 1);
+                        bank->dbck = clk_get(NULL, clk_name);
+                        if (IS_ERR(bank->dbck))
+                                printk(KERN_ERR "Could not get %s\n", clk_name);
+                }
         }
 
         /* Enable system clock for GPIO module.
@@ -1739,12 +1718,6 @@ static int __init omap_gpio_sysinit(void)
         return ret;
 }
 
-EXPORT_SYMBOL(omap_request_gpio);
-EXPORT_SYMBOL(omap_free_gpio);
-EXPORT_SYMBOL(omap_set_gpio_direction);
-EXPORT_SYMBOL(omap_set_gpio_dataout);
-EXPORT_SYMBOL(omap_get_gpio_datain);
-
 arch_initcall(omap_gpio_sysinit);
 
 
@@ -1801,14 +1774,14 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
                                 continue;
 
                         irq = bank->virtual_irq_start + j;
-                        value = omap_get_gpio_datain(gpio);
+                        value = gpio_get_value(gpio);
                         is_in = gpio_is_input(bank, mask);
 
                         if (bank_is_mpuio(bank))
                                 seq_printf(s, "MPUIO %2d ", j);
                         else
                                 seq_printf(s, "GPIO %3d ", gpio);
-                        seq_printf(s, "(%10s): %s %s",
+                        seq_printf(s, "(%-20.20s): %s %s",
                                         label,
                                         is_in ? "in " : "out",
                                         value ? "hi"  : "lo");
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index 0e6d147ab6f8..89a6ab0b7db8 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -79,26 +79,43 @@ static struct platform_device omap_i2c_devices[] = {
 #endif
 };
 
-static void __init omap_i2c_mux_pins(int bus_id)
+#if defined(CONFIG_ARCH_OMAP24XX)
+static const int omap24xx_pins[][2] = {
+        { M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA },
+        { J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA },
+};
+#else
+static const int omap24xx_pins[][2] = {};
+#endif
+#if defined(CONFIG_ARCH_OMAP34XX)
+static const int omap34xx_pins[][2] = {
+        { K21_34XX_I2C1_SCL, J21_34XX_I2C1_SDA},
+        { AF15_34XX_I2C2_SCL, AE15_34XX_I2C2_SDA},
+        { AF14_34XX_I2C3_SCL, AG14_34XX_I2C3_SDA},
+};
+#else
+static const int omap34xx_pins[][2] = {};
+#endif
+
+static void __init omap_i2c_mux_pins(int bus)
 {
-        /* TODO: Muxing for OMAP3 */
-        switch (bus_id) {
-        case 1:
-                if (cpu_class_is_omap1()) {
-                        omap_cfg_reg(I2C_SCL);
-                        omap_cfg_reg(I2C_SDA);
-                } else if (cpu_is_omap24xx()) {
-                        omap_cfg_reg(M19_24XX_I2C1_SCL);
-                        omap_cfg_reg(L15_24XX_I2C1_SDA);
-                }
-                break;
-        case 2:
-                if (cpu_is_omap24xx()) {
-                        omap_cfg_reg(J15_24XX_I2C2_SCL);
-                        omap_cfg_reg(H19_24XX_I2C2_SDA);
-                }
-                break;
+        int scl, sda;
+
+        if (cpu_class_is_omap1()) {
+                scl = I2C_SCL;
+                sda = I2C_SDA;
+        } else if (cpu_is_omap24xx()) {
+                scl = omap24xx_pins[bus][0];
+                sda = omap24xx_pins[bus][1];
+        } else if (cpu_is_omap34xx()) {
+                scl = omap34xx_pins[bus][0];
+                sda = omap34xx_pins[bus][1];
+        } else {
+                return;
         }
+
+        omap_cfg_reg(sda);
+        omap_cfg_reg(scl);
 }
 
 int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
@@ -142,6 +159,6 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
                 res[1].start = irq;
         }
 
-        omap_i2c_mux_pins(bus_id);
+        omap_i2c_mux_pins(bus_id - 1);
         return platform_device_register(pdev);
 }
diff --git a/arch/arm/plat-omap/include/mach/board-apollon.h b/arch/arm/plat-omap/include/mach/board-apollon.h
index 731c858cf3fe..61bd5e8f09b1 100644
--- a/arch/arm/plat-omap/include/mach/board-apollon.h
+++ b/arch/arm/plat-omap/include/mach/board-apollon.h
@@ -29,12 +29,14 @@
 #ifndef __ASM_ARCH_OMAP_APOLLON_H
 #define __ASM_ARCH_OMAP_APOLLON_H
 
+#include <mach/cpu.h>
+
 extern void apollon_mmc_init(void);
 
 static inline int apollon_plus(void)
 {
         /* The apollon plus has IDCODE revision 5 */
-        return system_rev & 0xc0;
+        return omap_rev() & 0xc0;
 }
 
 /* Placeholder for APOLLON specific defines */
diff --git a/arch/arm/plat-omap/include/mach/board-ldp.h b/arch/arm/plat-omap/include/mach/board-ldp.h
index 66e2746c04ca..f23399665212 100644
--- a/arch/arm/plat-omap/include/mach/board-ldp.h
+++ b/arch/arm/plat-omap/include/mach/board-ldp.h
@@ -32,5 +32,8 @@
 extern void twl4030_bci_battery_init(void);
 
 #define TWL4030_IRQNUM          INT_34XX_SYS_NIRQ
-
+#define LDP_SMC911X_CS         1
+#define LDP_SMC911X_GPIO       152
+#define DEBUG_BASE             0x08000000
+#define OMAP34XX_ETHR_START    DEBUG_BASE
 #endif /* __ASM_ARCH_OMAP_LDP_H */
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h
index e0464187209d..b2062f1175de 100644
--- a/arch/arm/plat-omap/include/mach/cpu.h
+++ b/arch/arm/plat-omap/include/mach/cpu.h
@@ -28,13 +28,18 @@
 
 struct omap_chip_id {
         u8 oc;
+        u8 type;
 };
 
 #define OMAP_CHIP_INIT(x)       { .oc = x }
 
-extern unsigned int system_rev;
-
-#define omap2_cpu_rev()         ((system_rev >> 12) & 0x0f)
+/*
+ * omap_rev bits:
+ * CPU id bits  (0730, 1510, 1710, 2422...)     [31:16]
+ * CPU revision (See _REV_ defined in cpu.h)    [15:08]
+ * CPU class bits (15xx, 16xx, 24xx, 34xx...)   [07:00]
+ */
+unsigned int omap_rev(void);
 
 /*
  * Test if multicore OMAP support is needed
@@ -108,7 +113,7 @@ extern unsigned int system_rev;
  * cpu_is_omap243x():   True for OMAP2430
  * cpu_is_omap343x():   True for OMAP3430
  */
-#define GET_OMAP_CLASS  ((system_rev >> 24) & 0xff)
+#define GET_OMAP_CLASS  (omap_rev() & 0xff)
 
 #define IS_OMAP_CLASS(class, id)                        \
 static inline int is_omap ##class (void)                \
@@ -116,7 +121,7 @@ static inline int is_omap ##class (void)		\
         return (GET_OMAP_CLASS == (id)) ? 1 : 0;        \
 }
 
-#define GET_OMAP_SUBCLASS       ((system_rev >> 20) & 0x0fff)
+#define GET_OMAP_SUBCLASS       ((omap_rev() >> 20) & 0x0fff)
 
 #define IS_OMAP_SUBCLASS(subclass, id)                  \
 static inline int is_omap ##subclass (void)             \
@@ -226,7 +231,7 @@ IS_OMAP_SUBCLASS(343x, 0x343)
  * cpu_is_omap2430():   True for OMAP2430
  * cpu_is_omap3430():   True for OMAP3430
  */
-#define GET_OMAP_TYPE   ((system_rev >> 16) & 0xffff)
+#define GET_OMAP_TYPE   ((omap_rev() >> 16) & 0xffff)
 
 #define IS_OMAP_TYPE(type, id)                          \
 static inline int is_omap ##type (void)                 \
@@ -320,44 +325,20 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define cpu_class_is_omap2()    (cpu_is_omap24xx() || cpu_is_omap34xx())
 
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-/*
- * Macros to detect silicon revision of OMAP2/3 processors.
- * is_sil_rev_greater_than:     true if passed cpu type & its rev is greater.
- * is_sil_rev_lesser_than:      true if passed cpu type & its rev is lesser.
- * is_sil_rev_equal_to:         true if passed cpu type & its rev is equal.
- * get_sil_rev:                 return the silicon rev value.
- */
-#define get_sil_omap_type(rev)  ((rev & 0xffff0000) >> 16)
-#define get_sil_revision(rev)   ((rev & 0x0000f000) >> 12)
 
-#define is_sil_rev_greater_than(rev) \
-                ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
-                (get_sil_revision(system_rev) > get_sil_revision(rev)))
+/* Various silicon revisions for omap2 */
+#define OMAP242X_CLASS          0x24200024
+#define OMAP2420_REV_ES1_0      0x24200024
+#define OMAP2420_REV_ES2_0      0x24201024
 
-#define is_sil_rev_less_than(rev) \
-                ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
-                (get_sil_revision(system_rev) < get_sil_revision(rev)))
+#define OMAP243X_CLASS          0x24300024
+#define OMAP2430_REV_ES1_0      0x24300024
 
-#define is_sil_rev_equal_to(rev) \
-                ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
-                (get_sil_revision(system_rev) == get_sil_revision(rev)))
-
-#define get_sil_rev() \
-                get_sil_revision(system_rev)
-
-/* Various silicon macros defined here */
-#define OMAP242X_CLASS          0x24200000
-#define OMAP2420_REV_ES1_0      0x24200000
-#define OMAP2420_REV_ES2_0      0x24201000
-
-#define OMAP243X_CLASS          0x24300000
-#define OMAP2430_REV_ES1_0      0x24300000
-
-#define OMAP343X_CLASS          0x34300000
-#define OMAP3430_REV_ES1_0      0x34300000
-#define OMAP3430_REV_ES2_0      0x34301000
-#define OMAP3430_REV_ES2_1      0x34302000
-#define OMAP3430_REV_ES2_2      0x34303000
+#define OMAP343X_CLASS          0x34300034
+#define OMAP3430_REV_ES1_0      0x34300034
+#define OMAP3430_REV_ES2_0      0x34301034
+#define OMAP3430_REV_ES2_1      0x34302034
+#define OMAP3430_REV_ES3_0      0x34303034
 
 /*
  * omap_chip bits
@@ -382,23 +363,16 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define CHIP_IS_OMAP24XX       (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
 
 int omap_chip_is(struct omap_chip_id oci);
-
+int omap_type(void);
 
 /*
  * Macro to detect device type i.e. EMU/HS/TST/GP/BAD
  */
-#define DEVICE_TYPE_TEST        0
-#define DEVICE_TYPE_EMU         1
-#define DEVICE_TYPE_SEC         2
-#define DEVICE_TYPE_GP          3
-#define DEVICE_TYPE_BAD         4
-
-#define get_device_type()       ((system_rev & 0x700) >> 8)
-#define is_device_type_test()   (get_device_type() == DEVICE_TYPE_TEST)
-#define is_device_type_emu()    (get_device_type() == DEVICE_TYPE_EMU)
-#define is_device_type_sec()    (get_device_type() == DEVICE_TYPE_SEC)
-#define is_device_type_gp()     (get_device_type() == DEVICE_TYPE_GP)
-#define is_device_type_bad()    (get_device_type() == DEVICE_TYPE_BAD)
+#define OMAP2_DEVICE_TYPE_TEST          0
+#define OMAP2_DEVICE_TYPE_EMU           1
+#define OMAP2_DEVICE_TYPE_SEC           2
+#define OMAP2_DEVICE_TYPE_GP            3
+#define OMAP2_DEVICE_TYPE_BAD           4
 
 void omap2_check_revision(void);
 
diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/mach/gpio.h
index 98e9008b7e9d..04e68e88f134 100644
--- a/arch/arm/plat-omap/include/mach/gpio.h
+++ b/arch/arm/plat-omap/include/mach/gpio.h
@@ -71,11 +71,6 @@
                                  IH_GPIO_BASE + (nr))
 
 extern int omap_gpio_init(void);        /* Call from board init only */
-extern int omap_request_gpio(int gpio);
-extern void omap_free_gpio(int gpio);
-extern void omap_set_gpio_direction(int gpio, int is_input);
-extern void omap_set_gpio_dataout(int gpio, int enable);
-extern int omap_get_gpio_datain(int gpio);
 extern void omap2_gpio_prepare_for_retention(void);
 extern void omap2_gpio_resume_after_retention(void);
 extern void omap_set_gpio_debounce(int gpio, int enable);
@@ -92,6 +87,16 @@ extern void omap_set_gpio_debounce_time(int gpio, int enable);
 #include <linux/errno.h>
 #include <asm-generic/gpio.h>
 
+static inline int omap_request_gpio(int gpio)
+{
+        return gpio_request(gpio, "FIXME");
+}
+
+static inline void omap_free_gpio(int gpio)
+{
+        gpio_free(gpio);
+}
+
 static inline int gpio_get_value(unsigned gpio)
 {
         return __gpio_get_value(gpio);
@@ -109,16 +114,24 @@ static inline int gpio_cansleep(unsigned gpio)
 
 static inline int gpio_to_irq(unsigned gpio)
 {
-        if (gpio < (OMAP_MAX_GPIO_LINES + 16))
-                return OMAP_GPIO_IRQ(gpio);
-        return -EINVAL;
+        return __gpio_to_irq(gpio);
 }
 
 static inline int irq_to_gpio(unsigned irq)
 {
+        int tmp;
+
+        /* omap1 SOC mpuio */
         if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16)))
                 return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES;
-        return irq - IH_GPIO_BASE;
+
+        /* SOC gpio */
+        tmp = irq - IH_GPIO_BASE;
+        if (tmp < OMAP_MAX_GPIO_LINES)
+                return tmp;
+
+        /* we don't supply reverse mappings for non-SOC gpios */
+        return -EIO;
 }
 
 #endif
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h
index 6bbf1789bed5..f4362b8682c7 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -632,6 +632,15 @@ enum omap24xx_index {
         AC7_2430_USB0HS_DATA7,
 
         /* 2430 McBSP */
+        AD6_2430_MCBSP_CLKS,
+
+        AB2_2430_MCBSP1_CLKR,
+        AD5_2430_MCBSP1_FSR,
+        AA1_2430_MCBSP1_DX,
+        AF3_2430_MCBSP1_DR,
+        AB3_2430_MCBSP1_FSX,
+        Y9_2430_MCBSP1_CLKX,
+
         AC10_2430_MCBSP2_FSX,
         AD16_2430_MCBSP2_CLX,
         AE13_2430_MCBSP2_DX,
@@ -641,6 +650,30 @@ enum omap24xx_index {
         AE13_2430_MCBSP2_DX_OFF,
         AD13_2430_MCBSP2_DR_OFF,
 
+        AC9_2430_MCBSP3_CLKX,
+        AE4_2430_MCBSP3_FSX,
+        AE2_2430_MCBSP3_DR,
+        AF4_2430_MCBSP3_DX,
+
+        N3_2430_MCBSP4_CLKX,
+        AD23_2430_MCBSP4_DR,
+        AB25_2430_MCBSP4_DX,
+        AC25_2430_MCBSP4_FSX,
+
+        AE16_2430_MCBSP5_CLKX,
+        AF12_2430_MCBSP5_FSX,
+        K7_2430_MCBSP5_DX,
+        M1_2430_MCBSP5_DR,
+
+        /* 2430 McSPI*/
+        Y18_2430_MCSPI1_CLK,
+        AD15_2430_MCSPI1_SIMO,
+        AE17_2430_MCSPI1_SOMI,
+        U1_2430_MCSPI1_CS0,
+
+        /* Touchscreen GPIO */
+        AF19_2430_GPIO_85,
+
 };
 
 enum omap34xx_index {
@@ -749,6 +782,14 @@ enum omap34xx_index {
         AD2_3430_USB3FS_PHY_MM3_TXDAT,
         AC1_3430_USB3FS_PHY_MM3_TXEN_N,
 
+        /* 34xx GPIO
+         *  - normally these are bidirectional, no internal pullup/pulldown
+         *  - "_UP" suffix (GPIO3_UP) if internal pullup is configured
+         *  - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown
+         *  - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx)
+         */
+        AH8_34XX_GPIO29,
+        J25_34XX_GPIO170,
 };
 
 struct omap_mux_cfg {
diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/mach/omapfb.h
index ec67fb428607..7b74d1255e0b 100644
--- a/arch/arm/plat-omap/include/mach/omapfb.h
+++ b/arch/arm/plat-omap/include/mach/omapfb.h
@@ -353,8 +353,8 @@ struct omapfb_device {
         u32                     pseudo_palette[17];
 
         struct lcd_panel        *panel;                 /* LCD panel */
-        struct lcd_ctrl         *ctrl;                  /* LCD controller */
-        struct lcd_ctrl         *int_ctrl;              /* internal LCD ctrl */
+        const struct lcd_ctrl   *ctrl;                  /* LCD controller */
+        const struct lcd_ctrl   *int_ctrl;              /* internal LCD ctrl */
         struct lcd_ctrl_extif   *ext_if;                /* LCD ctrl external
                                                            interface */
         struct device           *dev;
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 9f9a921829c0..be7bcaf2b832 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -24,6 +24,7 @@
 
 #include <mach/sram.h>
 #include <mach/board.h>
+#include <mach/cpu.h>
 
 #include <mach/control.h>
 
@@ -87,7 +88,7 @@ static int is_sram_locked(void)
         int type = 0;
 
         if (cpu_is_omap242x())
-                type = system_rev & OMAP2_DEVICETYPE_MASK;
+                type = omap_rev() & OMAP2_DEVICETYPE_MASK;
 
         if (type == GP_DEVICE) {
                 /* RAMFW: R/W access to all initiators for all qualifier sets */
@@ -255,7 +256,7 @@ void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
         if (!_omap_sram_reprogram_clock)
                 omap_sram_error();
 
-        return _omap_sram_reprogram_clock(dpllctl, ckctl);
+        _omap_sram_reprogram_clock(dpllctl, ckctl);
 }
 
 int __init omap1_sram_init(void)
@@ -282,8 +283,8 @@ void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
         if (!_omap2_sram_ddr_init)
                 omap_sram_error();
 
-        return _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
-                                    base_cs, force_unlock);
+        _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
+                             base_cs, force_unlock);
 }
 
 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
@@ -294,7 +295,7 @@ void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
         if (!_omap2_sram_reprogram_sdrc)
                 omap_sram_error();
 
-        return _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
+        _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
 }
 
 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);