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authorTony Lindgren <tony@atomide.com>2005-11-10 09:26:50 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-11-10 09:26:50 -0500
commit1a8bfa1eb998af6e650ad26201f7cae9f2a2fdc8 (patch)
tree1a9748171dbfe89a59e621009c32b5bb12d10f81 /arch/arm/plat-omap
parent3179a019391f0f8081245fd564a5f1be308ba64f (diff)
[ARM] 3142/1: OMAP 2/5: Update files common to omap1 and omap2
Patch from Tony Lindgren This patch syncs the mainline kernel with linux-omap tree. The highlights of the patch are: - Serial port and framebuffer init improvments by Imre Deak - Common omap pin mux framework by Tony Lindgren - Common omap clock framework by Tony Lindren Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r--arch/arm/plat-omap/Makefile2
-rw-r--r--arch/arm/plat-omap/clock.c1315
-rw-r--r--arch/arm/plat-omap/clock.h120
-rw-r--r--arch/arm/plat-omap/common.c50
-rw-r--r--arch/arm/plat-omap/devices.c381
-rw-r--r--arch/arm/plat-omap/dma.c910
-rw-r--r--arch/arm/plat-omap/gpio.c40
-rw-r--r--arch/arm/plat-omap/mcbsp.c22
-rw-r--r--arch/arm/plat-omap/mux.c65
-rw-r--r--arch/arm/plat-omap/pm.c103
-rw-r--r--arch/arm/plat-omap/sleep.S139
-rw-r--r--arch/arm/plat-omap/sram.c143
-rw-r--r--arch/arm/plat-omap/sram.h21
-rw-r--r--arch/arm/plat-omap/usb.c11
14 files changed, 1583 insertions, 1739 deletions
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 7e144f9cad1c..9ccf1943fc94 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := common.o sram.o sram-fn.o clock.o dma.o mux.o gpio.o mcbsp.o usb.o 6obj-y := common.o sram.o sram-fn.o clock.o devices.o dma.o mux.o gpio.o mcbsp.o usb.o
7obj-m := 7obj-m :=
8obj-n := 8obj-n :=
9obj- := 9obj- :=
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index a020fe16428f..7ce39b986e23 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -1,15 +1,20 @@
1/* 1/*
2 * linux/arch/arm/plat-omap/clock.c 2 * linux/arch/arm/plat-omap/clock.c
3 * 3 *
4 * Copyright (C) 2004 Nokia corporation 4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * 6 *
7 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
8 *
7 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
10 */ 12 */
11#include <linux/module.h> 13#include <linux/version.h>
14#include <linux/config.h>
12#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/module.h>
13#include <linux/list.h> 18#include <linux/list.h>
14#include <linux/errno.h> 19#include <linux/errno.h>
15#include <linux/err.h> 20#include <linux/err.h>
@@ -18,562 +23,20 @@
18#include <asm/io.h> 23#include <asm/io.h>
19#include <asm/semaphore.h> 24#include <asm/semaphore.h>
20#include <asm/hardware/clock.h> 25#include <asm/hardware/clock.h>
21#include <asm/arch/board.h>
22#include <asm/arch/usb.h>
23 26
24#include "clock.h" 27#include <asm/arch/clock.h>
25#include "sram.h"
26 28
27static LIST_HEAD(clocks); 29LIST_HEAD(clocks);
28static DECLARE_MUTEX(clocks_sem); 30static DECLARE_MUTEX(clocks_sem);
29static DEFINE_SPINLOCK(clockfw_lock); 31DEFINE_SPINLOCK(clockfw_lock);
30static void propagate_rate(struct clk * clk);
31/* UART clock function */
32static int set_uart_rate(struct clk * clk, unsigned long rate);
33/* External clock (MCLK & BCLK) functions */
34static int set_ext_clk_rate(struct clk * clk, unsigned long rate);
35static long round_ext_clk_rate(struct clk * clk, unsigned long rate);
36static void init_ext_clk(struct clk * clk);
37/* MPU virtual clock functions */
38static int select_table_rate(struct clk * clk, unsigned long rate);
39static long round_to_table_rate(struct clk * clk, unsigned long rate);
40void clk_setdpll(__u16, __u16);
41
42static struct mpu_rate rate_table[] = {
43 /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
44 * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
45 */
46#if defined(CONFIG_OMAP_ARM_216MHZ)
47 { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
48#endif
49#if defined(CONFIG_OMAP_ARM_195MHZ)
50 { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
51#endif
52#if defined(CONFIG_OMAP_ARM_192MHZ)
53 { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
54 { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
55 { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
56 { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/8/4/4/8/8 */
57 { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
58#endif
59#if defined(CONFIG_OMAP_ARM_182MHZ)
60 { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
61#endif
62#if defined(CONFIG_OMAP_ARM_168MHZ)
63 { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
64#endif
65#if defined(CONFIG_OMAP_ARM_150MHZ)
66 { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
67#endif
68#if defined(CONFIG_OMAP_ARM_120MHZ)
69 { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
70#endif
71#if defined(CONFIG_OMAP_ARM_96MHZ)
72 { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
73#endif
74#if defined(CONFIG_OMAP_ARM_60MHZ)
75 { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
76#endif
77#if defined(CONFIG_OMAP_ARM_30MHZ)
78 { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
79#endif
80 { 0, 0, 0, 0, 0 },
81};
82
83
84static void ckctl_recalc(struct clk * clk);
85int __clk_enable(struct clk *clk);
86void __clk_disable(struct clk *clk);
87void __clk_unuse(struct clk *clk);
88int __clk_use(struct clk *clk);
89
90
91static void followparent_recalc(struct clk * clk)
92{
93 clk->rate = clk->parent->rate;
94}
95
96
97static void watchdog_recalc(struct clk * clk)
98{
99 clk->rate = clk->parent->rate / 14;
100}
101
102static void uart_recalc(struct clk * clk)
103{
104 unsigned int val = omap_readl(clk->enable_reg);
105 if (val & clk->enable_bit)
106 clk->rate = 48000000;
107 else
108 clk->rate = 12000000;
109}
110
111static struct clk ck_ref = {
112 .name = "ck_ref",
113 .rate = 12000000,
114 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
115 ALWAYS_ENABLED,
116};
117
118static struct clk ck_dpll1 = {
119 .name = "ck_dpll1",
120 .parent = &ck_ref,
121 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
122 RATE_PROPAGATES | ALWAYS_ENABLED,
123};
124
125static struct clk ck_dpll1out = {
126 .name = "ck_dpll1out",
127 .parent = &ck_dpll1,
128 .flags = CLOCK_IN_OMAP16XX,
129 .enable_reg = ARM_IDLECT2,
130 .enable_bit = EN_CKOUT_ARM,
131 .recalc = &followparent_recalc,
132};
133
134static struct clk arm_ck = {
135 .name = "arm_ck",
136 .parent = &ck_dpll1,
137 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
138 RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
139 .rate_offset = CKCTL_ARMDIV_OFFSET,
140 .recalc = &ckctl_recalc,
141};
142
143static struct clk armper_ck = {
144 .name = "armper_ck",
145 .parent = &ck_dpll1,
146 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
147 RATE_CKCTL,
148 .enable_reg = ARM_IDLECT2,
149 .enable_bit = EN_PERCK,
150 .rate_offset = CKCTL_PERDIV_OFFSET,
151 .recalc = &ckctl_recalc,
152};
153
154static struct clk arm_gpio_ck = {
155 .name = "arm_gpio_ck",
156 .parent = &ck_dpll1,
157 .flags = CLOCK_IN_OMAP1510,
158 .enable_reg = ARM_IDLECT2,
159 .enable_bit = EN_GPIOCK,
160 .recalc = &followparent_recalc,
161};
162
163static struct clk armxor_ck = {
164 .name = "armxor_ck",
165 .parent = &ck_ref,
166 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
167 .enable_reg = ARM_IDLECT2,
168 .enable_bit = EN_XORPCK,
169 .recalc = &followparent_recalc,
170};
171
172static struct clk armtim_ck = {
173 .name = "armtim_ck",
174 .parent = &ck_ref,
175 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
176 .enable_reg = ARM_IDLECT2,
177 .enable_bit = EN_TIMCK,
178 .recalc = &followparent_recalc,
179};
180
181static struct clk armwdt_ck = {
182 .name = "armwdt_ck",
183 .parent = &ck_ref,
184 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
185 .enable_reg = ARM_IDLECT2,
186 .enable_bit = EN_WDTCK,
187 .recalc = &watchdog_recalc,
188};
189
190static struct clk arminth_ck16xx = {
191 .name = "arminth_ck",
192 .parent = &arm_ck,
193 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
194 .recalc = &followparent_recalc,
195 /* Note: On 16xx the frequency can be divided by 2 by programming
196 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
197 *
198 * 1510 version is in TC clocks.
199 */
200};
201
202static struct clk dsp_ck = {
203 .name = "dsp_ck",
204 .parent = &ck_dpll1,
205 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
206 RATE_CKCTL,
207 .enable_reg = ARM_CKCTL,
208 .enable_bit = EN_DSPCK,
209 .rate_offset = CKCTL_DSPDIV_OFFSET,
210 .recalc = &ckctl_recalc,
211};
212
213static struct clk dspmmu_ck = {
214 .name = "dspmmu_ck",
215 .parent = &ck_dpll1,
216 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
217 RATE_CKCTL | ALWAYS_ENABLED,
218 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
219 .recalc = &ckctl_recalc,
220};
221
222static struct clk dspper_ck = {
223 .name = "dspper_ck",
224 .parent = &ck_dpll1,
225 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
226 RATE_CKCTL | DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
227 .enable_reg = DSP_IDLECT2,
228 .enable_bit = EN_PERCK,
229 .rate_offset = CKCTL_PERDIV_OFFSET,
230 .recalc = &followparent_recalc,
231 //.recalc = &ckctl_recalc,
232};
233
234static struct clk dspxor_ck = {
235 .name = "dspxor_ck",
236 .parent = &ck_ref,
237 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
238 DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
239 .enable_reg = DSP_IDLECT2,
240 .enable_bit = EN_XORPCK,
241 .recalc = &followparent_recalc,
242};
243
244static struct clk dsptim_ck = {
245 .name = "dsptim_ck",
246 .parent = &ck_ref,
247 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
248 DSP_DOMAIN_CLOCK | VIRTUAL_IO_ADDRESS,
249 .enable_reg = DSP_IDLECT2,
250 .enable_bit = EN_DSPTIMCK,
251 .recalc = &followparent_recalc,
252};
253
254static struct clk tc_ck = {
255 .name = "tc_ck",
256 .parent = &ck_dpll1,
257 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 |
258 RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,
259 .rate_offset = CKCTL_TCDIV_OFFSET,
260 .recalc = &ckctl_recalc,
261};
262
263static struct clk arminth_ck1510 = {
264 .name = "arminth_ck",
265 .parent = &tc_ck,
266 .flags = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
267 .recalc = &followparent_recalc,
268 /* Note: On 1510 the frequency follows TC_CK
269 *
270 * 16xx version is in MPU clocks.
271 */
272};
273
274static struct clk tipb_ck = {
275 .name = "tibp_ck",
276 .parent = &tc_ck,
277 .flags = CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,
278 .recalc = &followparent_recalc,
279};
280
281static struct clk l3_ocpi_ck = {
282 .name = "l3_ocpi_ck",
283 .parent = &tc_ck,
284 .flags = CLOCK_IN_OMAP16XX,
285 .enable_reg = ARM_IDLECT3,
286 .enable_bit = EN_OCPI_CK,
287 .recalc = &followparent_recalc,
288};
289 32
290static struct clk tc1_ck = { 33static struct clk_functions *arch_clock;
291 .name = "tc1_ck",
292 .parent = &tc_ck,
293 .flags = CLOCK_IN_OMAP16XX,
294 .enable_reg = ARM_IDLECT3,
295 .enable_bit = EN_TC1_CK,
296 .recalc = &followparent_recalc,
297};
298 34
299static struct clk tc2_ck = { 35/*-------------------------------------------------------------------------
300 .name = "tc2_ck", 36 * Standard clock functions defined in asm/hardware/clock.h
301 .parent = &tc_ck, 37 *-------------------------------------------------------------------------*/
302 .flags = CLOCK_IN_OMAP16XX,
303 .enable_reg = ARM_IDLECT3,
304 .enable_bit = EN_TC2_CK,
305 .recalc = &followparent_recalc,
306};
307 38
308static struct clk dma_ck = { 39struct clk * clk_get(struct device *dev, const char *id)
309 .name = "dma_ck",
310 .parent = &tc_ck,
311 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
312 ALWAYS_ENABLED,
313 .recalc = &followparent_recalc,
314};
315
316static struct clk dma_lcdfree_ck = {
317 .name = "dma_lcdfree_ck",
318 .parent = &tc_ck,
319 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
320 .recalc = &followparent_recalc,
321};
322
323static struct clk api_ck = {
324 .name = "api_ck",
325 .parent = &tc_ck,
326 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
327 .enable_reg = ARM_IDLECT2,
328 .enable_bit = EN_APICK,
329 .recalc = &followparent_recalc,
330};
331
332static struct clk lb_ck = {
333 .name = "lb_ck",
334 .parent = &tc_ck,
335 .flags = CLOCK_IN_OMAP1510,
336 .enable_reg = ARM_IDLECT2,
337 .enable_bit = EN_LBCK,
338 .recalc = &followparent_recalc,
339};
340
341static struct clk rhea1_ck = {
342 .name = "rhea1_ck",
343 .parent = &tc_ck,
344 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
345 .recalc = &followparent_recalc,
346};
347
348static struct clk rhea2_ck = {
349 .name = "rhea2_ck",
350 .parent = &tc_ck,
351 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
352 .recalc = &followparent_recalc,
353};
354
355static struct clk lcd_ck = {
356 .name = "lcd_ck",
357 .parent = &ck_dpll1,
358 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 |
359 RATE_CKCTL,
360 .enable_reg = ARM_IDLECT2,
361 .enable_bit = EN_LCDCK,
362 .rate_offset = CKCTL_LCDDIV_OFFSET,
363 .recalc = &ckctl_recalc,
364};
365
366static struct clk uart1_1510 = {
367 .name = "uart1_ck",
368 /* Direct from ULPD, no parent */
369 .rate = 12000000,
370 .flags = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT | ALWAYS_ENABLED,
371 .enable_reg = MOD_CONF_CTRL_0,
372 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */
373 .set_rate = &set_uart_rate,
374 .recalc = &uart_recalc,
375};
376
377static struct clk uart1_16xx = {
378 .name = "uart1_ck",
379 /* Direct from ULPD, no parent */
380 .rate = 48000000,
381 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | ENABLE_REG_32BIT,
382 .enable_reg = MOD_CONF_CTRL_0,
383 .enable_bit = 29,
384};
385
386static struct clk uart2_ck = {
387 .name = "uart2_ck",
388 /* Direct from ULPD, no parent */
389 .rate = 12000000,
390 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | ENABLE_REG_32BIT |
391 ALWAYS_ENABLED,
392 .enable_reg = MOD_CONF_CTRL_0,
393 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */
394 .set_rate = &set_uart_rate,
395 .recalc = &uart_recalc,
396};
397
398static struct clk uart3_1510 = {
399 .name = "uart3_ck",
400 /* Direct from ULPD, no parent */
401 .rate = 12000000,
402 .flags = CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT | ALWAYS_ENABLED,
403 .enable_reg = MOD_CONF_CTRL_0,
404 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */
405 .set_rate = &set_uart_rate,
406 .recalc = &uart_recalc,
407};
408
409static struct clk uart3_16xx = {
410 .name = "uart3_ck",
411 /* Direct from ULPD, no parent */
412 .rate = 48000000,
413 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | ENABLE_REG_32BIT,
414 .enable_reg = MOD_CONF_CTRL_0,
415 .enable_bit = 31,
416};
417
418static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
419 .name = "usb_clko",
420 /* Direct from ULPD, no parent */
421 .rate = 6000000,
422 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
423 RATE_FIXED | ENABLE_REG_32BIT,
424 .enable_reg = ULPD_CLOCK_CTRL,
425 .enable_bit = USB_MCLK_EN_BIT,
426};
427
428static struct clk usb_hhc_ck1510 = {
429 .name = "usb_hhc_ck",
430 /* Direct from ULPD, no parent */
431 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
432 .flags = CLOCK_IN_OMAP1510 |
433 RATE_FIXED | ENABLE_REG_32BIT,
434 .enable_reg = MOD_CONF_CTRL_0,
435 .enable_bit = USB_HOST_HHC_UHOST_EN,
436};
437
438static struct clk usb_hhc_ck16xx = {
439 .name = "usb_hhc_ck",
440 /* Direct from ULPD, no parent */
441 .rate = 48000000,
442 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
443 .flags = CLOCK_IN_OMAP16XX |
444 RATE_FIXED | ENABLE_REG_32BIT,
445 .enable_reg = OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
446 .enable_bit = 8 /* UHOST_EN */,
447};
448
449static struct clk usb_dc_ck = {
450 .name = "usb_dc_ck",
451 /* Direct from ULPD, no parent */
452 .rate = 48000000,
453 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED,
454 .enable_reg = SOFT_REQ_REG,
455 .enable_bit = 4,
456};
457
458static struct clk mclk_1510 = {
459 .name = "mclk",
460 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
461 .rate = 12000000,
462 .flags = CLOCK_IN_OMAP1510 | RATE_FIXED,
463};
464
465static struct clk mclk_16xx = {
466 .name = "mclk",
467 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
468 .flags = CLOCK_IN_OMAP16XX,
469 .enable_reg = COM_CLK_DIV_CTRL_SEL,
470 .enable_bit = COM_ULPD_PLL_CLK_REQ,
471 .set_rate = &set_ext_clk_rate,
472 .round_rate = &round_ext_clk_rate,
473 .init = &init_ext_clk,
474};
475
476static struct clk bclk_1510 = {
477 .name = "bclk",
478 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
479 .rate = 12000000,
480 .flags = CLOCK_IN_OMAP1510 | RATE_FIXED,
481};
482
483static struct clk bclk_16xx = {
484 .name = "bclk",
485 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
486 .flags = CLOCK_IN_OMAP16XX,
487 .enable_reg = SWD_CLK_DIV_CTRL_SEL,
488 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
489 .set_rate = &set_ext_clk_rate,
490 .round_rate = &round_ext_clk_rate,
491 .init = &init_ext_clk,
492};
493
494static struct clk mmc1_ck = {
495 .name = "mmc1_ck",
496 /* Functional clock is direct from ULPD, interface clock is ARMPER */
497 .parent = &armper_ck,
498 .rate = 48000000,
499 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
500 RATE_FIXED | ENABLE_REG_32BIT,
501 .enable_reg = MOD_CONF_CTRL_0,
502 .enable_bit = 23,
503};
504
505static struct clk mmc2_ck = {
506 .name = "mmc2_ck",
507 /* Functional clock is direct from ULPD, interface clock is ARMPER */
508 .parent = &armper_ck,
509 .rate = 48000000,
510 .flags = CLOCK_IN_OMAP16XX |
511 RATE_FIXED | ENABLE_REG_32BIT,
512 .enable_reg = MOD_CONF_CTRL_0,
513 .enable_bit = 20,
514};
515
516static struct clk virtual_ck_mpu = {
517 .name = "mpu",
518 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
519 VIRTUAL_CLOCK | ALWAYS_ENABLED,
520 .parent = &arm_ck, /* Is smarter alias for */
521 .recalc = &followparent_recalc,
522 .set_rate = &select_table_rate,
523 .round_rate = &round_to_table_rate,
524};
525
526
527static struct clk * onchip_clks[] = {
528 /* non-ULPD clocks */
529 &ck_ref,
530 &ck_dpll1,
531 /* CK_GEN1 clocks */
532 &ck_dpll1out,
533 &arm_ck,
534 &armper_ck,
535 &arm_gpio_ck,
536 &armxor_ck,
537 &armtim_ck,
538 &armwdt_ck,
539 &arminth_ck1510, &arminth_ck16xx,
540 /* CK_GEN2 clocks */
541 &dsp_ck,
542 &dspmmu_ck,
543 &dspper_ck,
544 &dspxor_ck,
545 &dsptim_ck,
546 /* CK_GEN3 clocks */
547 &tc_ck,
548 &tipb_ck,
549 &l3_ocpi_ck,
550 &tc1_ck,
551 &tc2_ck,
552 &dma_ck,
553 &dma_lcdfree_ck,
554 &api_ck,
555 &lb_ck,
556 &rhea1_ck,
557 &rhea2_ck,
558 &lcd_ck,
559 /* ULPD clocks */
560 &uart1_1510,
561 &uart1_16xx,
562 &uart2_ck,
563 &uart3_1510,
564 &uart3_16xx,
565 &usb_clko,
566 &usb_hhc_ck1510, &usb_hhc_ck16xx,
567 &usb_dc_ck,
568 &mclk_1510, &mclk_16xx,
569 &bclk_1510, &bclk_16xx,
570 &mmc1_ck,
571 &mmc2_ck,
572 /* Virtual clocks */
573 &virtual_ck_mpu,
574};
575
576struct clk *clk_get(struct device *dev, const char *id)
577{ 40{
578 struct clk *p, *clk = ERR_PTR(-ENOENT); 41 struct clk *p, *clk = ERR_PTR(-ENOENT);
579 42
@@ -590,534 +53,200 @@ struct clk *clk_get(struct device *dev, const char *id)
590} 53}
591EXPORT_SYMBOL(clk_get); 54EXPORT_SYMBOL(clk_get);
592 55
593
594void clk_put(struct clk *clk)
595{
596 if (clk && !IS_ERR(clk))
597 module_put(clk->owner);
598}
599EXPORT_SYMBOL(clk_put);
600
601
602int __clk_enable(struct clk *clk)
603{
604 __u16 regval16;
605 __u32 regval32;
606
607 if (clk->flags & ALWAYS_ENABLED)
608 return 0;
609
610 if (unlikely(clk->enable_reg == 0)) {
611 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
612 clk->name);
613 return 0;
614 }
615
616 if (clk->flags & DSP_DOMAIN_CLOCK) {
617 __clk_use(&api_ck);
618 }
619
620 if (clk->flags & ENABLE_REG_32BIT) {
621 if (clk->flags & VIRTUAL_IO_ADDRESS) {
622 regval32 = __raw_readl(clk->enable_reg);
623 regval32 |= (1 << clk->enable_bit);
624 __raw_writel(regval32, clk->enable_reg);
625 } else {
626 regval32 = omap_readl(clk->enable_reg);
627 regval32 |= (1 << clk->enable_bit);
628 omap_writel(regval32, clk->enable_reg);
629 }
630 } else {
631 if (clk->flags & VIRTUAL_IO_ADDRESS) {
632 regval16 = __raw_readw(clk->enable_reg);
633 regval16 |= (1 << clk->enable_bit);
634 __raw_writew(regval16, clk->enable_reg);
635 } else {
636 regval16 = omap_readw(clk->enable_reg);
637 regval16 |= (1 << clk->enable_bit);
638 omap_writew(regval16, clk->enable_reg);
639 }
640 }
641
642 if (clk->flags & DSP_DOMAIN_CLOCK) {
643 __clk_unuse(&api_ck);
644 }
645
646 return 0;
647}
648
649
650void __clk_disable(struct clk *clk)
651{
652 __u16 regval16;
653 __u32 regval32;
654
655 if (clk->enable_reg == 0)
656 return;
657
658 if (clk->flags & DSP_DOMAIN_CLOCK) {
659 __clk_use(&api_ck);
660 }
661
662 if (clk->flags & ENABLE_REG_32BIT) {
663 if (clk->flags & VIRTUAL_IO_ADDRESS) {
664 regval32 = __raw_readl(clk->enable_reg);
665 regval32 &= ~(1 << clk->enable_bit);
666 __raw_writel(regval32, clk->enable_reg);
667 } else {
668 regval32 = omap_readl(clk->enable_reg);
669 regval32 &= ~(1 << clk->enable_bit);
670 omap_writel(regval32, clk->enable_reg);
671 }
672 } else {
673 if (clk->flags & VIRTUAL_IO_ADDRESS) {
674 regval16 = __raw_readw(clk->enable_reg);
675 regval16 &= ~(1 << clk->enable_bit);
676 __raw_writew(regval16, clk->enable_reg);
677 } else {
678 regval16 = omap_readw(clk->enable_reg);
679 regval16 &= ~(1 << clk->enable_bit);
680 omap_writew(regval16, clk->enable_reg);
681 }
682 }
683
684 if (clk->flags & DSP_DOMAIN_CLOCK) {
685 __clk_unuse(&api_ck);
686 }
687}
688
689
690void __clk_unuse(struct clk *clk)
691{
692 if (clk->usecount > 0 && !(--clk->usecount)) {
693 __clk_disable(clk);
694 if (likely(clk->parent))
695 __clk_unuse(clk->parent);
696 }
697}
698
699
700int __clk_use(struct clk *clk)
701{
702 int ret = 0;
703 if (clk->usecount++ == 0) {
704 if (likely(clk->parent))
705 ret = __clk_use(clk->parent);
706
707 if (unlikely(ret != 0)) {
708 clk->usecount--;
709 return ret;
710 }
711
712 ret = __clk_enable(clk);
713
714 if (unlikely(ret != 0) && clk->parent) {
715 __clk_unuse(clk->parent);
716 clk->usecount--;
717 }
718 }
719
720 return ret;
721}
722
723
724int clk_enable(struct clk *clk) 56int clk_enable(struct clk *clk)
725{ 57{
726 unsigned long flags; 58 unsigned long flags;
727 int ret; 59 int ret = 0;
728 60
729 spin_lock_irqsave(&clockfw_lock, flags); 61 spin_lock_irqsave(&clockfw_lock, flags);
730 ret = __clk_enable(clk); 62 if (clk->enable)
63 ret = clk->enable(clk);
64 else if (arch_clock->clk_enable)
65 ret = arch_clock->clk_enable(clk);
66 else
67 printk(KERN_ERR "Could not enable clock %s\n", clk->name);
731 spin_unlock_irqrestore(&clockfw_lock, flags); 68 spin_unlock_irqrestore(&clockfw_lock, flags);
69
732 return ret; 70 return ret;
733} 71}
734EXPORT_SYMBOL(clk_enable); 72EXPORT_SYMBOL(clk_enable);
735 73
736
737void clk_disable(struct clk *clk) 74void clk_disable(struct clk *clk)
738{ 75{
739 unsigned long flags; 76 unsigned long flags;
740 77
741 spin_lock_irqsave(&clockfw_lock, flags); 78 spin_lock_irqsave(&clockfw_lock, flags);
742 __clk_disable(clk); 79 if (clk->disable)
80 clk->disable(clk);
81 else if (arch_clock->clk_disable)
82 arch_clock->clk_disable(clk);
83 else
84 printk(KERN_ERR "Could not disable clock %s\n", clk->name);
743 spin_unlock_irqrestore(&clockfw_lock, flags); 85 spin_unlock_irqrestore(&clockfw_lock, flags);
744} 86}
745EXPORT_SYMBOL(clk_disable); 87EXPORT_SYMBOL(clk_disable);
746 88
747
748int clk_use(struct clk *clk) 89int clk_use(struct clk *clk)
749{ 90{
750 unsigned long flags; 91 unsigned long flags;
751 int ret = 0; 92 int ret = 0;
752 93
753 spin_lock_irqsave(&clockfw_lock, flags); 94 spin_lock_irqsave(&clockfw_lock, flags);
754 ret = __clk_use(clk); 95 if (arch_clock->clk_use)
96 ret = arch_clock->clk_use(clk);
755 spin_unlock_irqrestore(&clockfw_lock, flags); 97 spin_unlock_irqrestore(&clockfw_lock, flags);
98
756 return ret; 99 return ret;
757} 100}
758EXPORT_SYMBOL(clk_use); 101EXPORT_SYMBOL(clk_use);
759 102
760
761void clk_unuse(struct clk *clk) 103void clk_unuse(struct clk *clk)
762{ 104{
763 unsigned long flags; 105 unsigned long flags;
764 106
765 spin_lock_irqsave(&clockfw_lock, flags); 107 spin_lock_irqsave(&clockfw_lock, flags);
766 __clk_unuse(clk); 108 if (arch_clock->clk_unuse)
109 arch_clock->clk_unuse(clk);
767 spin_unlock_irqrestore(&clockfw_lock, flags); 110 spin_unlock_irqrestore(&clockfw_lock, flags);
768} 111}
769EXPORT_SYMBOL(clk_unuse); 112EXPORT_SYMBOL(clk_unuse);
770 113
771
772int clk_get_usecount(struct clk *clk) 114int clk_get_usecount(struct clk *clk)
773{ 115{
774 return clk->usecount; 116 unsigned long flags;
775} 117 int ret = 0;
776EXPORT_SYMBOL(clk_get_usecount);
777
778
779unsigned long clk_get_rate(struct clk *clk)
780{
781 return clk->rate;
782}
783EXPORT_SYMBOL(clk_get_rate);
784
785
786static __u16 verify_ckctl_value(__u16 newval)
787{
788 /* This function checks for following limitations set
789 * by the hardware (all conditions must be true):
790 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
791 * ARM_CK >= TC_CK
792 * DSP_CK >= TC_CK
793 * DSPMMU_CK >= TC_CK
794 *
795 * In addition following rules are enforced:
796 * LCD_CK <= TC_CK
797 * ARMPER_CK <= TC_CK
798 *
799 * However, maximum frequencies are not checked for!
800 */
801 __u8 per_exp;
802 __u8 lcd_exp;
803 __u8 arm_exp;
804 __u8 dsp_exp;
805 __u8 tc_exp;
806 __u8 dspmmu_exp;
807
808 per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
809 lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
810 arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
811 dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
812 tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
813 dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
814
815 if (dspmmu_exp < dsp_exp)
816 dspmmu_exp = dsp_exp;
817 if (dspmmu_exp > dsp_exp+1)
818 dspmmu_exp = dsp_exp+1;
819 if (tc_exp < arm_exp)
820 tc_exp = arm_exp;
821 if (tc_exp < dspmmu_exp)
822 tc_exp = dspmmu_exp;
823 if (tc_exp > lcd_exp)
824 lcd_exp = tc_exp;
825 if (tc_exp > per_exp)
826 per_exp = tc_exp;
827 118
828 newval &= 0xf000; 119 spin_lock_irqsave(&clockfw_lock, flags);
829 newval |= per_exp << CKCTL_PERDIV_OFFSET; 120 ret = clk->usecount;
830 newval |= lcd_exp << CKCTL_LCDDIV_OFFSET; 121 spin_unlock_irqrestore(&clockfw_lock, flags);
831 newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
832 newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
833 newval |= tc_exp << CKCTL_TCDIV_OFFSET;
834 newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
835 122
836 return newval; 123 return ret;
837} 124}
125EXPORT_SYMBOL(clk_get_usecount);
838 126
839 127unsigned long clk_get_rate(struct clk *clk)
840static int calc_dsor_exp(struct clk *clk, unsigned long rate)
841{ 128{
842 /* Note: If target frequency is too low, this function will return 4, 129 unsigned long flags;
843 * which is invalid value. Caller must check for this value and act 130 unsigned long ret = 0;
844 * accordingly.
845 *
846 * Note: This function does not check for following limitations set
847 * by the hardware (all conditions must be true):
848 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
849 * ARM_CK >= TC_CK
850 * DSP_CK >= TC_CK
851 * DSPMMU_CK >= TC_CK
852 */
853 unsigned long realrate;
854 struct clk * parent;
855 unsigned dsor_exp;
856
857 if (unlikely(!(clk->flags & RATE_CKCTL)))
858 return -EINVAL;
859
860 parent = clk->parent;
861 if (unlikely(parent == 0))
862 return -EIO;
863
864 realrate = parent->rate;
865 for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
866 if (realrate <= rate)
867 break;
868 131
869 realrate /= 2; 132 spin_lock_irqsave(&clockfw_lock, flags);
870 } 133 ret = clk->rate;
134 spin_unlock_irqrestore(&clockfw_lock, flags);
871 135
872 return dsor_exp; 136 return ret;
873} 137}
138EXPORT_SYMBOL(clk_get_rate);
874 139
875 140void clk_put(struct clk *clk)
876static void ckctl_recalc(struct clk * clk)
877{ 141{
878 int dsor; 142 if (clk && !IS_ERR(clk))
879 143 module_put(clk->owner);
880 /* Calculate divisor encoded as 2-bit exponent */
881 if (clk->flags & DSP_DOMAIN_CLOCK) {
882 /* The clock control bits are in DSP domain,
883 * so api_ck is needed for access.
884 * Note that DSP_CKCTL virt addr = phys addr, so
885 * we must use __raw_readw() instead of omap_readw().
886 */
887 __clk_use(&api_ck);
888 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
889 __clk_unuse(&api_ck);
890 } else {
891 dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
892 }
893 if (unlikely(clk->rate == clk->parent->rate / dsor))
894 return; /* No change, quick exit */
895 clk->rate = clk->parent->rate / dsor;
896
897 if (unlikely(clk->flags & RATE_PROPAGATES))
898 propagate_rate(clk);
899} 144}
145EXPORT_SYMBOL(clk_put);
900 146
147/*-------------------------------------------------------------------------
148 * Optional clock functions defined in asm/hardware/clock.h
149 *-------------------------------------------------------------------------*/
901 150
902long clk_round_rate(struct clk *clk, unsigned long rate) 151long clk_round_rate(struct clk *clk, unsigned long rate)
903{ 152{
904 int dsor_exp; 153 unsigned long flags;
905 154 long ret = 0;
906 if (clk->flags & RATE_FIXED)
907 return clk->rate;
908
909 if (clk->flags & RATE_CKCTL) {
910 dsor_exp = calc_dsor_exp(clk, rate);
911 if (dsor_exp < 0)
912 return dsor_exp;
913 if (dsor_exp > 3)
914 dsor_exp = 3;
915 return clk->parent->rate / (1 << dsor_exp);
916 }
917 155
918 if(clk->round_rate != 0) 156 spin_lock_irqsave(&clockfw_lock, flags);
919 return clk->round_rate(clk, rate); 157 if (arch_clock->clk_round_rate)
158 ret = arch_clock->clk_round_rate(clk, rate);
159 spin_unlock_irqrestore(&clockfw_lock, flags);
920 160
921 return clk->rate; 161 return ret;
922} 162}
923EXPORT_SYMBOL(clk_round_rate); 163EXPORT_SYMBOL(clk_round_rate);
924 164
925 165int clk_set_rate(struct clk *clk, unsigned long rate)
926static void propagate_rate(struct clk * clk)
927{
928 struct clk ** clkp;
929
930 for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
931 if (likely((*clkp)->parent != clk)) continue;
932 if (likely((*clkp)->recalc))
933 (*clkp)->recalc(*clkp);
934 }
935}
936
937
938static int select_table_rate(struct clk * clk, unsigned long rate)
939{ 166{
940 /* Find the highest supported frequency <= rate and switch to it */ 167 unsigned long flags;
941 struct mpu_rate * ptr; 168 int ret = 0;
942
943 if (clk != &virtual_ck_mpu)
944 return -EINVAL;
945
946 for (ptr = rate_table; ptr->rate; ptr++) {
947 if (ptr->xtal != ck_ref.rate)
948 continue;
949
950 /* DPLL1 cannot be reprogrammed without risking system crash */
951 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
952 continue;
953
954 /* Can check only after xtal frequency check */
955 if (ptr->rate <= rate)
956 break;
957 }
958
959 if (!ptr->rate)
960 return -EINVAL;
961 169
962 /* 170 spin_lock_irqsave(&clockfw_lock, flags);
963 * In most cases we should not need to reprogram DPLL. 171 if (arch_clock->clk_set_rate)
964 * Reprogramming the DPLL is tricky, it must be done from SRAM. 172 ret = arch_clock->clk_set_rate(clk, rate);
965 */ 173 spin_unlock_irqrestore(&clockfw_lock, flags);
966 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
967 174
968 ck_dpll1.rate = ptr->pll_rate; 175 return ret;
969 propagate_rate(&ck_dpll1);
970 return 0;
971} 176}
177EXPORT_SYMBOL(clk_set_rate);
972 178
973 179int clk_set_parent(struct clk *clk, struct clk *parent)
974static long round_to_table_rate(struct clk * clk, unsigned long rate)
975{ 180{
976 /* Find the highest supported frequency <= rate */ 181 unsigned long flags;
977 struct mpu_rate * ptr; 182 int ret = 0;
978 long highest_rate;
979
980 if (clk != &virtual_ck_mpu)
981 return -EINVAL;
982
983 highest_rate = -EINVAL;
984
985 for (ptr = rate_table; ptr->rate; ptr++) {
986 if (ptr->xtal != ck_ref.rate)
987 continue;
988
989 highest_rate = ptr->rate;
990 183
991 /* Can check only after xtal frequency check */ 184 spin_lock_irqsave(&clockfw_lock, flags);
992 if (ptr->rate <= rate) 185 if (arch_clock->clk_set_parent)
993 break; 186 ret = arch_clock->clk_set_parent(clk, parent);
994 } 187 spin_unlock_irqrestore(&clockfw_lock, flags);
995 188
996 return highest_rate; 189 return ret;
997} 190}
191EXPORT_SYMBOL(clk_set_parent);
998 192
999 193struct clk *clk_get_parent(struct clk *clk)
1000int clk_set_rate(struct clk *clk, unsigned long rate)
1001{ 194{
1002 int ret = -EINVAL; 195 unsigned long flags;
1003 int dsor_exp; 196 struct clk * ret = NULL;
1004 __u16 regval;
1005 unsigned long flags;
1006
1007 if (clk->flags & RATE_CKCTL) {
1008 dsor_exp = calc_dsor_exp(clk, rate);
1009 if (dsor_exp > 3)
1010 dsor_exp = -EINVAL;
1011 if (dsor_exp < 0)
1012 return dsor_exp;
1013
1014 spin_lock_irqsave(&clockfw_lock, flags);
1015 regval = omap_readw(ARM_CKCTL);
1016 regval &= ~(3 << clk->rate_offset);
1017 regval |= dsor_exp << clk->rate_offset;
1018 regval = verify_ckctl_value(regval);
1019 omap_writew(regval, ARM_CKCTL);
1020 clk->rate = clk->parent->rate / (1 << dsor_exp);
1021 spin_unlock_irqrestore(&clockfw_lock, flags);
1022 ret = 0;
1023 } else if(clk->set_rate != 0) {
1024 spin_lock_irqsave(&clockfw_lock, flags);
1025 ret = clk->set_rate(clk, rate);
1026 spin_unlock_irqrestore(&clockfw_lock, flags);
1027 }
1028 197
1029 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) 198 spin_lock_irqsave(&clockfw_lock, flags);
1030 propagate_rate(clk); 199 if (arch_clock->clk_get_parent)
200 ret = arch_clock->clk_get_parent(clk);
201 spin_unlock_irqrestore(&clockfw_lock, flags);
1031 202
1032 return ret; 203 return ret;
1033} 204}
1034EXPORT_SYMBOL(clk_set_rate); 205EXPORT_SYMBOL(clk_get_parent);
1035 206
207/*-------------------------------------------------------------------------
208 * OMAP specific clock functions shared between omap1 and omap2
209 *-------------------------------------------------------------------------*/
1036 210
1037static unsigned calc_ext_dsor(unsigned long rate) 211unsigned int __initdata mpurate;
1038{
1039 unsigned dsor;
1040 212
1041 /* MCLK and BCLK divisor selection is not linear: 213/*
1042 * freq = 96MHz / dsor 214 * By default we use the rate set by the bootloader.
1043 * 215 * You can override this with mpurate= cmdline option.
1044 * RATIO_SEL range: dsor <-> RATIO_SEL 216 */
1045 * 0..6: (RATIO_SEL+2) <-> (dsor-2) 217static int __init omap_clk_setup(char *str)
1046 * 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
1047 * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
1048 * can not be used.
1049 */
1050 for (dsor = 2; dsor < 96; ++dsor) {
1051 if ((dsor & 1) && dsor > 8)
1052 continue;
1053 if (rate >= 96000000 / dsor)
1054 break;
1055 }
1056 return dsor;
1057}
1058
1059/* Only needed on 1510 */
1060static int set_uart_rate(struct clk * clk, unsigned long rate)
1061{
1062 unsigned int val;
1063
1064 val = omap_readl(clk->enable_reg);
1065 if (rate == 12000000)
1066 val &= ~(1 << clk->enable_bit);
1067 else if (rate == 48000000)
1068 val |= (1 << clk->enable_bit);
1069 else
1070 return -EINVAL;
1071 omap_writel(val, clk->enable_reg);
1072 clk->rate = rate;
1073
1074 return 0;
1075}
1076
1077static int set_ext_clk_rate(struct clk * clk, unsigned long rate)
1078{ 218{
1079 unsigned dsor; 219 get_option(&str, &mpurate);
1080 __u16 ratio_bits;
1081 220
1082 dsor = calc_ext_dsor(rate); 221 if (!mpurate)
1083 clk->rate = 96000000 / dsor; 222 return 1;
1084 if (dsor > 8)
1085 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
1086 else
1087 ratio_bits = (dsor - 2) << 2;
1088 223
1089 ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd; 224 if (mpurate < 1000)
1090 omap_writew(ratio_bits, clk->enable_reg); 225 mpurate *= 1000000;
1091 226
1092 return 0; 227 return 1;
1093} 228}
229__setup("mpurate=", omap_clk_setup);
1094 230
1095 231/* Used for clocks that always have same value as the parent clock */
1096static long round_ext_clk_rate(struct clk * clk, unsigned long rate) 232void followparent_recalc(struct clk *clk)
1097{ 233{
1098 return 96000000 / calc_ext_dsor(rate); 234 clk->rate = clk->parent->rate;
1099} 235}
1100 236
1101 237/* Propagate rate to children */
1102static void init_ext_clk(struct clk * clk) 238void propagate_rate(struct clk * tclk)
1103{ 239{
1104 unsigned dsor; 240 struct clk *clkp;
1105 __u16 ratio_bits;
1106 241
1107 /* Determine current rate and ensure clock is based on 96MHz APLL */ 242 list_for_each_entry(clkp, &clocks, node) {
1108 ratio_bits = omap_readw(clk->enable_reg) & ~1; 243 if (likely(clkp->parent != tclk))
1109 omap_writew(ratio_bits, clk->enable_reg); 244 continue;
1110 245 if (likely((u32)clkp->recalc))
1111 ratio_bits = (ratio_bits & 0xfc) >> 2; 246 clkp->recalc(clkp);
1112 if (ratio_bits > 6) 247 }
1113 dsor = (ratio_bits - 6) * 2 + 8;
1114 else
1115 dsor = ratio_bits + 2;
1116
1117 clk-> rate = 96000000 / dsor;
1118} 248}
1119 249
1120
1121int clk_register(struct clk *clk) 250int clk_register(struct clk *clk)
1122{ 251{
1123 down(&clocks_sem); 252 down(&clocks_sem);
@@ -1125,6 +254,7 @@ int clk_register(struct clk *clk)
1125 if (clk->init) 254 if (clk->init)
1126 clk->init(clk); 255 clk->init(clk);
1127 up(&clocks_sem); 256 up(&clocks_sem);
257
1128 return 0; 258 return 0;
1129} 259}
1130EXPORT_SYMBOL(clk_register); 260EXPORT_SYMBOL(clk_register);
@@ -1137,203 +267,38 @@ void clk_unregister(struct clk *clk)
1137} 267}
1138EXPORT_SYMBOL(clk_unregister); 268EXPORT_SYMBOL(clk_unregister);
1139 269
1140#ifdef CONFIG_OMAP_RESET_CLOCKS 270void clk_deny_idle(struct clk *clk)
1141/*
1142 * Resets some clocks that may be left on from bootloader,
1143 * but leaves serial clocks on. See also omap_late_clk_reset().
1144 */
1145static inline void omap_early_clk_reset(void)
1146{ 271{
1147 //omap_writel(0x3 << 29, MOD_CONF_CTRL_0); 272 unsigned long flags;
273
274 spin_lock_irqsave(&clockfw_lock, flags);
275 if (arch_clock->clk_deny_idle)
276 arch_clock->clk_deny_idle(clk);
277 spin_unlock_irqrestore(&clockfw_lock, flags);
1148} 278}
1149#else 279EXPORT_SYMBOL(clk_deny_idle);
1150#define omap_early_clk_reset() {}
1151#endif
1152 280
1153int __init clk_init(void) 281void clk_allow_idle(struct clk *clk)
1154{ 282{
1155 struct clk ** clkp; 283 unsigned long flags;
1156 const struct omap_clock_config *info;
1157 int crystal_type = 0; /* Default 12 MHz */
1158
1159 omap_early_clk_reset();
1160
1161 for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
1162 if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) {
1163 clk_register(*clkp);
1164 continue;
1165 }
1166
1167 if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) {
1168 clk_register(*clkp);
1169 continue;
1170 }
1171
1172 if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) {
1173 clk_register(*clkp);
1174 continue;
1175 }
1176 }
1177
1178 info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
1179 if (info != NULL) {
1180 if (!cpu_is_omap1510())
1181 crystal_type = info->system_clock_type;
1182 }
1183
1184#if defined(CONFIG_ARCH_OMAP730)
1185 ck_ref.rate = 13000000;
1186#elif defined(CONFIG_ARCH_OMAP16XX)
1187 if (crystal_type == 2)
1188 ck_ref.rate = 19200000;
1189#endif
1190
1191 printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
1192 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
1193 omap_readw(ARM_CKCTL));
1194
1195 /* We want to be in syncronous scalable mode */
1196 omap_writew(0x1000, ARM_SYSST);
1197
1198#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
1199 /* Use values set by bootloader. Determine PLL rate and recalculate
1200 * dependent clocks as if kernel had changed PLL or divisors.
1201 */
1202 {
1203 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
1204
1205 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
1206 if (pll_ctl_val & 0x10) {
1207 /* PLL enabled, apply multiplier and divisor */
1208 if (pll_ctl_val & 0xf80)
1209 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
1210 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
1211 } else {
1212 /* PLL disabled, apply bypass divisor */
1213 switch (pll_ctl_val & 0xc) {
1214 case 0:
1215 break;
1216 case 0x4:
1217 ck_dpll1.rate /= 2;
1218 break;
1219 default:
1220 ck_dpll1.rate /= 4;
1221 break;
1222 }
1223 }
1224 }
1225 propagate_rate(&ck_dpll1);
1226#else
1227 /* Find the highest supported frequency and enable it */
1228 if (select_table_rate(&virtual_ck_mpu, ~0)) {
1229 printk(KERN_ERR "System frequencies not set. Check your config.\n");
1230 /* Guess sane values (60MHz) */
1231 omap_writew(0x2290, DPLL_CTL);
1232 omap_writew(0x1005, ARM_CKCTL);
1233 ck_dpll1.rate = 60000000;
1234 propagate_rate(&ck_dpll1);
1235 }
1236#endif
1237 /* Cache rates for clocks connected to ck_ref (not dpll1) */
1238 propagate_rate(&ck_ref);
1239 printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
1240 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
1241 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
1242 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
1243 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
1244
1245#ifdef CONFIG_MACH_OMAP_PERSEUS2
1246 /* Select slicer output as OMAP input clock */
1247 omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
1248#endif
1249
1250 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
1251 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
1252
1253 /* Put DSP/MPUI into reset until needed */
1254 omap_writew(0, ARM_RSTCT1);
1255 omap_writew(1, ARM_RSTCT2);
1256 omap_writew(0x400, ARM_IDLECT1);
1257
1258 /*
1259 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
1260 * of the ARM_IDLECT2 register must be set to zero. The power-on
1261 * default value of this bit is one.
1262 */
1263 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
1264
1265 /*
1266 * Only enable those clocks we will need, let the drivers
1267 * enable other clocks as necessary
1268 */
1269 clk_use(&armper_ck);
1270 clk_use(&armxor_ck);
1271 clk_use(&armtim_ck);
1272
1273 if (cpu_is_omap1510())
1274 clk_enable(&arm_gpio_ck);
1275 284
1276 return 0; 285 spin_lock_irqsave(&clockfw_lock, flags);
286 if (arch_clock->clk_allow_idle)
287 arch_clock->clk_allow_idle(clk);
288 spin_unlock_irqrestore(&clockfw_lock, flags);
1277} 289}
290EXPORT_SYMBOL(clk_allow_idle);
1278 291
292/*-------------------------------------------------------------------------*/
1279 293
1280#ifdef CONFIG_OMAP_RESET_CLOCKS 294int __init clk_init(struct clk_functions * custom_clocks)
1281
1282static int __init omap_late_clk_reset(void)
1283{ 295{
1284 /* Turn off all unused clocks */ 296 if (!custom_clocks) {
1285 struct clk *p; 297 printk(KERN_ERR "No custom clock functions registered\n");
1286 __u32 regval32; 298 BUG();
1287
1288 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
1289 regval32 = omap_readw(SOFT_REQ_REG) & (1 << 4);
1290 omap_writew(regval32, SOFT_REQ_REG);
1291 omap_writew(0, SOFT_REQ_REG2);
1292
1293 list_for_each_entry(p, &clocks, node) {
1294 if (p->usecount > 0 || (p->flags & ALWAYS_ENABLED) ||
1295 p->enable_reg == 0)
1296 continue;
1297
1298 /* Assume no DSP clocks have been activated by bootloader */
1299 if (p->flags & DSP_DOMAIN_CLOCK)
1300 continue;
1301
1302 /* Is the clock already disabled? */
1303 if (p->flags & ENABLE_REG_32BIT) {
1304 if (p->flags & VIRTUAL_IO_ADDRESS)
1305 regval32 = __raw_readl(p->enable_reg);
1306 else
1307 regval32 = omap_readl(p->enable_reg);
1308 } else {
1309 if (p->flags & VIRTUAL_IO_ADDRESS)
1310 regval32 = __raw_readw(p->enable_reg);
1311 else
1312 regval32 = omap_readw(p->enable_reg);
1313 }
1314
1315 if ((regval32 & (1 << p->enable_bit)) == 0)
1316 continue;
1317
1318 /* FIXME: This clock seems to be necessary but no-one
1319 * has asked for its activation. */
1320 if (p == &tc2_ck // FIX: pm.c (SRAM), CCP, Camera
1321 || p == &ck_dpll1out // FIX: SoSSI, SSR
1322 || p == &arm_gpio_ck // FIX: GPIO code for 1510
1323 ) {
1324 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
1325 p->name);
1326 continue;
1327 }
1328
1329 printk(KERN_INFO "Disabling unused clock \"%s\"... ", p->name);
1330 __clk_disable(p);
1331 printk(" done\n");
1332 } 299 }
1333 300
301 arch_clock = custom_clocks;
302
1334 return 0; 303 return 0;
1335} 304}
1336
1337late_initcall(omap_late_clk_reset);
1338
1339#endif
diff --git a/arch/arm/plat-omap/clock.h b/arch/arm/plat-omap/clock.h
deleted file mode 100644
index a89e1e8c2519..000000000000
--- a/arch/arm/plat-omap/clock.h
+++ /dev/null
@@ -1,120 +0,0 @@
1/*
2 * linux/arch/arm/plat-omap/clock.h
3 *
4 * Copyright (C) 2004 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ARCH_ARM_OMAP_CLOCK_H
14#define __ARCH_ARM_OMAP_CLOCK_H
15
16struct module;
17
18struct clk {
19 struct list_head node;
20 struct module *owner;
21 const char *name;
22 struct clk *parent;
23 unsigned long rate;
24 __s8 usecount;
25 __u16 flags;
26 __u32 enable_reg;
27 __u8 enable_bit;
28 __u8 rate_offset;
29 void (*recalc)(struct clk *);
30 int (*set_rate)(struct clk *, unsigned long);
31 long (*round_rate)(struct clk *, unsigned long);
32 void (*init)(struct clk *);
33};
34
35
36struct mpu_rate {
37 unsigned long rate;
38 unsigned long xtal;
39 unsigned long pll_rate;
40 __u16 ckctl_val;
41 __u16 dpllctl_val;
42};
43
44
45/* Clock flags */
46#define RATE_CKCTL 1
47#define RATE_FIXED 2
48#define RATE_PROPAGATES 4
49#define VIRTUAL_CLOCK 8
50#define ALWAYS_ENABLED 16
51#define ENABLE_REG_32BIT 32
52#define CLOCK_IN_OMAP16XX 64
53#define CLOCK_IN_OMAP1510 128
54#define CLOCK_IN_OMAP730 256
55#define DSP_DOMAIN_CLOCK 512
56#define VIRTUAL_IO_ADDRESS 1024
57
58/* ARM_CKCTL bit shifts */
59#define CKCTL_PERDIV_OFFSET 0
60#define CKCTL_LCDDIV_OFFSET 2
61#define CKCTL_ARMDIV_OFFSET 4
62#define CKCTL_DSPDIV_OFFSET 6
63#define CKCTL_TCDIV_OFFSET 8
64#define CKCTL_DSPMMUDIV_OFFSET 10
65/*#define ARM_TIMXO 12*/
66#define EN_DSPCK 13
67/*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */
68/* DSP_CKCTL bit shifts */
69#define CKCTL_DSPPERDIV_OFFSET 0
70
71/* ARM_IDLECT1 bit shifts */
72/*#define IDLWDT_ARM 0*/
73/*#define IDLXORP_ARM 1*/
74/*#define IDLPER_ARM 2*/
75/*#define IDLLCD_ARM 3*/
76/*#define IDLLB_ARM 4*/
77/*#define IDLHSAB_ARM 5*/
78/*#define IDLIF_ARM 6*/
79/*#define IDLDPLL_ARM 7*/
80/*#define IDLAPI_ARM 8*/
81/*#define IDLTIM_ARM 9*/
82/*#define SETARM_IDLE 11*/
83
84/* ARM_IDLECT2 bit shifts */
85#define EN_WDTCK 0
86#define EN_XORPCK 1
87#define EN_PERCK 2
88#define EN_LCDCK 3
89#define EN_LBCK 4 /* Not on 1610/1710 */
90/*#define EN_HSABCK 5*/
91#define EN_APICK 6
92#define EN_TIMCK 7
93#define DMACK_REQ 8
94#define EN_GPIOCK 9 /* Not on 1610/1710 */
95/*#define EN_LBFREECK 10*/
96#define EN_CKOUT_ARM 11
97
98/* ARM_IDLECT3 bit shifts */
99#define EN_OCPI_CK 0
100#define EN_TC1_CK 2
101#define EN_TC2_CK 4
102
103/* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
104#define EN_DSPTIMCK 5
105
106/* Various register defines for clock controls scattered around OMAP chip */
107#define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */
108#define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */
109#define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */
110#define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */
111#define SWD_CLK_DIV_CTRL_SEL 0xfffe0874
112#define COM_CLK_DIV_CTRL_SEL 0xfffe0878
113#define SOFT_REQ_REG 0xfffe0834
114#define SOFT_REQ_REG2 0xfffe0880
115
116int clk_register(struct clk *clk);
117void clk_unregister(struct clk *clk);
118int clk_init(void);
119
120#endif
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 02bcc6c1cd1b..ccdb452630cf 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -31,7 +31,7 @@
31#include <asm/arch/mux.h> 31#include <asm/arch/mux.h>
32#include <asm/arch/fpga.h> 32#include <asm/arch/fpga.h>
33 33
34#include "clock.h" 34#include <asm/arch/clock.h>
35 35
36#define NO_LENGTH_CHECK 0xffffffff 36#define NO_LENGTH_CHECK 0xffffffff
37 37
@@ -117,19 +117,43 @@ EXPORT_SYMBOL(omap_get_var_config);
117 117
118static int __init omap_add_serial_console(void) 118static int __init omap_add_serial_console(void)
119{ 119{
120 const struct omap_serial_console_config *info; 120 const struct omap_serial_console_config *con_info;
121 121 const struct omap_uart_config *uart_info;
122 info = omap_get_config(OMAP_TAG_SERIAL_CONSOLE, 122 static char speed[11], *opt = NULL;
123 struct omap_serial_console_config); 123 int line, i, uart_idx;
124 if (info != NULL && info->console_uart) { 124
125 static char speed[11], *opt = NULL; 125 uart_info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
126 con_info = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
127 struct omap_serial_console_config);
128 if (uart_info == NULL || con_info == NULL)
129 return 0;
130
131 if (con_info->console_uart == 0)
132 return 0;
133
134 if (con_info->console_speed) {
135 snprintf(speed, sizeof(speed), "%u", con_info->console_speed);
136 opt = speed;
137 }
126 138
127 if (info->console_speed) { 139 uart_idx = con_info->console_uart - 1;
128 snprintf(speed, sizeof(speed), "%u", info->console_speed); 140 if (uart_idx >= OMAP_MAX_NR_PORTS) {
129 opt = speed; 141 printk(KERN_INFO "Console: external UART#%d. "
130 } 142 "Not adding it as console this time.\n",
131 return add_preferred_console("ttyS", info->console_uart - 1, opt); 143 uart_idx + 1);
144 return 0;
145 }
146 if (!(uart_info->enabled_uarts & (1 << uart_idx))) {
147 printk(KERN_ERR "Console: Selected UART#%d is "
148 "not enabled for this platform\n",
149 uart_idx + 1);
150 return -1;
151 }
152 line = 0;
153 for (i = 0; i < uart_idx; i++) {
154 if (uart_info->enabled_uarts & (1 << i))
155 line++;
132 } 156 }
133 return 0; 157 return add_preferred_console("ttyS", line, opt);
134} 158}
135console_initcall(omap_add_serial_console); 159console_initcall(omap_add_serial_console);
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
new file mode 100644
index 000000000000..9dcce904b608
--- /dev/null
+++ b/arch/arm/plat-omap/devices.c
@@ -0,0 +1,381 @@
1/*
2 * linux/arch/arm/plat-omap/devices.c
3 *
4 * Common platform device setup/initialization for OMAP1 and OMAP2
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/config.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17
18#include <asm/hardware.h>
19#include <asm/io.h>
20#include <asm/mach-types.h>
21#include <asm/mach/map.h>
22
23#include <asm/arch/tc.h>
24#include <asm/arch/board.h>
25#include <asm/arch/mux.h>
26#include <asm/arch/gpio.h>
27
28
29void omap_nop_release(struct device *dev)
30{
31 /* Nothing */
32}
33
34/*-------------------------------------------------------------------------*/
35
36#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
37
38#define OMAP1_I2C_BASE 0xfffb3800
39#define OMAP2_I2C_BASE1 0x48070000
40#define OMAP_I2C_SIZE 0x3f
41#define OMAP1_I2C_INT INT_I2C
42#define OMAP2_I2C_INT1 56
43
44static struct resource i2c_resources1[] = {
45 {
46 .start = 0,
47 .end = 0,
48 .flags = IORESOURCE_MEM,
49 },
50 {
51 .start = 0,
52 .flags = IORESOURCE_IRQ,
53 },
54};
55
56/* DMA not used; works around erratum writing to non-empty i2c fifo */
57
58static struct platform_device omap_i2c_device1 = {
59 .name = "i2c_omap",
60 .id = 1,
61 .dev = {
62 .release = omap_nop_release,
63 },
64 .num_resources = ARRAY_SIZE(i2c_resources1),
65 .resource = i2c_resources1,
66};
67
68/* See also arch/arm/mach-omap2/devices.c for second I2C on 24xx */
69static void omap_init_i2c(void)
70{
71 if (cpu_is_omap24xx()) {
72 i2c_resources1[0].start = OMAP2_I2C_BASE1;
73 i2c_resources1[0].end = OMAP2_I2C_BASE1 + OMAP_I2C_SIZE;
74 i2c_resources1[1].start = OMAP2_I2C_INT1;
75 } else {
76 i2c_resources1[0].start = OMAP1_I2C_BASE;
77 i2c_resources1[0].end = OMAP1_I2C_BASE + OMAP_I2C_SIZE;
78 i2c_resources1[1].start = OMAP1_I2C_INT;
79 }
80
81 /* FIXME define and use a boot tag, in case of boards that
82 * either don't wire up I2C, or chips that mux it differently...
83 * it can include clocking and address info, maybe more.
84 */
85 if (cpu_is_omap24xx()) {
86 omap_cfg_reg(M19_24XX_I2C1_SCL);
87 omap_cfg_reg(L15_24XX_I2C1_SDA);
88 } else {
89 omap_cfg_reg(I2C_SCL);
90 omap_cfg_reg(I2C_SDA);
91 }
92
93 (void) platform_device_register(&omap_i2c_device1);
94}
95
96#else
97static inline void omap_init_i2c(void) {}
98#endif
99
100/*-------------------------------------------------------------------------*/
101
102#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
103
104#ifdef CONFIG_ARCH_OMAP24XX
105#define OMAP_MMC1_BASE 0x4809c000
106#define OMAP_MMC1_INT 83
107#else
108#define OMAP_MMC1_BASE 0xfffb7800
109#define OMAP_MMC1_INT INT_MMC
110#endif
111#define OMAP_MMC2_BASE 0xfffb7c00 /* omap16xx only */
112
113static struct omap_mmc_conf mmc1_conf;
114
115static u64 mmc1_dmamask = 0xffffffff;
116
117static struct resource mmc1_resources[] = {
118 {
119 .start = IO_ADDRESS(OMAP_MMC1_BASE),
120 .end = IO_ADDRESS(OMAP_MMC1_BASE) + 0x7f,
121 .flags = IORESOURCE_MEM,
122 },
123 {
124 .start = OMAP_MMC1_INT,
125 .flags = IORESOURCE_IRQ,
126 },
127};
128
129static struct platform_device mmc_omap_device1 = {
130 .name = "mmci-omap",
131 .id = 1,
132 .dev = {
133 .release = omap_nop_release,
134 .dma_mask = &mmc1_dmamask,
135 .platform_data = &mmc1_conf,
136 },
137 .num_resources = ARRAY_SIZE(mmc1_resources),
138 .resource = mmc1_resources,
139};
140
141#ifdef CONFIG_ARCH_OMAP16XX
142
143static struct omap_mmc_conf mmc2_conf;
144
145static u64 mmc2_dmamask = 0xffffffff;
146
147static struct resource mmc2_resources[] = {
148 {
149 .start = IO_ADDRESS(OMAP_MMC2_BASE),
150 .end = IO_ADDRESS(OMAP_MMC2_BASE) + 0x7f,
151 .flags = IORESOURCE_MEM,
152 },
153 {
154 .start = INT_1610_MMC2,
155 .flags = IORESOURCE_IRQ,
156 },
157};
158
159static struct platform_device mmc_omap_device2 = {
160 .name = "mmci-omap",
161 .id = 2,
162 .dev = {
163 .release = omap_nop_release,
164 .dma_mask = &mmc2_dmamask,
165 .platform_data = &mmc2_conf,
166 },
167 .num_resources = ARRAY_SIZE(mmc2_resources),
168 .resource = mmc2_resources,
169};
170#endif
171
172static void __init omap_init_mmc(void)
173{
174 const struct omap_mmc_config *mmc_conf;
175 const struct omap_mmc_conf *mmc;
176
177 /* NOTE: assumes MMC was never (wrongly) enabled */
178 mmc_conf = omap_get_config(OMAP_TAG_MMC, struct omap_mmc_config);
179 if (!mmc_conf)
180 return;
181
182 /* block 1 is always available and has just one pinout option */
183 mmc = &mmc_conf->mmc[0];
184 if (mmc->enabled) {
185 if (!cpu_is_omap24xx()) {
186 omap_cfg_reg(MMC_CMD);
187 omap_cfg_reg(MMC_CLK);
188 omap_cfg_reg(MMC_DAT0);
189 if (cpu_is_omap1710()) {
190 omap_cfg_reg(M15_1710_MMC_CLKI);
191 omap_cfg_reg(P19_1710_MMC_CMDDIR);
192 omap_cfg_reg(P20_1710_MMC_DATDIR0);
193 }
194 }
195 if (mmc->wire4) {
196 if (!cpu_is_omap24xx()) {
197 omap_cfg_reg(MMC_DAT1);
198 /* NOTE: DAT2 can be on W10 (here) or M15 */
199 if (!mmc->nomux)
200 omap_cfg_reg(MMC_DAT2);
201 omap_cfg_reg(MMC_DAT3);
202 }
203 }
204 mmc1_conf = *mmc;
205 (void) platform_device_register(&mmc_omap_device1);
206 }
207
208#ifdef CONFIG_ARCH_OMAP16XX
209 /* block 2 is on newer chips, and has many pinout options */
210 mmc = &mmc_conf->mmc[1];
211 if (mmc->enabled) {
212 if (!mmc->nomux) {
213 omap_cfg_reg(Y8_1610_MMC2_CMD);
214 omap_cfg_reg(Y10_1610_MMC2_CLK);
215 omap_cfg_reg(R18_1610_MMC2_CLKIN);
216 omap_cfg_reg(W8_1610_MMC2_DAT0);
217 if (mmc->wire4) {
218 omap_cfg_reg(V8_1610_MMC2_DAT1);
219 omap_cfg_reg(W15_1610_MMC2_DAT2);
220 omap_cfg_reg(R10_1610_MMC2_DAT3);
221 }
222
223 /* These are needed for the level shifter */
224 omap_cfg_reg(V9_1610_MMC2_CMDDIR);
225 omap_cfg_reg(V5_1610_MMC2_DATDIR0);
226 omap_cfg_reg(W19_1610_MMC2_DATDIR1);
227 }
228
229 /* Feedback clock must be set on OMAP-1710 MMC2 */
230 if (cpu_is_omap1710())
231 omap_writel(omap_readl(MOD_CONF_CTRL_1) | (1 << 24),
232 MOD_CONF_CTRL_1);
233 mmc2_conf = *mmc;
234 (void) platform_device_register(&mmc_omap_device2);
235 }
236#endif
237 return;
238}
239#else
240static inline void omap_init_mmc(void) {}
241#endif
242
243#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
244
245#ifdef CONFIG_ARCH_OMAP24XX
246#define OMAP_WDT_BASE 0x48022000
247#else
248#define OMAP_WDT_BASE 0xfffeb000
249#endif
250
251static struct resource wdt_resources[] = {
252 {
253 .start = OMAP_WDT_BASE,
254 .end = OMAP_WDT_BASE + 0x4f,
255 .flags = IORESOURCE_MEM,
256 },
257};
258
259static struct platform_device omap_wdt_device = {
260 .name = "omap_wdt",
261 .id = -1,
262 .dev = {
263 .release = omap_nop_release,
264 },
265 .num_resources = ARRAY_SIZE(wdt_resources),
266 .resource = wdt_resources,
267};
268
269static void omap_init_wdt(void)
270{
271 (void) platform_device_register(&omap_wdt_device);
272}
273#else
274static inline void omap_init_wdt(void) {}
275#endif
276
277/*-------------------------------------------------------------------------*/
278
279#if defined(CONFIG_OMAP_RNG) || defined(CONFIG_OMAP_RNG_MODULE)
280
281#ifdef CONFIG_ARCH_OMAP24XX
282#define OMAP_RNG_BASE 0x480A0000
283#else
284#define OMAP_RNG_BASE 0xfffe5000
285#endif
286
287static struct resource rng_resources[] = {
288 {
289 .start = OMAP_RNG_BASE,
290 .end = OMAP_RNG_BASE + 0x4f,
291 .flags = IORESOURCE_MEM,
292 },
293};
294
295static struct platform_device omap_rng_device = {
296 .name = "omap_rng",
297 .id = -1,
298 .dev = {
299 .release = omap_nop_release,
300 },
301 .num_resources = ARRAY_SIZE(rng_resources),
302 .resource = rng_resources,
303};
304
305static void omap_init_rng(void)
306{
307 (void) platform_device_register(&omap_rng_device);
308}
309#else
310static inline void omap_init_rng(void) {}
311#endif
312
313#if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
314
315static struct omap_lcd_config omap_fb_conf;
316
317static u64 omap_fb_dma_mask = ~(u32)0;
318
319static struct platform_device omap_fb_device = {
320 .name = "omapfb",
321 .id = -1,
322 .dev = {
323 .release = omap_nop_release,
324 .dma_mask = &omap_fb_dma_mask,
325 .coherent_dma_mask = ~(u32)0,
326 .platform_data = &omap_fb_conf,
327 },
328 .num_resources = 0,
329};
330
331static inline void omap_init_fb(void)
332{
333 const struct omap_lcd_config *conf;
334
335 conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config);
336 if (conf != NULL)
337 omap_fb_conf = *conf;
338 platform_device_register(&omap_fb_device);
339}
340
341#else
342
343static inline void omap_init_fb(void) {}
344
345#endif
346
347/*
348 * This gets called after board-specific INIT_MACHINE, and initializes most
349 * on-chip peripherals accessible on this board (except for few like USB):
350 *
351 * (a) Does any "standard config" pin muxing needed. Board-specific
352 * code will have muxed GPIO pins and done "nonstandard" setup;
353 * that code could live in the boot loader.
354 * (b) Populating board-specific platform_data with the data drivers
355 * rely on to handle wiring variations.
356 * (c) Creating platform devices as meaningful on this board and
357 * with this kernel configuration.
358 *
359 * Claiming GPIOs, and setting their direction and initial values, is the
360 * responsibility of the device drivers. So is responding to probe().
361 *
362 * Board-specific knowlege like creating devices or pin setup is to be
363 * kept out of drivers as much as possible. In particular, pin setup
364 * may be handled by the boot loader, and drivers should expect it will
365 * normally have been done by the time they're probed.
366 */
367static int __init omap_init_devices(void)
368{
369 /* please keep these calls, and their implementations above,
370 * in alphabetical order so they're easier to sort through.
371 */
372 omap_init_fb();
373 omap_init_i2c();
374 omap_init_mmc();
375 omap_init_wdt();
376 omap_init_rng();
377
378 return 0;
379}
380arch_initcall(omap_init_devices);
381
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index da7b65145658..f5cc21ad0956 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -6,6 +6,8 @@
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> 6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations 7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com> 8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2 support Copyright (C) 2004-2005 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
9 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. 11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
10 * 12 *
11 * Support functions for the OMAP internal DMA channels. 13 * Support functions for the OMAP internal DMA channels.
@@ -31,8 +33,15 @@
31 33
32#include <asm/arch/tc.h> 34#include <asm/arch/tc.h>
33 35
34#define OMAP_DMA_ACTIVE 0x01 36#define DEBUG_PRINTS
37#undef DEBUG_PRINTS
38#ifdef DEBUG_PRINTS
39#define debug_printk(x) printk x
40#else
41#define debug_printk(x)
42#endif
35 43
44#define OMAP_DMA_ACTIVE 0x01
36#define OMAP_DMA_CCR_EN (1 << 7) 45#define OMAP_DMA_CCR_EN (1 << 7)
37 46
38#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) 47#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
@@ -55,7 +64,7 @@ static int dma_chan_count;
55static spinlock_t dma_chan_lock; 64static spinlock_t dma_chan_lock;
56static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT]; 65static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT];
57 66
58const static u8 dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = { 67const static u8 omap1_dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
59 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3, 68 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
60 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7, 69 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
61 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10, 70 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
@@ -63,6 +72,20 @@ const static u8 dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
63 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD 72 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
64}; 73};
65 74
75#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
76 __FUNCTION__);
77
78#ifdef CONFIG_ARCH_OMAP15XX
79/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
80int omap_dma_in_1510_mode(void)
81{
82 return enable_1510_mode;
83}
84#else
85#define omap_dma_in_1510_mode() 0
86#endif
87
88#ifdef CONFIG_ARCH_OMAP1
66static inline int get_gdma_dev(int req) 89static inline int get_gdma_dev(int req)
67{ 90{
68 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; 91 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
@@ -82,6 +105,9 @@ static inline void set_gdma_dev(int req, int dev)
82 l |= (dev - 1) << shift; 105 l |= (dev - 1) << shift;
83 omap_writel(l, reg); 106 omap_writel(l, reg);
84} 107}
108#else
109#define set_gdma_dev(req, dev) do {} while (0)
110#endif
85 111
86static void clear_lch_regs(int lch) 112static void clear_lch_regs(int lch)
87{ 113{
@@ -121,38 +147,62 @@ void omap_set_dma_priority(int dst_port, int priority)
121} 147}
122 148
123void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, 149void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
124 int frame_count, int sync_mode) 150 int frame_count, int sync_mode,
151 int dma_trigger, int src_or_dst_synch)
125{ 152{
126 u16 w; 153 OMAP_DMA_CSDP_REG(lch) &= ~0x03;
154 OMAP_DMA_CSDP_REG(lch) |= data_type;
127 155
128 w = omap_readw(OMAP_DMA_CSDP(lch)); 156 if (cpu_class_is_omap1()) {
129 w &= ~0x03; 157 OMAP_DMA_CCR_REG(lch) &= ~(1 << 5);
130 w |= data_type; 158 if (sync_mode == OMAP_DMA_SYNC_FRAME)
131 omap_writew(w, OMAP_DMA_CSDP(lch)); 159 OMAP_DMA_CCR_REG(lch) |= 1 << 5;
160
161 OMAP1_DMA_CCR2_REG(lch) &= ~(1 << 2);
162 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
163 OMAP1_DMA_CCR2_REG(lch) |= 1 << 2;
164 }
165
166 if (cpu_is_omap24xx() && dma_trigger) {
167 u32 val = OMAP_DMA_CCR_REG(lch);
168
169 if (dma_trigger > 63)
170 val |= 1 << 20;
171 if (dma_trigger > 31)
172 val |= 1 << 19;
132 173
133 w = omap_readw(OMAP_DMA_CCR(lch)); 174 val |= (dma_trigger & 0x1f);
134 w &= ~(1 << 5);
135 if (sync_mode == OMAP_DMA_SYNC_FRAME)
136 w |= 1 << 5;
137 omap_writew(w, OMAP_DMA_CCR(lch));
138 175
139 w = omap_readw(OMAP_DMA_CCR2(lch)); 176 if (sync_mode & OMAP_DMA_SYNC_FRAME)
140 w &= ~(1 << 2); 177 val |= 1 << 5;
141 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
142 w |= 1 << 2;
143 omap_writew(w, OMAP_DMA_CCR2(lch));
144 178
145 omap_writew(elem_count, OMAP_DMA_CEN(lch)); 179 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
146 omap_writew(frame_count, OMAP_DMA_CFN(lch)); 180 val |= 1 << 18;
147 181
182 if (src_or_dst_synch)
183 val |= 1 << 24; /* source synch */
184 else
185 val &= ~(1 << 24); /* dest synch */
186
187 OMAP_DMA_CCR_REG(lch) = val;
188 }
189
190 OMAP_DMA_CEN_REG(lch) = elem_count;
191 OMAP_DMA_CFN_REG(lch) = frame_count;
148} 192}
193
149void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) 194void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
150{ 195{
151 u16 w; 196 u16 w;
152 197
153 BUG_ON(omap_dma_in_1510_mode()); 198 BUG_ON(omap_dma_in_1510_mode());
154 199
155 w = omap_readw(OMAP_DMA_CCR2(lch)) & ~0x03; 200 if (cpu_is_omap24xx()) {
201 REVISIT_24XX();
202 return;
203 }
204
205 w = OMAP1_DMA_CCR2_REG(lch) & ~0x03;
156 switch (mode) { 206 switch (mode) {
157 case OMAP_DMA_CONSTANT_FILL: 207 case OMAP_DMA_CONSTANT_FILL:
158 w |= 0x01; 208 w |= 0x01;
@@ -165,63 +215,84 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
165 default: 215 default:
166 BUG(); 216 BUG();
167 } 217 }
168 omap_writew(w, OMAP_DMA_CCR2(lch)); 218 OMAP1_DMA_CCR2_REG(lch) = w;
169 219
170 w = omap_readw(OMAP_DMA_LCH_CTRL(lch)) & ~0x0f; 220 w = OMAP1_DMA_LCH_CTRL_REG(lch) & ~0x0f;
171 /* Default is channel type 2D */ 221 /* Default is channel type 2D */
172 if (mode) { 222 if (mode) {
173 omap_writew((u16)color, OMAP_DMA_COLOR_L(lch)); 223 OMAP1_DMA_COLOR_L_REG(lch) = (u16)color;
174 omap_writew((u16)(color >> 16), OMAP_DMA_COLOR_U(lch)); 224 OMAP1_DMA_COLOR_U_REG(lch) = (u16)(color >> 16);
175 w |= 1; /* Channel type G */ 225 w |= 1; /* Channel type G */
176 } 226 }
177 omap_writew(w, OMAP_DMA_LCH_CTRL(lch)); 227 OMAP1_DMA_LCH_CTRL_REG(lch) = w;
178} 228}
179 229
180 230/* Note that src_port is only for omap1 */
181void omap_set_dma_src_params(int lch, int src_port, int src_amode, 231void omap_set_dma_src_params(int lch, int src_port, int src_amode,
182 unsigned long src_start) 232 unsigned long src_start,
233 int src_ei, int src_fi)
183{ 234{
184 u16 w; 235 if (cpu_class_is_omap1()) {
236 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 2);
237 OMAP_DMA_CSDP_REG(lch) |= src_port << 2;
238 }
239
240 OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 12);
241 OMAP_DMA_CCR_REG(lch) |= src_amode << 12;
242
243 if (cpu_class_is_omap1()) {
244 OMAP1_DMA_CSSA_U_REG(lch) = src_start >> 16;
245 OMAP1_DMA_CSSA_L_REG(lch) = src_start;
246 }
185 247
186 w = omap_readw(OMAP_DMA_CSDP(lch)); 248 if (cpu_is_omap24xx())
187 w &= ~(0x1f << 2); 249 OMAP2_DMA_CSSA_REG(lch) = src_start;
188 w |= src_port << 2;
189 omap_writew(w, OMAP_DMA_CSDP(lch));
190 250
191 w = omap_readw(OMAP_DMA_CCR(lch)); 251 OMAP_DMA_CSEI_REG(lch) = src_ei;
192 w &= ~(0x03 << 12); 252 OMAP_DMA_CSFI_REG(lch) = src_fi;
193 w |= src_amode << 12; 253}
194 omap_writew(w, OMAP_DMA_CCR(lch));
195 254
196 omap_writew(src_start >> 16, OMAP_DMA_CSSA_U(lch)); 255void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
197 omap_writew(src_start, OMAP_DMA_CSSA_L(lch)); 256{
257 omap_set_dma_transfer_params(lch, params->data_type,
258 params->elem_count, params->frame_count,
259 params->sync_mode, params->trigger,
260 params->src_or_dst_synch);
261 omap_set_dma_src_params(lch, params->src_port,
262 params->src_amode, params->src_start,
263 params->src_ei, params->src_fi);
264
265 omap_set_dma_dest_params(lch, params->dst_port,
266 params->dst_amode, params->dst_start,
267 params->dst_ei, params->dst_fi);
198} 268}
199 269
200void omap_set_dma_src_index(int lch, int eidx, int fidx) 270void omap_set_dma_src_index(int lch, int eidx, int fidx)
201{ 271{
202 omap_writew(eidx, OMAP_DMA_CSEI(lch)); 272 if (cpu_is_omap24xx()) {
203 omap_writew(fidx, OMAP_DMA_CSFI(lch)); 273 REVISIT_24XX();
274 return;
275 }
276 OMAP_DMA_CSEI_REG(lch) = eidx;
277 OMAP_DMA_CSFI_REG(lch) = fidx;
204} 278}
205 279
206void omap_set_dma_src_data_pack(int lch, int enable) 280void omap_set_dma_src_data_pack(int lch, int enable)
207{ 281{
208 u16 w; 282 OMAP_DMA_CSDP_REG(lch) &= ~(1 << 6);
209 283 if (enable)
210 w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(1 << 6); 284 OMAP_DMA_CSDP_REG(lch) |= (1 << 6);
211 w |= enable ? (1 << 6) : 0;
212 omap_writew(w, OMAP_DMA_CSDP(lch));
213} 285}
214 286
215void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) 287void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
216{ 288{
217 u16 w; 289 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7);
218 290
219 w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(0x03 << 7);
220 switch (burst_mode) { 291 switch (burst_mode) {
221 case OMAP_DMA_DATA_BURST_DIS: 292 case OMAP_DMA_DATA_BURST_DIS:
222 break; 293 break;
223 case OMAP_DMA_DATA_BURST_4: 294 case OMAP_DMA_DATA_BURST_4:
224 w |= (0x01 << 7); 295 OMAP_DMA_CSDP_REG(lch) |= (0x02 << 7);
225 break; 296 break;
226 case OMAP_DMA_DATA_BURST_8: 297 case OMAP_DMA_DATA_BURST_8:
227 /* not supported by current hardware 298 /* not supported by current hardware
@@ -231,110 +302,283 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
231 default: 302 default:
232 BUG(); 303 BUG();
233 } 304 }
234 omap_writew(w, OMAP_DMA_CSDP(lch));
235} 305}
236 306
307/* Note that dest_port is only for OMAP1 */
237void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, 308void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
238 unsigned long dest_start) 309 unsigned long dest_start,
310 int dst_ei, int dst_fi)
239{ 311{
240 u16 w; 312 if (cpu_class_is_omap1()) {
313 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 9);
314 OMAP_DMA_CSDP_REG(lch) |= dest_port << 9;
315 }
241 316
242 w = omap_readw(OMAP_DMA_CSDP(lch)); 317 OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 14);
243 w &= ~(0x1f << 9); 318 OMAP_DMA_CCR_REG(lch) |= dest_amode << 14;
244 w |= dest_port << 9; 319
245 omap_writew(w, OMAP_DMA_CSDP(lch)); 320 if (cpu_class_is_omap1()) {
321 OMAP1_DMA_CDSA_U_REG(lch) = dest_start >> 16;
322 OMAP1_DMA_CDSA_L_REG(lch) = dest_start;
323 }
246 324
247 w = omap_readw(OMAP_DMA_CCR(lch)); 325 if (cpu_is_omap24xx())
248 w &= ~(0x03 << 14); 326 OMAP2_DMA_CDSA_REG(lch) = dest_start;
249 w |= dest_amode << 14;
250 omap_writew(w, OMAP_DMA_CCR(lch));
251 327
252 omap_writew(dest_start >> 16, OMAP_DMA_CDSA_U(lch)); 328 OMAP_DMA_CDEI_REG(lch) = dst_ei;
253 omap_writew(dest_start, OMAP_DMA_CDSA_L(lch)); 329 OMAP_DMA_CDFI_REG(lch) = dst_fi;
254} 330}
255 331
256void omap_set_dma_dest_index(int lch, int eidx, int fidx) 332void omap_set_dma_dest_index(int lch, int eidx, int fidx)
257{ 333{
258 omap_writew(eidx, OMAP_DMA_CDEI(lch)); 334 if (cpu_is_omap24xx()) {
259 omap_writew(fidx, OMAP_DMA_CDFI(lch)); 335 REVISIT_24XX();
336 return;
337 }
338 OMAP_DMA_CDEI_REG(lch) = eidx;
339 OMAP_DMA_CDFI_REG(lch) = fidx;
260} 340}
261 341
262void omap_set_dma_dest_data_pack(int lch, int enable) 342void omap_set_dma_dest_data_pack(int lch, int enable)
263{ 343{
264 u16 w; 344 OMAP_DMA_CSDP_REG(lch) &= ~(1 << 13);
265 345 if (enable)
266 w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(1 << 13); 346 OMAP_DMA_CSDP_REG(lch) |= 1 << 13;
267 w |= enable ? (1 << 13) : 0;
268 omap_writew(w, OMAP_DMA_CSDP(lch));
269} 347}
270 348
271void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) 349void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
272{ 350{
273 u16 w; 351 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14);
274 352
275 w = omap_readw(OMAP_DMA_CSDP(lch)) & ~(0x03 << 14);
276 switch (burst_mode) { 353 switch (burst_mode) {
277 case OMAP_DMA_DATA_BURST_DIS: 354 case OMAP_DMA_DATA_BURST_DIS:
278 break; 355 break;
279 case OMAP_DMA_DATA_BURST_4: 356 case OMAP_DMA_DATA_BURST_4:
280 w |= (0x01 << 14); 357 OMAP_DMA_CSDP_REG(lch) |= (0x02 << 14);
281 break; 358 break;
282 case OMAP_DMA_DATA_BURST_8: 359 case OMAP_DMA_DATA_BURST_8:
283 w |= (0x03 << 14); 360 OMAP_DMA_CSDP_REG(lch) |= (0x03 << 14);
284 break; 361 break;
285 default: 362 default:
286 printk(KERN_ERR "Invalid DMA burst mode\n"); 363 printk(KERN_ERR "Invalid DMA burst mode\n");
287 BUG(); 364 BUG();
288 return; 365 return;
289 } 366 }
290 omap_writew(w, OMAP_DMA_CSDP(lch));
291} 367}
292 368
293static inline void init_intr(int lch) 369static inline void omap_enable_channel_irq(int lch)
294{ 370{
295 u16 w; 371 u32 status;
296 372
297 /* Read CSR to make sure it's cleared. */ 373 /* Read CSR to make sure it's cleared. */
298 w = omap_readw(OMAP_DMA_CSR(lch)); 374 status = OMAP_DMA_CSR_REG(lch);
375
299 /* Enable some nice interrupts. */ 376 /* Enable some nice interrupts. */
300 omap_writew(dma_chan[lch].enabled_irqs, OMAP_DMA_CICR(lch)); 377 OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs;
378
301 dma_chan[lch].flags |= OMAP_DMA_ACTIVE; 379 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
302} 380}
303 381
304static inline void enable_lnk(int lch) 382static void omap_disable_channel_irq(int lch)
305{ 383{
306 u16 w; 384 if (cpu_is_omap24xx())
385 OMAP_DMA_CICR_REG(lch) = 0;
386}
387
388void omap_enable_dma_irq(int lch, u16 bits)
389{
390 dma_chan[lch].enabled_irqs |= bits;
391}
307 392
308 /* Clear the STOP_LNK bits */ 393void omap_disable_dma_irq(int lch, u16 bits)
309 w = omap_readw(OMAP_DMA_CLNK_CTRL(lch)); 394{
310 w &= ~(1 << 14); 395 dma_chan[lch].enabled_irqs &= ~bits;
311 omap_writew(w, OMAP_DMA_CLNK_CTRL(lch)); 396}
397
398static inline void enable_lnk(int lch)
399{
400 if (cpu_class_is_omap1())
401 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 14);
312 402
313 /* And set the ENABLE_LNK bits */ 403 /* Set the ENABLE_LNK bits */
314 if (dma_chan[lch].next_lch != -1) 404 if (dma_chan[lch].next_lch != -1)
315 omap_writew(dma_chan[lch].next_lch | (1 << 15), 405 OMAP_DMA_CLNK_CTRL_REG(lch) =
316 OMAP_DMA_CLNK_CTRL(lch)); 406 dma_chan[lch].next_lch | (1 << 15);
317} 407}
318 408
319static inline void disable_lnk(int lch) 409static inline void disable_lnk(int lch)
320{ 410{
321 u16 w;
322
323 /* Disable interrupts */ 411 /* Disable interrupts */
324 omap_writew(0, OMAP_DMA_CICR(lch)); 412 if (cpu_class_is_omap1()) {
413 OMAP_DMA_CICR_REG(lch) = 0;
414 /* Set the STOP_LNK bit */
415 OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14;
416 }
325 417
326 /* Set the STOP_LNK bit */ 418 if (cpu_is_omap24xx()) {
327 w = omap_readw(OMAP_DMA_CLNK_CTRL(lch)); 419 omap_disable_channel_irq(lch);
328 w |= (1 << 14); 420 /* Clear the ENABLE_LNK bit */
329 w = omap_writew(w, OMAP_DMA_CLNK_CTRL(lch)); 421 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15);
422 }
330 423
331 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; 424 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
332} 425}
333 426
334void omap_start_dma(int lch) 427static inline void omap2_enable_irq_lch(int lch)
335{ 428{
336 u16 w; 429 u32 val;
430
431 if (!cpu_is_omap24xx())
432 return;
433
434 val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
435 val |= 1 << lch;
436 omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
437}
438
439int omap_request_dma(int dev_id, const char *dev_name,
440 void (* callback)(int lch, u16 ch_status, void *data),
441 void *data, int *dma_ch_out)
442{
443 int ch, free_ch = -1;
444 unsigned long flags;
445 struct omap_dma_lch *chan;
446
447 spin_lock_irqsave(&dma_chan_lock, flags);
448 for (ch = 0; ch < dma_chan_count; ch++) {
449 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
450 free_ch = ch;
451 if (dev_id == 0)
452 break;
453 }
454 }
455 if (free_ch == -1) {
456 spin_unlock_irqrestore(&dma_chan_lock, flags);
457 return -EBUSY;
458 }
459 chan = dma_chan + free_ch;
460 chan->dev_id = dev_id;
461
462 if (cpu_class_is_omap1())
463 clear_lch_regs(free_ch);
337 464
465 if (cpu_is_omap24xx())
466 omap_clear_dma(free_ch);
467
468 spin_unlock_irqrestore(&dma_chan_lock, flags);
469
470 chan->dev_name = dev_name;
471 chan->callback = callback;
472 chan->data = data;
473 chan->enabled_irqs = OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ |
474 OMAP_DMA_BLOCK_IRQ;
475
476 if (cpu_is_omap24xx())
477 chan->enabled_irqs |= OMAP2_DMA_TRANS_ERR_IRQ;
478
479 if (cpu_is_omap16xx()) {
480 /* If the sync device is set, configure it dynamically. */
481 if (dev_id != 0) {
482 set_gdma_dev(free_ch + 1, dev_id);
483 dev_id = free_ch + 1;
484 }
485 /* Disable the 1510 compatibility mode and set the sync device
486 * id. */
487 OMAP_DMA_CCR_REG(free_ch) = dev_id | (1 << 10);
488 } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
489 OMAP_DMA_CCR_REG(free_ch) = dev_id;
490 }
491
492 if (cpu_is_omap24xx()) {
493 omap2_enable_irq_lch(free_ch);
494
495 omap_enable_channel_irq(free_ch);
496 /* Clear the CSR register and IRQ status register */
497 OMAP_DMA_CSR_REG(free_ch) = 0x0;
498 omap_writel(~0x0, OMAP_DMA4_IRQSTATUS_L0);
499 }
500
501 *dma_ch_out = free_ch;
502
503 return 0;
504}
505
506void omap_free_dma(int lch)
507{
508 unsigned long flags;
509
510 spin_lock_irqsave(&dma_chan_lock, flags);
511 if (dma_chan[lch].dev_id == -1) {
512 printk("omap_dma: trying to free nonallocated DMA channel %d\n",
513 lch);
514 spin_unlock_irqrestore(&dma_chan_lock, flags);
515 return;
516 }
517 dma_chan[lch].dev_id = -1;
518 dma_chan[lch].next_lch = -1;
519 dma_chan[lch].callback = NULL;
520 spin_unlock_irqrestore(&dma_chan_lock, flags);
521
522 if (cpu_class_is_omap1()) {
523 /* Disable all DMA interrupts for the channel. */
524 OMAP_DMA_CICR_REG(lch) = 0;
525 /* Make sure the DMA transfer is stopped. */
526 OMAP_DMA_CCR_REG(lch) = 0;
527 }
528
529 if (cpu_is_omap24xx()) {
530 u32 val;
531 /* Disable interrupts */
532 val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
533 val &= ~(1 << lch);
534 omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
535
536 /* Clear the CSR register and IRQ status register */
537 OMAP_DMA_CSR_REG(lch) = 0x0;
538
539 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
540 val |= 1 << lch;
541 omap_writel(val, OMAP_DMA4_IRQSTATUS_L0);
542
543 /* Disable all DMA interrupts for the channel. */
544 OMAP_DMA_CICR_REG(lch) = 0;
545
546 /* Make sure the DMA transfer is stopped. */
547 OMAP_DMA_CCR_REG(lch) = 0;
548 omap_clear_dma(lch);
549 }
550}
551
552/*
553 * Clears any DMA state so the DMA engine is ready to restart with new buffers
554 * through omap_start_dma(). Any buffers in flight are discarded.
555 */
556void omap_clear_dma(int lch)
557{
558 unsigned long flags;
559
560 local_irq_save(flags);
561
562 if (cpu_class_is_omap1()) {
563 int status;
564 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
565
566 /* Clear pending interrupts */
567 status = OMAP_DMA_CSR_REG(lch);
568 }
569
570 if (cpu_is_omap24xx()) {
571 int i;
572 u32 lch_base = OMAP24XX_DMA_BASE + lch * 0x60 + 0x80;
573 for (i = 0; i < 0x44; i += 4)
574 omap_writel(0, lch_base + i);
575 }
576
577 local_irq_restore(flags);
578}
579
580void omap_start_dma(int lch)
581{
338 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { 582 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
339 int next_lch, cur_lch; 583 int next_lch, cur_lch;
340 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT]; 584 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
@@ -348,31 +592,37 @@ void omap_start_dma(int lch)
348 do { 592 do {
349 next_lch = dma_chan[cur_lch].next_lch; 593 next_lch = dma_chan[cur_lch].next_lch;
350 594
351 /* The loop case: we've been here already */ 595 /* The loop case: we've been here already */
352 if (dma_chan_link_map[cur_lch]) 596 if (dma_chan_link_map[cur_lch])
353 break; 597 break;
354 /* Mark the current channel */ 598 /* Mark the current channel */
355 dma_chan_link_map[cur_lch] = 1; 599 dma_chan_link_map[cur_lch] = 1;
356 600
357 enable_lnk(cur_lch); 601 enable_lnk(cur_lch);
358 init_intr(cur_lch); 602 omap_enable_channel_irq(cur_lch);
359 603
360 cur_lch = next_lch; 604 cur_lch = next_lch;
361 } while (next_lch != -1); 605 } while (next_lch != -1);
606 } else if (cpu_is_omap24xx()) {
607 /* Errata: Need to write lch even if not using chaining */
608 OMAP_DMA_CLNK_CTRL_REG(lch) = lch;
362 } 609 }
363 610
364 init_intr(lch); 611 omap_enable_channel_irq(lch);
612
613 /* Errata: On ES2.0 BUFFERING disable must be set.
614 * This will always fail on ES1.0 */
615 if (cpu_is_omap24xx()) {
616 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
617 }
618
619 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
365 620
366 w = omap_readw(OMAP_DMA_CCR(lch));
367 w |= OMAP_DMA_CCR_EN;
368 omap_writew(w, OMAP_DMA_CCR(lch));
369 dma_chan[lch].flags |= OMAP_DMA_ACTIVE; 621 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
370} 622}
371 623
372void omap_stop_dma(int lch) 624void omap_stop_dma(int lch)
373{ 625{
374 u16 w;
375
376 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { 626 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
377 int next_lch, cur_lch = lch; 627 int next_lch, cur_lch = lch;
378 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT]; 628 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
@@ -393,146 +643,83 @@ void omap_stop_dma(int lch)
393 643
394 return; 644 return;
395 } 645 }
646
396 /* Disable all interrupts on the channel */ 647 /* Disable all interrupts on the channel */
397 omap_writew(0, OMAP_DMA_CICR(lch)); 648 if (cpu_class_is_omap1())
649 OMAP_DMA_CICR_REG(lch) = 0;
398 650
399 w = omap_readw(OMAP_DMA_CCR(lch)); 651 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
400 w &= ~OMAP_DMA_CCR_EN;
401 omap_writew(w, OMAP_DMA_CCR(lch));
402 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; 652 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
403} 653}
404 654
405void omap_enable_dma_irq(int lch, u16 bits) 655/*
656 * Returns current physical source address for the given DMA channel.
657 * If the channel is running the caller must disable interrupts prior calling
658 * this function and process the returned value before re-enabling interrupt to
659 * prevent races with the interrupt handler. Note that in continuous mode there
660 * is a chance for CSSA_L register overflow inbetween the two reads resulting
661 * in incorrect return value.
662 */
663dma_addr_t omap_get_dma_src_pos(int lch)
406{ 664{
407 dma_chan[lch].enabled_irqs |= bits; 665 dma_addr_t offset;
408}
409 666
410void omap_disable_dma_irq(int lch, u16 bits) 667 if (cpu_class_is_omap1())
411{ 668 offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) |
412 dma_chan[lch].enabled_irqs &= ~bits; 669 (OMAP1_DMA_CSSA_U_REG(lch) << 16));
413}
414 670
415static int dma_handle_ch(int ch) 671 if (cpu_is_omap24xx())
416{ 672 offset = OMAP_DMA_CSAC_REG(lch);
417 u16 csr;
418 673
419 if (enable_1510_mode && ch >= 6) { 674 return offset;
420 csr = dma_chan[ch].saved_csr;
421 dma_chan[ch].saved_csr = 0;
422 } else
423 csr = omap_readw(OMAP_DMA_CSR(ch));
424 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
425 dma_chan[ch + 6].saved_csr = csr >> 7;
426 csr &= 0x7f;
427 }
428 if ((csr & 0x3f) == 0)
429 return 0;
430 if (unlikely(dma_chan[ch].dev_id == -1)) {
431 printk(KERN_WARNING "Spurious interrupt from DMA channel %d (CSR %04x)\n",
432 ch, csr);
433 return 0;
434 }
435 if (unlikely(csr & OMAP_DMA_TOUT_IRQ))
436 printk(KERN_WARNING "DMA timeout with device %d\n", dma_chan[ch].dev_id);
437 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
438 printk(KERN_WARNING "DMA synchronization event drop occurred with device %d\n",
439 dma_chan[ch].dev_id);
440 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
441 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
442 if (likely(dma_chan[ch].callback != NULL))
443 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
444 return 1;
445} 675}
446 676
447static irqreturn_t dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs) 677/*
678 * Returns current physical destination address for the given DMA channel.
679 * If the channel is running the caller must disable interrupts prior calling
680 * this function and process the returned value before re-enabling interrupt to
681 * prevent races with the interrupt handler. Note that in continuous mode there
682 * is a chance for CDSA_L register overflow inbetween the two reads resulting
683 * in incorrect return value.
684 */
685dma_addr_t omap_get_dma_dst_pos(int lch)
448{ 686{
449 int ch = ((int) dev_id) - 1; 687 dma_addr_t offset;
450 int handled = 0;
451 688
452 for (;;) { 689 if (cpu_class_is_omap1())
453 int handled_now = 0; 690 offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) |
691 (OMAP1_DMA_CDSA_U_REG(lch) << 16));
454 692
455 handled_now += dma_handle_ch(ch); 693 if (cpu_is_omap24xx())
456 if (enable_1510_mode && dma_chan[ch + 6].saved_csr) 694 offset = OMAP2_DMA_CDSA_REG(lch);
457 handled_now += dma_handle_ch(ch + 6);
458 if (!handled_now)
459 break;
460 handled += handled_now;
461 }
462 695
463 return handled ? IRQ_HANDLED : IRQ_NONE; 696 return offset;
464} 697}
465 698
466int omap_request_dma(int dev_id, const char *dev_name, 699/*
467 void (* callback)(int lch, u16 ch_status, void *data), 700 * Returns current source transfer counting for the given DMA channel.
468 void *data, int *dma_ch_out) 701 * Can be used to monitor the progress of a transfer inside a block.
702 * It must be called with disabled interrupts.
703 */
704int omap_get_dma_src_addr_counter(int lch)
469{ 705{
470 int ch, free_ch = -1; 706 return (dma_addr_t) OMAP_DMA_CSAC_REG(lch);
471 unsigned long flags;
472 struct omap_dma_lch *chan;
473
474 spin_lock_irqsave(&dma_chan_lock, flags);
475 for (ch = 0; ch < dma_chan_count; ch++) {
476 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
477 free_ch = ch;
478 if (dev_id == 0)
479 break;
480 }
481 }
482 if (free_ch == -1) {
483 spin_unlock_irqrestore(&dma_chan_lock, flags);
484 return -EBUSY;
485 }
486 chan = dma_chan + free_ch;
487 chan->dev_id = dev_id;
488 clear_lch_regs(free_ch);
489 spin_unlock_irqrestore(&dma_chan_lock, flags);
490
491 chan->dev_id = dev_id;
492 chan->dev_name = dev_name;
493 chan->callback = callback;
494 chan->data = data;
495 chan->enabled_irqs = OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
496
497 if (cpu_is_omap16xx()) {
498 /* If the sync device is set, configure it dynamically. */
499 if (dev_id != 0) {
500 set_gdma_dev(free_ch + 1, dev_id);
501 dev_id = free_ch + 1;
502 }
503 /* Disable the 1510 compatibility mode and set the sync device
504 * id. */
505 omap_writew(dev_id | (1 << 10), OMAP_DMA_CCR(free_ch));
506 } else {
507 omap_writew(dev_id, OMAP_DMA_CCR(free_ch));
508 }
509 *dma_ch_out = free_ch;
510
511 return 0;
512} 707}
513 708
514void omap_free_dma(int ch) 709int omap_dma_running(void)
515{ 710{
516 unsigned long flags; 711 int lch;
517 712
518 spin_lock_irqsave(&dma_chan_lock, flags); 713 /* Check if LCD DMA is running */
519 if (dma_chan[ch].dev_id == -1) { 714 if (cpu_is_omap16xx())
520 printk("omap_dma: trying to free nonallocated DMA channel %d\n", ch); 715 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
521 spin_unlock_irqrestore(&dma_chan_lock, flags); 716 return 1;
522 return;
523 }
524 dma_chan[ch].dev_id = -1;
525 spin_unlock_irqrestore(&dma_chan_lock, flags);
526 717
527 /* Disable all DMA interrupts for the channel. */ 718 for (lch = 0; lch < dma_chan_count; lch++)
528 omap_writew(0, OMAP_DMA_CICR(ch)); 719 if (OMAP_DMA_CCR_REG(lch) & OMAP_DMA_CCR_EN)
529 /* Make sure the DMA transfer is stopped. */ 720 return 1;
530 omap_writew(0, OMAP_DMA_CCR(ch));
531}
532 721
533int omap_dma_in_1510_mode(void) 722 return 0;
534{
535 return enable_1510_mode;
536} 723}
537 724
538/* 725/*
@@ -550,7 +737,8 @@ void omap_dma_link_lch (int lch_head, int lch_queue)
550 737
551 if ((dma_chan[lch_head].dev_id == -1) || 738 if ((dma_chan[lch_head].dev_id == -1) ||
552 (dma_chan[lch_queue].dev_id == -1)) { 739 (dma_chan[lch_queue].dev_id == -1)) {
553 printk(KERN_ERR "omap_dma: trying to link non requested channels\n"); 740 printk(KERN_ERR "omap_dma: trying to link "
741 "non requested channels\n");
554 dump_stack(); 742 dump_stack();
555 } 743 }
556 744
@@ -570,20 +758,149 @@ void omap_dma_unlink_lch (int lch_head, int lch_queue)
570 758
571 if (dma_chan[lch_head].next_lch != lch_queue || 759 if (dma_chan[lch_head].next_lch != lch_queue ||
572 dma_chan[lch_head].next_lch == -1) { 760 dma_chan[lch_head].next_lch == -1) {
573 printk(KERN_ERR "omap_dma: trying to unlink non linked channels\n"); 761 printk(KERN_ERR "omap_dma: trying to unlink "
762 "non linked channels\n");
574 dump_stack(); 763 dump_stack();
575 } 764 }
576 765
577 766
578 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) || 767 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
579 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) { 768 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
580 printk(KERN_ERR "omap_dma: You need to stop the DMA channels before unlinking\n"); 769 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
770 "before unlinking\n");
581 dump_stack(); 771 dump_stack();
582 } 772 }
583 773
584 dma_chan[lch_head].next_lch = -1; 774 dma_chan[lch_head].next_lch = -1;
585} 775}
586 776
777/*----------------------------------------------------------------------------*/
778
779#ifdef CONFIG_ARCH_OMAP1
780
781static int omap1_dma_handle_ch(int ch)
782{
783 u16 csr;
784
785 if (enable_1510_mode && ch >= 6) {
786 csr = dma_chan[ch].saved_csr;
787 dma_chan[ch].saved_csr = 0;
788 } else
789 csr = OMAP_DMA_CSR_REG(ch);
790 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
791 dma_chan[ch + 6].saved_csr = csr >> 7;
792 csr &= 0x7f;
793 }
794 if ((csr & 0x3f) == 0)
795 return 0;
796 if (unlikely(dma_chan[ch].dev_id == -1)) {
797 printk(KERN_WARNING "Spurious interrupt from DMA channel "
798 "%d (CSR %04x)\n", ch, csr);
799 return 0;
800 }
801 if (unlikely(csr & OMAP_DMA_TOUT_IRQ))
802 printk(KERN_WARNING "DMA timeout with device %d\n",
803 dma_chan[ch].dev_id);
804 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
805 printk(KERN_WARNING "DMA synchronization event drop occurred "
806 "with device %d\n", dma_chan[ch].dev_id);
807 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
808 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
809 if (likely(dma_chan[ch].callback != NULL))
810 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
811 return 1;
812}
813
814static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id,
815 struct pt_regs *regs)
816{
817 int ch = ((int) dev_id) - 1;
818 int handled = 0;
819
820 for (;;) {
821 int handled_now = 0;
822
823 handled_now += omap1_dma_handle_ch(ch);
824 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
825 handled_now += omap1_dma_handle_ch(ch + 6);
826 if (!handled_now)
827 break;
828 handled += handled_now;
829 }
830
831 return handled ? IRQ_HANDLED : IRQ_NONE;
832}
833
834#else
835#define omap1_dma_irq_handler NULL
836#endif
837
838#ifdef CONFIG_ARCH_OMAP2
839
840static int omap2_dma_handle_ch(int ch)
841{
842 u32 status = OMAP_DMA_CSR_REG(ch);
843 u32 val;
844
845 if (!status)
846 return 0;
847 if (unlikely(dma_chan[ch].dev_id == -1))
848 return 0;
849 /* REVISIT: According to 24xx TRM, there's no TOUT_IE */
850 if (unlikely(status & OMAP_DMA_TOUT_IRQ))
851 printk(KERN_INFO "DMA timeout with device %d\n",
852 dma_chan[ch].dev_id);
853 if (unlikely(status & OMAP_DMA_DROP_IRQ))
854 printk(KERN_INFO
855 "DMA synchronization event drop occurred with device "
856 "%d\n", dma_chan[ch].dev_id);
857
858 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ))
859 printk(KERN_INFO "DMA transaction error with device %d\n",
860 dma_chan[ch].dev_id);
861
862 OMAP_DMA_CSR_REG(ch) = 0x20;
863
864 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
865 /* ch in this function is from 0-31 while in register it is 1-32 */
866 val = 1 << (ch);
867 omap_writel(val, OMAP_DMA4_IRQSTATUS_L0);
868
869 if (likely(dma_chan[ch].callback != NULL))
870 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
871
872 return 0;
873}
874
875/* STATUS register count is from 1-32 while our is 0-31 */
876static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id,
877 struct pt_regs *regs)
878{
879 u32 val;
880 int i;
881
882 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
883
884 for (i = 1; i <= OMAP_LOGICAL_DMA_CH_COUNT; i++) {
885 int active = val & (1 << (i - 1));
886 if (active)
887 omap2_dma_handle_ch(i - 1);
888 }
889
890 return IRQ_HANDLED;
891}
892
893static struct irqaction omap24xx_dma_irq = {
894 .name = "DMA",
895 .handler = omap2_dma_irq_handler,
896 .flags = SA_INTERRUPT
897};
898
899#else
900static struct irqaction omap24xx_dma_irq;
901#endif
902
903/*----------------------------------------------------------------------------*/
587 904
588static struct lcd_dma_info { 905static struct lcd_dma_info {
589 spinlock_t lock; 906 spinlock_t lock;
@@ -795,7 +1112,7 @@ static void set_b1_regs(void)
795 /* Always set the source port as SDRAM for now*/ 1112 /* Always set the source port as SDRAM for now*/
796 w &= ~(0x03 << 6); 1113 w &= ~(0x03 << 6);
797 if (lcd_dma.callback != NULL) 1114 if (lcd_dma.callback != NULL)
798 w |= 1 << 1; /* Block interrupt enable */ 1115 w |= 1 << 1; /* Block interrupt enable */
799 else 1116 else
800 w &= ~(1 << 1); 1117 w &= ~(1 << 1);
801 omap_writew(w, OMAP1610_DMA_LCD_CTRL); 1118 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
@@ -814,7 +1131,8 @@ static void set_b1_regs(void)
814 omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L); 1131 omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
815} 1132}
816 1133
817static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs) 1134static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id,
1135 struct pt_regs *regs)
818{ 1136{
819 u16 w; 1137 u16 w;
820 1138
@@ -870,7 +1188,8 @@ void omap_free_lcd_dma(void)
870 return; 1188 return;
871 } 1189 }
872 if (!enable_1510_mode) 1190 if (!enable_1510_mode)
873 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1, OMAP1610_DMA_LCD_CCR); 1191 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
1192 OMAP1610_DMA_LCD_CCR);
874 lcd_dma.reserved = 0; 1193 lcd_dma.reserved = 0;
875 spin_unlock(&lcd_dma.lock); 1194 spin_unlock(&lcd_dma.lock);
876} 1195}
@@ -939,93 +1258,24 @@ void omap_stop_lcd_dma(void)
939 omap_writew(w, OMAP1610_DMA_LCD_CTRL); 1258 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
940} 1259}
941 1260
942/* 1261/*----------------------------------------------------------------------------*/
943 * Clears any DMA state so the DMA engine is ready to restart with new buffers
944 * through omap_start_dma(). Any buffers in flight are discarded.
945 */
946void omap_clear_dma(int lch)
947{
948 unsigned long flags;
949 int status;
950
951 local_irq_save(flags);
952 omap_writew(omap_readw(OMAP_DMA_CCR(lch)) & ~OMAP_DMA_CCR_EN,
953 OMAP_DMA_CCR(lch));
954 status = OMAP_DMA_CSR(lch); /* clear pending interrupts */
955 local_irq_restore(flags);
956}
957
958/*
959 * Returns current physical source address for the given DMA channel.
960 * If the channel is running the caller must disable interrupts prior calling
961 * this function and process the returned value before re-enabling interrupt to
962 * prevent races with the interrupt handler. Note that in continuous mode there
963 * is a chance for CSSA_L register overflow inbetween the two reads resulting
964 * in incorrect return value.
965 */
966dma_addr_t omap_get_dma_src_pos(int lch)
967{
968 return (dma_addr_t) (omap_readw(OMAP_DMA_CSSA_L(lch)) |
969 (omap_readw(OMAP_DMA_CSSA_U(lch)) << 16));
970}
971
972/*
973 * Returns current physical destination address for the given DMA channel.
974 * If the channel is running the caller must disable interrupts prior calling
975 * this function and process the returned value before re-enabling interrupt to
976 * prevent races with the interrupt handler. Note that in continuous mode there
977 * is a chance for CDSA_L register overflow inbetween the two reads resulting
978 * in incorrect return value.
979 */
980dma_addr_t omap_get_dma_dst_pos(int lch)
981{
982 return (dma_addr_t) (omap_readw(OMAP_DMA_CDSA_L(lch)) |
983 (omap_readw(OMAP_DMA_CDSA_U(lch)) << 16));
984}
985
986/*
987 * Returns current source transfer counting for the given DMA channel.
988 * Can be used to monitor the progress of a transfer inside a block.
989 * It must be called with disabled interrupts.
990 */
991int omap_get_dma_src_addr_counter(int lch)
992{
993 return (dma_addr_t) omap_readw(OMAP_DMA_CSAC(lch));
994}
995
996int omap_dma_running(void)
997{
998 int lch;
999
1000 /* Check if LCD DMA is running */
1001 if (cpu_is_omap16xx())
1002 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1003 return 1;
1004
1005 for (lch = 0; lch < dma_chan_count; lch++) {
1006 u16 w;
1007
1008 w = omap_readw(OMAP_DMA_CCR(lch));
1009 if (w & OMAP_DMA_CCR_EN)
1010 return 1;
1011 }
1012 return 0;
1013}
1014 1262
1015static int __init omap_init_dma(void) 1263static int __init omap_init_dma(void)
1016{ 1264{
1017 int ch, r; 1265 int ch, r;
1018 1266
1019 if (cpu_is_omap1510()) { 1267 if (cpu_is_omap15xx()) {
1020 printk(KERN_INFO "DMA support for OMAP1510 initialized\n"); 1268 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
1021 dma_chan_count = 9; 1269 dma_chan_count = 9;
1022 enable_1510_mode = 1; 1270 enable_1510_mode = 1;
1023 } else if (cpu_is_omap16xx() || cpu_is_omap730()) { 1271 } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
1024 printk(KERN_INFO "OMAP DMA hardware version %d\n", 1272 printk(KERN_INFO "OMAP DMA hardware version %d\n",
1025 omap_readw(OMAP_DMA_HW_ID)); 1273 omap_readw(OMAP_DMA_HW_ID));
1026 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n", 1274 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
1027 (omap_readw(OMAP_DMA_CAPS_0_U) << 16) | omap_readw(OMAP_DMA_CAPS_0_L), 1275 (omap_readw(OMAP_DMA_CAPS_0_U) << 16) |
1028 (omap_readw(OMAP_DMA_CAPS_1_U) << 16) | omap_readw(OMAP_DMA_CAPS_1_L), 1276 omap_readw(OMAP_DMA_CAPS_0_L),
1277 (omap_readw(OMAP_DMA_CAPS_1_U) << 16) |
1278 omap_readw(OMAP_DMA_CAPS_1_L),
1029 omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3), 1279 omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3),
1030 omap_readw(OMAP_DMA_CAPS_4)); 1280 omap_readw(OMAP_DMA_CAPS_4));
1031 if (!enable_1510_mode) { 1281 if (!enable_1510_mode) {
@@ -1038,6 +1288,11 @@ static int __init omap_init_dma(void)
1038 dma_chan_count = 16; 1288 dma_chan_count = 16;
1039 } else 1289 } else
1040 dma_chan_count = 9; 1290 dma_chan_count = 9;
1291 } else if (cpu_is_omap24xx()) {
1292 u8 revision = omap_readb(OMAP_DMA4_REVISION);
1293 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
1294 revision >> 4, revision & 0xf);
1295 dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT;
1041 } else { 1296 } else {
1042 dma_chan_count = 0; 1297 dma_chan_count = 0;
1043 return 0; 1298 return 0;
@@ -1049,41 +1304,56 @@ static int __init omap_init_dma(void)
1049 memset(&dma_chan, 0, sizeof(dma_chan)); 1304 memset(&dma_chan, 0, sizeof(dma_chan));
1050 1305
1051 for (ch = 0; ch < dma_chan_count; ch++) { 1306 for (ch = 0; ch < dma_chan_count; ch++) {
1307 omap_clear_dma(ch);
1052 dma_chan[ch].dev_id = -1; 1308 dma_chan[ch].dev_id = -1;
1053 dma_chan[ch].next_lch = -1; 1309 dma_chan[ch].next_lch = -1;
1054 1310
1055 if (ch >= 6 && enable_1510_mode) 1311 if (ch >= 6 && enable_1510_mode)
1056 continue; 1312 continue;
1057 1313
1058 /* request_irq() doesn't like dev_id (ie. ch) being zero, 1314 if (cpu_class_is_omap1()) {
1059 * so we have to kludge around this. */ 1315 /* request_irq() doesn't like dev_id (ie. ch) being
1060 r = request_irq(dma_irq[ch], dma_irq_handler, 0, "DMA", 1316 * zero, so we have to kludge around this. */
1061 (void *) (ch + 1)); 1317 r = request_irq(omap1_dma_irq[ch],
1318 omap1_dma_irq_handler, 0, "DMA",
1319 (void *) (ch + 1));
1320 if (r != 0) {
1321 int i;
1322
1323 printk(KERN_ERR "unable to request IRQ %d "
1324 "for DMA (error %d)\n",
1325 omap1_dma_irq[ch], r);
1326 for (i = 0; i < ch; i++)
1327 free_irq(omap1_dma_irq[i],
1328 (void *) (i + 1));
1329 return r;
1330 }
1331 }
1332 }
1333
1334 if (cpu_is_omap24xx())
1335 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
1336
1337 /* FIXME: Update LCD DMA to work on 24xx */
1338 if (cpu_class_is_omap1()) {
1339 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
1340 "LCD DMA", NULL);
1062 if (r != 0) { 1341 if (r != 0) {
1063 int i; 1342 int i;
1064 1343
1065 printk(KERN_ERR "unable to request IRQ %d for DMA (error %d)\n", 1344 printk(KERN_ERR "unable to request IRQ for LCD DMA "
1066 dma_irq[ch], r); 1345 "(error %d)\n", r);
1067 for (i = 0; i < ch; i++) 1346 for (i = 0; i < dma_chan_count; i++)
1068 free_irq(dma_irq[i], (void *) (i + 1)); 1347 free_irq(omap1_dma_irq[i], (void *) (i + 1));
1069 return r; 1348 return r;
1070 } 1349 }
1071 } 1350 }
1072 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0, "LCD DMA", NULL);
1073 if (r != 0) {
1074 int i;
1075 1351
1076 printk(KERN_ERR "unable to request IRQ for LCD DMA (error %d)\n", r);
1077 for (i = 0; i < dma_chan_count; i++)
1078 free_irq(dma_irq[i], (void *) (i + 1));
1079 return r;
1080 }
1081 return 0; 1352 return 0;
1082} 1353}
1083 1354
1084arch_initcall(omap_init_dma); 1355arch_initcall(omap_init_dma);
1085 1356
1086
1087EXPORT_SYMBOL(omap_get_dma_src_pos); 1357EXPORT_SYMBOL(omap_get_dma_src_pos);
1088EXPORT_SYMBOL(omap_get_dma_dst_pos); 1358EXPORT_SYMBOL(omap_get_dma_dst_pos);
1089EXPORT_SYMBOL(omap_get_dma_src_addr_counter); 1359EXPORT_SYMBOL(omap_get_dma_src_addr_counter);
@@ -1109,6 +1379,8 @@ EXPORT_SYMBOL(omap_set_dma_dest_index);
1109EXPORT_SYMBOL(omap_set_dma_dest_data_pack); 1379EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
1110EXPORT_SYMBOL(omap_set_dma_dest_burst_mode); 1380EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
1111 1381
1382EXPORT_SYMBOL(omap_set_dma_params);
1383
1112EXPORT_SYMBOL(omap_dma_link_lch); 1384EXPORT_SYMBOL(omap_dma_link_lch);
1113EXPORT_SYMBOL(omap_dma_unlink_lch); 1385EXPORT_SYMBOL(omap_dma_unlink_lch);
1114 1386
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 55059a24ad41..76f721d85137 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -140,7 +140,7 @@ static struct gpio_bank gpio_bank_1610[5] = {
140}; 140};
141#endif 141#endif
142 142
143#ifdef CONFIG_ARCH_OMAP1510 143#ifdef CONFIG_ARCH_OMAP15XX
144static struct gpio_bank gpio_bank_1510[2] = { 144static struct gpio_bank gpio_bank_1510[2] = {
145 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, 145 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
146 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 } 146 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
@@ -173,7 +173,7 @@ static int gpio_bank_count;
173 173
174static inline struct gpio_bank *get_gpio_bank(int gpio) 174static inline struct gpio_bank *get_gpio_bank(int gpio)
175{ 175{
176#ifdef CONFIG_ARCH_OMAP1510 176#ifdef CONFIG_ARCH_OMAP15XX
177 if (cpu_is_omap1510()) { 177 if (cpu_is_omap1510()) {
178 if (OMAP_GPIO_IS_MPUIO(gpio)) 178 if (OMAP_GPIO_IS_MPUIO(gpio))
179 return &gpio_bank[0]; 179 return &gpio_bank[0];
@@ -222,7 +222,7 @@ static inline int gpio_valid(int gpio)
222 return -1; 222 return -1;
223 return 0; 223 return 0;
224 } 224 }
225#ifdef CONFIG_ARCH_OMAP1510 225#ifdef CONFIG_ARCH_OMAP15XX
226 if (cpu_is_omap1510() && gpio < 16) 226 if (cpu_is_omap1510() && gpio < 16)
227 return 0; 227 return 0;
228#endif 228#endif
@@ -654,7 +654,7 @@ int omap_request_gpio(int gpio)
654 /* Set trigger to none. You need to enable the trigger after request_irq */ 654 /* Set trigger to none. You need to enable the trigger after request_irq */
655 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE); 655 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
656 656
657#ifdef CONFIG_ARCH_OMAP1510 657#ifdef CONFIG_ARCH_OMAP15XX
658 if (bank->method == METHOD_GPIO_1510) { 658 if (bank->method == METHOD_GPIO_1510) {
659 void __iomem *reg; 659 void __iomem *reg;
660 660
@@ -739,7 +739,7 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
739 bank = (struct gpio_bank *) desc->data; 739 bank = (struct gpio_bank *) desc->data;
740 if (bank->method == METHOD_MPUIO) 740 if (bank->method == METHOD_MPUIO)
741 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT; 741 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
742#ifdef CONFIG_ARCH_OMAP1510 742#ifdef CONFIG_ARCH_OMAP15XX
743 if (bank->method == METHOD_GPIO_1510) 743 if (bank->method == METHOD_GPIO_1510)
744 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS; 744 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
745#endif 745#endif
@@ -774,7 +774,7 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
774 d = irq_desc + gpio_irq; 774 d = irq_desc + gpio_irq;
775 desc_handle_irq(gpio_irq, d, regs); 775 desc_handle_irq(gpio_irq, d, regs);
776 } 776 }
777 } 777 }
778} 778}
779 779
780static void gpio_ack_irq(unsigned int irq) 780static void gpio_ack_irq(unsigned int irq)
@@ -837,8 +837,9 @@ static struct irqchip mpuio_irq_chip = {
837 .unmask = mpuio_unmask_irq 837 .unmask = mpuio_unmask_irq
838}; 838};
839 839
840static int initialized = 0; 840static int initialized;
841static struct clk * gpio_ck = NULL; 841static struct clk * gpio_ick;
842static struct clk * gpio_fck;
842 843
843static int __init _omap_gpio_init(void) 844static int __init _omap_gpio_init(void)
844{ 845{
@@ -848,14 +849,26 @@ static int __init _omap_gpio_init(void)
848 initialized = 1; 849 initialized = 1;
849 850
850 if (cpu_is_omap1510()) { 851 if (cpu_is_omap1510()) {
851 gpio_ck = clk_get(NULL, "arm_gpio_ck"); 852 gpio_ick = clk_get(NULL, "arm_gpio_ck");
852 if (IS_ERR(gpio_ck)) 853 if (IS_ERR(gpio_ick))
853 printk("Could not get arm_gpio_ck\n"); 854 printk("Could not get arm_gpio_ck\n");
854 else 855 else
855 clk_use(gpio_ck); 856 clk_use(gpio_ick);
857 }
858 if (cpu_is_omap24xx()) {
859 gpio_ick = clk_get(NULL, "gpios_ick");
860 if (IS_ERR(gpio_ick))
861 printk("Could not get gpios_ick\n");
862 else
863 clk_use(gpio_ick);
864 gpio_fck = clk_get(NULL, "gpios_fck");
865 if (IS_ERR(gpio_ick))
866 printk("Could not get gpios_fck\n");
867 else
868 clk_use(gpio_fck);
856 } 869 }
857 870
858#ifdef CONFIG_ARCH_OMAP1510 871#ifdef CONFIG_ARCH_OMAP15XX
859 if (cpu_is_omap1510()) { 872 if (cpu_is_omap1510()) {
860 printk(KERN_INFO "OMAP1510 GPIO hardware\n"); 873 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
861 gpio_bank_count = 2; 874 gpio_bank_count = 2;
@@ -901,7 +914,7 @@ static int __init _omap_gpio_init(void)
901 if (bank->method == METHOD_MPUIO) { 914 if (bank->method == METHOD_MPUIO) {
902 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT); 915 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
903 } 916 }
904#ifdef CONFIG_ARCH_OMAP1510 917#ifdef CONFIG_ARCH_OMAP15XX
905 if (bank->method == METHOD_GPIO_1510) { 918 if (bank->method == METHOD_GPIO_1510) {
906 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); 919 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
907 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); 920 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
@@ -1038,6 +1051,7 @@ static struct sys_device omap_gpio_device = {
1038 1051
1039/* 1052/*
1040 * This may get called early from board specific init 1053 * This may get called early from board specific init
1054 * for boards that have interrupts routed via FPGA.
1041 */ 1055 */
1042int omap_gpio_init(void) 1056int omap_gpio_init(void)
1043{ 1057{
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 9c9b7df3faf6..ea9475c86656 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -491,17 +491,20 @@ int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
491 omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch, 491 omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
492 OMAP_DMA_DATA_TYPE_S16, 492 OMAP_DMA_DATA_TYPE_S16,
493 length >> 1, 1, 493 length >> 1, 1,
494 OMAP_DMA_SYNC_ELEMENT); 494 OMAP_DMA_SYNC_ELEMENT,
495 0, 0);
495 496
496 omap_set_dma_dest_params(mcbsp[id].dma_tx_lch, 497 omap_set_dma_dest_params(mcbsp[id].dma_tx_lch,
497 OMAP_DMA_PORT_TIPB, 498 OMAP_DMA_PORT_TIPB,
498 OMAP_DMA_AMODE_CONSTANT, 499 OMAP_DMA_AMODE_CONSTANT,
499 mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1); 500 mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1,
501 0, 0);
500 502
501 omap_set_dma_src_params(mcbsp[id].dma_tx_lch, 503 omap_set_dma_src_params(mcbsp[id].dma_tx_lch,
502 OMAP_DMA_PORT_EMIFF, 504 OMAP_DMA_PORT_EMIFF,
503 OMAP_DMA_AMODE_POST_INC, 505 OMAP_DMA_AMODE_POST_INC,
504 buffer); 506 buffer,
507 0, 0);
505 508
506 omap_start_dma(mcbsp[id].dma_tx_lch); 509 omap_start_dma(mcbsp[id].dma_tx_lch);
507 wait_for_completion(&(mcbsp[id].tx_dma_completion)); 510 wait_for_completion(&(mcbsp[id].tx_dma_completion));
@@ -531,17 +534,20 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
531 omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch, 534 omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
532 OMAP_DMA_DATA_TYPE_S16, 535 OMAP_DMA_DATA_TYPE_S16,
533 length >> 1, 1, 536 length >> 1, 1,
534 OMAP_DMA_SYNC_ELEMENT); 537 OMAP_DMA_SYNC_ELEMENT,
538 0, 0);
535 539
536 omap_set_dma_src_params(mcbsp[id].dma_rx_lch, 540 omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
537 OMAP_DMA_PORT_TIPB, 541 OMAP_DMA_PORT_TIPB,
538 OMAP_DMA_AMODE_CONSTANT, 542 OMAP_DMA_AMODE_CONSTANT,
539 mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1); 543 mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1,
544 0, 0);
540 545
541 omap_set_dma_dest_params(mcbsp[id].dma_rx_lch, 546 omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
542 OMAP_DMA_PORT_EMIFF, 547 OMAP_DMA_PORT_EMIFF,
543 OMAP_DMA_AMODE_POST_INC, 548 OMAP_DMA_AMODE_POST_INC,
544 buffer); 549 buffer,
550 0, 0);
545 551
546 omap_start_dma(mcbsp[id].dma_rx_lch); 552 omap_start_dma(mcbsp[id].dma_rx_lch);
547 wait_for_completion(&(mcbsp[id].rx_dma_completion)); 553 wait_for_completion(&(mcbsp[id].rx_dma_completion));
@@ -643,7 +649,7 @@ static const struct omap_mcbsp_info mcbsp_730[] = {
643}; 649};
644#endif 650#endif
645 651
646#ifdef CONFIG_ARCH_OMAP1510 652#ifdef CONFIG_ARCH_OMAP15XX
647static const struct omap_mcbsp_info mcbsp_1510[] = { 653static const struct omap_mcbsp_info mcbsp_1510[] = {
648 [0] = { .virt_base = OMAP1510_MCBSP1_BASE, 654 [0] = { .virt_base = OMAP1510_MCBSP1_BASE,
649 .dma_rx_sync = OMAP_DMA_MCBSP1_RX, 655 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
@@ -712,7 +718,7 @@ static int __init omap_mcbsp_init(void)
712 mcbsp_count = ARRAY_SIZE(mcbsp_730); 718 mcbsp_count = ARRAY_SIZE(mcbsp_730);
713 } 719 }
714#endif 720#endif
715#ifdef CONFIG_ARCH_OMAP1510 721#ifdef CONFIG_ARCH_OMAP15XX
716 if (cpu_is_omap1510()) { 722 if (cpu_is_omap1510()) {
717 mcbsp_info = mcbsp_1510; 723 mcbsp_info = mcbsp_1510;
718 mcbsp_count = ARRAY_SIZE(mcbsp_1510); 724 mcbsp_count = ARRAY_SIZE(mcbsp_1510);
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index 64482040f89e..8c1c016aa689 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h 4 * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
5 * 5 *
6 * Copyright (C) 2003 Nokia Corporation 6 * Copyright (C) 2003 - 2005 Nokia Corporation
7 * 7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com> 8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 * 9 *
@@ -25,38 +25,74 @@
25#include <linux/config.h> 25#include <linux/config.h>
26#include <linux/module.h> 26#include <linux/module.h>
27#include <linux/init.h> 27#include <linux/init.h>
28#include <linux/kernel.h>
28#include <asm/system.h> 29#include <asm/system.h>
29#include <asm/io.h> 30#include <asm/io.h>
30#include <linux/spinlock.h> 31#include <linux/spinlock.h>
31
32#define __MUX_C__
33#include <asm/arch/mux.h> 32#include <asm/arch/mux.h>
34 33
35#ifdef CONFIG_OMAP_MUX 34#ifdef CONFIG_OMAP_MUX
36 35
36#define OMAP24XX_L4_BASE 0x48000000
37#define OMAP24XX_PULL_ENA (1 << 3)
38#define OMAP24XX_PULL_UP (1 << 4)
39
40static struct pin_config * pin_table;
41static unsigned long pin_table_sz;
42
43extern struct pin_config * omap730_pins;
44extern struct pin_config * omap1xxx_pins;
45extern struct pin_config * omap24xx_pins;
46
47int __init omap_mux_register(struct pin_config * pins, unsigned long size)
48{
49 pin_table = pins;
50 pin_table_sz = size;
51
52 return 0;
53}
54
37/* 55/*
38 * Sets the Omap MUX and PULL_DWN registers based on the table 56 * Sets the Omap MUX and PULL_DWN registers based on the table
39 */ 57 */
40int __init_or_module 58int __init_or_module omap_cfg_reg(const unsigned long index)
41omap_cfg_reg(const reg_cfg_t reg_cfg)
42{ 59{
43 static DEFINE_SPINLOCK(mux_spin_lock); 60 static DEFINE_SPINLOCK(mux_spin_lock);
44 61
45 unsigned long flags; 62 unsigned long flags;
46 reg_cfg_set *cfg; 63 struct pin_config *cfg;
47 unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0, 64 unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
48 pull_orig = 0, pull = 0; 65 pull_orig = 0, pull = 0;
49 unsigned int mask, warn = 0; 66 unsigned int mask, warn = 0;
50 67
51 if (cpu_is_omap7xx()) 68 if (!pin_table)
52 return 0; 69 BUG();
53 70
54 if (reg_cfg > ARRAY_SIZE(reg_cfg_table)) { 71 if (index >= pin_table_sz) {
55 printk(KERN_ERR "MUX: reg_cfg %d\n", reg_cfg); 72 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
56 return -EINVAL; 73 index, pin_table_sz);
74 dump_stack();
75 return -ENODEV;
57 } 76 }
58 77
59 cfg = (reg_cfg_set *)&reg_cfg_table[reg_cfg]; 78 cfg = (struct pin_config *)&pin_table[index];
79 if (cpu_is_omap24xx()) {
80 u8 reg = 0;
81
82 reg |= cfg->mask & 0x7;
83 if (cfg->pull_val)
84 reg |= OMAP24XX_PULL_ENA;
85 if(cfg->pu_pd_val)
86 reg |= OMAP24XX_PULL_UP;
87#ifdef CONFIG_OMAP_MUX_DEBUG
88 printk("Muxing %s (0x%08x): 0x%02x -> 0x%02x\n",
89 cfg->name, OMAP24XX_L4_BASE + cfg->mux_reg,
90 omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg), reg);
91#endif
92 omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg);
93
94 return 0;
95 }
60 96
61 /* Check the mux register in question */ 97 /* Check the mux register in question */
62 if (cfg->mux_reg) { 98 if (cfg->mux_reg) {
@@ -157,7 +193,8 @@ omap_cfg_reg(const reg_cfg_t reg_cfg)
157 return 0; 193 return 0;
158#endif 194#endif
159} 195}
160
161EXPORT_SYMBOL(omap_cfg_reg); 196EXPORT_SYMBOL(omap_cfg_reg);
162 197#else
198#define omap_mux_init() do {} while(0)
199#define omap_cfg_reg(x) do {} while(0)
163#endif /* CONFIG_OMAP_MUX */ 200#endif /* CONFIG_OMAP_MUX */
diff --git a/arch/arm/plat-omap/pm.c b/arch/arm/plat-omap/pm.c
index e15c6c1ddec9..966cca031ca7 100644
--- a/arch/arm/plat-omap/pm.c
+++ b/arch/arm/plat-omap/pm.c
@@ -54,11 +54,12 @@
54#include <asm/arch/tps65010.h> 54#include <asm/arch/tps65010.h>
55#include <asm/arch/dsp_common.h> 55#include <asm/arch/dsp_common.h>
56 56
57#include "clock.h" 57#include <asm/arch/clock.h>
58#include "sram.h" 58#include <asm/arch/sram.h>
59 59
60static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE]; 60static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
61static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE]; 61static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
62static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
62static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE]; 63static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
63static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE]; 64static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
64 65
@@ -120,8 +121,8 @@ void omap_pm_idle(void)
120 */ 121 */
121static void omap_pm_wakeup_setup(void) 122static void omap_pm_wakeup_setup(void)
122{ 123{
123 u32 level1_wake = OMAP_IRQ_BIT(INT_IH2_IRQ); 124 u32 level1_wake = 0;
124 u32 level2_wake = OMAP_IRQ_BIT(INT_UART2) | OMAP_IRQ_BIT(INT_KEYBOARD); 125 u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
125 126
126 /* 127 /*
127 * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade, 128 * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
@@ -129,19 +130,29 @@ static void omap_pm_wakeup_setup(void)
129 * drivers must still separately call omap_set_gpio_wakeup() to 130 * drivers must still separately call omap_set_gpio_wakeup() to
130 * wake up to a GPIO interrupt. 131 * wake up to a GPIO interrupt.
131 */ 132 */
132 if (cpu_is_omap1510() || cpu_is_omap16xx()) 133 if (cpu_is_omap730())
133 level1_wake |= OMAP_IRQ_BIT(INT_GPIO_BANK1); 134 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
134 else if (cpu_is_omap730()) 135 OMAP_IRQ_BIT(INT_730_IH2_IRQ);
135 level1_wake |= OMAP_IRQ_BIT(INT_730_GPIO_BANK1); 136 else if (cpu_is_omap1510())
137 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
138 OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
139 else if (cpu_is_omap16xx())
140 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
141 OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
136 142
137 omap_writel(~level1_wake, OMAP_IH1_MIR); 143 omap_writel(~level1_wake, OMAP_IH1_MIR);
138 144
139 if (cpu_is_omap1510()) 145 if (cpu_is_omap730()) {
146 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
147 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) | OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)), OMAP_IH2_1_MIR);
148 } else if (cpu_is_omap1510()) {
149 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
140 omap_writel(~level2_wake, OMAP_IH2_MIR); 150 omap_writel(~level2_wake, OMAP_IH2_MIR);
141 151 } else if (cpu_is_omap16xx()) {
142 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */ 152 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
143 if (cpu_is_omap16xx()) {
144 omap_writel(~level2_wake, OMAP_IH2_0_MIR); 153 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
154
155 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
145 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ), OMAP_IH2_1_MIR); 156 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ), OMAP_IH2_1_MIR);
146 omap_writel(~0x0, OMAP_IH2_2_MIR); 157 omap_writel(~0x0, OMAP_IH2_2_MIR);
147 omap_writel(~0x0, OMAP_IH2_3_MIR); 158 omap_writel(~0x0, OMAP_IH2_3_MIR);
@@ -185,7 +196,17 @@ void omap_pm_suspend(void)
185 * Save interrupt, MPUI, ARM and UPLD control registers. 196 * Save interrupt, MPUI, ARM and UPLD control registers.
186 */ 197 */
187 198
188 if (cpu_is_omap1510()) { 199 if (cpu_is_omap730()) {
200 MPUI730_SAVE(OMAP_IH1_MIR);
201 MPUI730_SAVE(OMAP_IH2_0_MIR);
202 MPUI730_SAVE(OMAP_IH2_1_MIR);
203 MPUI730_SAVE(MPUI_CTRL);
204 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
205 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
206 MPUI730_SAVE(EMIFS_CONFIG);
207 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
208
209 } else if (cpu_is_omap1510()) {
189 MPUI1510_SAVE(OMAP_IH1_MIR); 210 MPUI1510_SAVE(OMAP_IH1_MIR);
190 MPUI1510_SAVE(OMAP_IH2_MIR); 211 MPUI1510_SAVE(OMAP_IH2_MIR);
191 MPUI1510_SAVE(MPUI_CTRL); 212 MPUI1510_SAVE(MPUI_CTRL);
@@ -280,7 +301,13 @@ void omap_pm_suspend(void)
280 ULPD_RESTORE(ULPD_CLOCK_CTRL); 301 ULPD_RESTORE(ULPD_CLOCK_CTRL);
281 ULPD_RESTORE(ULPD_STATUS_REQ); 302 ULPD_RESTORE(ULPD_STATUS_REQ);
282 303
283 if (cpu_is_omap1510()) { 304 if (cpu_is_omap730()) {
305 MPUI730_RESTORE(EMIFS_CONFIG);
306 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
307 MPUI730_RESTORE(OMAP_IH1_MIR);
308 MPUI730_RESTORE(OMAP_IH2_0_MIR);
309 MPUI730_RESTORE(OMAP_IH2_1_MIR);
310 } else if (cpu_is_omap1510()) {
284 MPUI1510_RESTORE(MPUI_CTRL); 311 MPUI1510_RESTORE(MPUI_CTRL);
285 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG); 312 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
286 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG); 313 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
@@ -355,7 +382,14 @@ static int omap_pm_read_proc(
355 ULPD_SAVE(ULPD_DPLL_CTRL); 382 ULPD_SAVE(ULPD_DPLL_CTRL);
356 ULPD_SAVE(ULPD_POWER_CTRL); 383 ULPD_SAVE(ULPD_POWER_CTRL);
357 384
358 if (cpu_is_omap1510()) { 385 if (cpu_is_omap730()) {
386 MPUI730_SAVE(MPUI_CTRL);
387 MPUI730_SAVE(MPUI_DSP_STATUS);
388 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
389 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
390 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
391 MPUI730_SAVE(EMIFS_CONFIG);
392 } else if (cpu_is_omap1510()) {
359 MPUI1510_SAVE(MPUI_CTRL); 393 MPUI1510_SAVE(MPUI_CTRL);
360 MPUI1510_SAVE(MPUI_DSP_STATUS); 394 MPUI1510_SAVE(MPUI_DSP_STATUS);
361 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG); 395 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
@@ -404,7 +438,21 @@ static int omap_pm_read_proc(
404 ULPD_SHOW(ULPD_STATUS_REQ), 438 ULPD_SHOW(ULPD_STATUS_REQ),
405 ULPD_SHOW(ULPD_POWER_CTRL)); 439 ULPD_SHOW(ULPD_POWER_CTRL));
406 440
407 if (cpu_is_omap1510()) { 441 if (cpu_is_omap730()) {
442 my_buffer_offset += sprintf(my_base + my_buffer_offset,
443 "MPUI730_CTRL_REG 0x%-8x \n"
444 "MPUI730_DSP_STATUS_REG: 0x%-8x \n"
445 "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
446 "MPUI730_DSP_API_CONFIG_REG: 0x%-8x \n"
447 "MPUI730_SDRAM_CONFIG_REG: 0x%-8x \n"
448 "MPUI730_EMIFS_CONFIG_REG: 0x%-8x \n",
449 MPUI730_SHOW(MPUI_CTRL),
450 MPUI730_SHOW(MPUI_DSP_STATUS),
451 MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
452 MPUI730_SHOW(MPUI_DSP_API_CONFIG),
453 MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
454 MPUI730_SHOW(EMIFS_CONFIG));
455 } else if (cpu_is_omap1510()) {
408 my_buffer_offset += sprintf(my_base + my_buffer_offset, 456 my_buffer_offset += sprintf(my_base + my_buffer_offset,
409 "MPUI1510_CTRL_REG 0x%-8x \n" 457 "MPUI1510_CTRL_REG 0x%-8x \n"
410 "MPUI1510_DSP_STATUS_REG: 0x%-8x \n" 458 "MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
@@ -553,7 +601,12 @@ static int __init omap_pm_init(void)
553 * These routines need to be in SRAM as that's the only 601 * These routines need to be in SRAM as that's the only
554 * memory the MPU can see when it wakes up. 602 * memory the MPU can see when it wakes up.
555 */ 603 */
556 if (cpu_is_omap1510()) { 604 if (cpu_is_omap730()) {
605 omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend,
606 omap730_idle_loop_suspend_sz);
607 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
608 omap730_cpu_suspend_sz);
609 } else if (cpu_is_omap1510()) {
557 omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend, 610 omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
558 omap1510_idle_loop_suspend_sz); 611 omap1510_idle_loop_suspend_sz);
559 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend, 612 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
@@ -572,7 +625,11 @@ static int __init omap_pm_init(void)
572 625
573 pm_idle = omap_pm_idle; 626 pm_idle = omap_pm_idle;
574 627
575 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq); 628 if (cpu_is_omap730())
629 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
630 else if (cpu_is_omap16xx())
631 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
632
576#if 0 633#if 0
577 /* --- BEGIN BOARD-DEPENDENT CODE --- */ 634 /* --- BEGIN BOARD-DEPENDENT CODE --- */
578 /* Sleepx mask direction */ 635 /* Sleepx mask direction */
@@ -591,7 +648,9 @@ static int __init omap_pm_init(void)
591 omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL); 648 omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
592 649
593 /* Configure IDLECT3 */ 650 /* Configure IDLECT3 */
594 if (cpu_is_omap16xx()) 651 if (cpu_is_omap730())
652 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
653 else if (cpu_is_omap16xx())
595 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3); 654 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
596 655
597 pm_set_ops(&omap_pm_ops); 656 pm_set_ops(&omap_pm_ops);
@@ -600,8 +659,10 @@ static int __init omap_pm_init(void)
600 omap_pm_init_proc(); 659 omap_pm_init_proc();
601#endif 660#endif
602 661
603 /* configure LOW_PWR pin */ 662 if (cpu_is_omap16xx()) {
604 omap_cfg_reg(T20_1610_LOW_PWR); 663 /* configure LOW_PWR pin */
664 omap_cfg_reg(T20_1610_LOW_PWR);
665 }
605 666
606 return 0; 667 return 0;
607} 668}
diff --git a/arch/arm/plat-omap/sleep.S b/arch/arm/plat-omap/sleep.S
index 9f745836f6aa..4cd7d292f854 100644
--- a/arch/arm/plat-omap/sleep.S
+++ b/arch/arm/plat-omap/sleep.S
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/arm/plat-omap/sleep.S 2 * linux/arch/arm/plat-omap/sleep.S
3 * 3 *
4 * Low-level OMAP1510/1610 sleep/wakeUp support 4 * Low-level OMAP730/1510/1610 sleep/wakeUp support
5 * 5 *
6 * Initial SA1110 code: 6 * Initial SA1110 code:
7 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> 7 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
@@ -52,7 +52,57 @@
52 * processor specific functions here. 52 * processor specific functions here.
53 */ 53 */
54 54
55#ifdef CONFIG_ARCH_OMAP1510 55#if defined(CONFIG_ARCH_OMAP730)
56ENTRY(omap730_idle_loop_suspend)
57
58 stmfd sp!, {r0 - r12, lr} @ save registers on stack
59
60 @ load base address of ARM_IDLECT1 and ARM_IDLECT2
61 mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
62 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
63 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
64
65 @ turn off clock domains
66 @ get ARM_IDLECT2 into r2
67 ldrh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
68 mov r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff
69 orr r5, r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff00
70 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
71
72 @ request ARM idle
73 @ get ARM_IDLECT1 into r1
74 ldrh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
75 orr r3, r1, #OMAP730_IDLE_LOOP_REQUEST & 0xffff
76 strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
77
78 mov r5, #IDLE_WAIT_CYCLES & 0xff
79 orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
80l_730: subs r5, r5, #1
81 bne l_730
82/*
83 * Let's wait for the next clock tick to wake us up.
84 */
85 mov r0, #0
86 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
87/*
88 * omap730_idle_loop_suspend()'s resume point.
89 *
90 * It will just start executing here, so we'll restore stuff from the
91 * stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
92 */
93
94 @ restore ARM_IDLECT1 and ARM_IDLECT2 and return
95 @ r1 has ARM_IDLECT1 and r2 still has ARM_IDLECT2
96 strh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
97 strh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
98
99 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
100
101ENTRY(omap730_idle_loop_suspend_sz)
102 .word . - omap730_idle_loop_suspend
103#endif /* CONFIG_ARCH_OMAP730 */
104
105#ifdef CONFIG_ARCH_OMAP15XX
56ENTRY(omap1510_idle_loop_suspend) 106ENTRY(omap1510_idle_loop_suspend)
57 107
58 stmfd sp!, {r0 - r12, lr} @ save registers on stack 108 stmfd sp!, {r0 - r12, lr} @ save registers on stack
@@ -100,7 +150,7 @@ l_1510: subs r5, r5, #1
100 150
101ENTRY(omap1510_idle_loop_suspend_sz) 151ENTRY(omap1510_idle_loop_suspend_sz)
102 .word . - omap1510_idle_loop_suspend 152 .word . - omap1510_idle_loop_suspend
103#endif /* CONFIG_ARCH_OMAP1510 */ 153#endif /* CONFIG_ARCH_OMAP15XX */
104 154
105#if defined(CONFIG_ARCH_OMAP16XX) 155#if defined(CONFIG_ARCH_OMAP16XX)
106ENTRY(omap1610_idle_loop_suspend) 156ENTRY(omap1610_idle_loop_suspend)
@@ -169,7 +219,86 @@ ENTRY(omap1610_idle_loop_suspend_sz)
169 * 219 *
170 */ 220 */
171 221
172#ifdef CONFIG_ARCH_OMAP1510 222#if defined(CONFIG_ARCH_OMAP730)
223ENTRY(omap730_cpu_suspend)
224
225 @ save registers on stack
226 stmfd sp!, {r0 - r12, lr}
227
228 @ Drain write cache
229 mov r4, #0
230 mcr p15, 0, r0, c7, c10, 4
231 nop
232
233 @ load base address of Traffic Controller
234 mov r6, #TCMIF_ASM_BASE & 0xff000000
235 orr r6, r6, #TCMIF_ASM_BASE & 0x00ff0000
236 orr r6, r6, #TCMIF_ASM_BASE & 0x0000ff00
237
238 @ prepare to put SDRAM into self-refresh manually
239 ldr r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
240 orr r9, r7, #SELF_REFRESH_MODE & 0xff000000
241 orr r9, r9, #SELF_REFRESH_MODE & 0x000000ff
242 str r9, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
243
244 @ prepare to put EMIFS to Sleep
245 ldr r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
246 orr r9, r8, #IDLE_EMIFS_REQUEST & 0xff
247 str r9, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
248
249 @ load base address of ARM_IDLECT1 and ARM_IDLECT2
250 mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
251 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
252 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
253
254 @ turn off clock domains
255 @ do not disable PERCK (0x04)
256 mov r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff
257 orr r5, r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff00
258 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
259
260 @ request ARM idle
261 mov r3, #OMAP730_IDLECT1_SLEEP_VAL & 0xff
262 orr r3, r3, #OMAP730_IDLECT1_SLEEP_VAL & 0xff00
263 strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
264
265 @ disable instruction cache
266 mrc p15, 0, r9, c1, c0, 0
267 bic r2, r9, #0x1000
268 mcr p15, 0, r2, c1, c0, 0
269 nop
270
271/*
272 * Let's wait for the next wake up event to wake us up. r0 can't be
273 * used here because r0 holds ARM_IDLECT1
274 */
275 mov r2, #0
276 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
277/*
278 * omap730_cpu_suspend()'s resume point.
279 *
280 * It will just start executing here, so we'll restore stuff from the
281 * stack.
282 */
283 @ re-enable Icache
284 mcr p15, 0, r9, c1, c0, 0
285
286 @ reset the ARM_IDLECT1 and ARM_IDLECT2.
287 strh r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
288 strh r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
289
290 @ Restore EMIFF controls
291 str r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
292 str r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
293
294 @ restore regs and return
295 ldmfd sp!, {r0 - r12, pc}
296
297ENTRY(omap730_cpu_suspend_sz)
298 .word . - omap730_cpu_suspend
299#endif /* CONFIG_ARCH_OMAP730 */
300
301#ifdef CONFIG_ARCH_OMAP15XX
173ENTRY(omap1510_cpu_suspend) 302ENTRY(omap1510_cpu_suspend)
174 303
175 @ save registers on stack 304 @ save registers on stack
@@ -241,7 +370,7 @@ l_1510_2:
241 370
242ENTRY(omap1510_cpu_suspend_sz) 371ENTRY(omap1510_cpu_suspend_sz)
243 .word . - omap1510_cpu_suspend 372 .word . - omap1510_cpu_suspend
244#endif /* CONFIG_ARCH_OMAP1510 */ 373#endif /* CONFIG_ARCH_OMAP15XX */
245 374
246#if defined(CONFIG_ARCH_OMAP16XX) 375#if defined(CONFIG_ARCH_OMAP16XX)
247ENTRY(omap1610_cpu_suspend) 376ENTRY(omap1610_cpu_suspend)
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 7ad69f14a3e7..792f66375830 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -20,10 +20,13 @@
20#include <asm/io.h> 20#include <asm/io.h>
21#include <asm/cacheflush.h> 21#include <asm/cacheflush.h>
22 22
23#include "sram.h" 23#include <asm/arch/sram.h>
24
25#define OMAP1_SRAM_PA 0x20000000
26#define OMAP1_SRAM_VA 0xd0000000
27#define OMAP2_SRAM_PA 0x40200000
28#define OMAP2_SRAM_VA 0xd0000000
24 29
25#define OMAP1_SRAM_BASE 0xd0000000
26#define OMAP1_SRAM_START 0x20000000
27#define SRAM_BOOTLOADER_SZ 0x80 30#define SRAM_BOOTLOADER_SZ 0x80
28 31
29static unsigned long omap_sram_base; 32static unsigned long omap_sram_base;
@@ -31,37 +34,40 @@ static unsigned long omap_sram_size;
31static unsigned long omap_sram_ceil; 34static unsigned long omap_sram_ceil;
32 35
33/* 36/*
34 * The amount of SRAM depends on the core type: 37 * The amount of SRAM depends on the core type.
35 * 730 = 200K, 1510 = 512K, 5912 = 256K, 1610 = 16K, 1710 = 16K
36 * Note that we cannot try to test for SRAM here because writes 38 * Note that we cannot try to test for SRAM here because writes
37 * to secure SRAM will hang the system. Also the SRAM is not 39 * to secure SRAM will hang the system. Also the SRAM is not
38 * yet mapped at this point. 40 * yet mapped at this point.
39 */ 41 */
40void __init omap_detect_sram(void) 42void __init omap_detect_sram(void)
41{ 43{
42 omap_sram_base = OMAP1_SRAM_BASE; 44 if (!cpu_is_omap24xx())
45 omap_sram_base = OMAP1_SRAM_VA;
46 else
47 omap_sram_base = OMAP2_SRAM_VA;
43 48
44 if (cpu_is_omap730()) 49 if (cpu_is_omap730())
45 omap_sram_size = 0x32000; 50 omap_sram_size = 0x32000; /* 200K */
46 else if (cpu_is_omap1510()) 51 else if (cpu_is_omap15xx())
47 omap_sram_size = 0x80000; 52 omap_sram_size = 0x30000; /* 192K */
48 else if (cpu_is_omap1610() || cpu_is_omap1621() || cpu_is_omap1710()) 53 else if (cpu_is_omap1610() || cpu_is_omap1621() || cpu_is_omap1710())
49 omap_sram_size = 0x4000; 54 omap_sram_size = 0x4000; /* 16K */
50 else if (cpu_is_omap1611()) 55 else if (cpu_is_omap1611())
51 omap_sram_size = 0x3e800; 56 omap_sram_size = 0x3e800; /* 250K */
57 else if (cpu_is_omap2420())
58 omap_sram_size = 0xa0014; /* 640K */
52 else { 59 else {
53 printk(KERN_ERR "Could not detect SRAM size\n"); 60 printk(KERN_ERR "Could not detect SRAM size\n");
54 omap_sram_size = 0x4000; 61 omap_sram_size = 0x4000;
55 } 62 }
56 63
57 printk(KERN_INFO "SRAM size: 0x%lx\n", omap_sram_size);
58 omap_sram_ceil = omap_sram_base + omap_sram_size; 64 omap_sram_ceil = omap_sram_base + omap_sram_size;
59} 65}
60 66
61static struct map_desc omap_sram_io_desc[] __initdata = { 67static struct map_desc omap_sram_io_desc[] __initdata = {
62 { /* .length gets filled in at runtime */ 68 { /* .length gets filled in at runtime */
63 .virtual = OMAP1_SRAM_BASE, 69 .virtual = OMAP1_SRAM_VA,
64 .pfn = __phys_to_pfn(OMAP1_SRAM_START), 70 .pfn = __phys_to_pfn(OMAP1_SRAM_PA),
65 .type = MT_DEVICE 71 .type = MT_DEVICE
66 } 72 }
67}; 73};
@@ -76,10 +82,19 @@ void __init omap_map_sram(void)
76 if (omap_sram_size == 0) 82 if (omap_sram_size == 0)
77 return; 83 return;
78 84
85 if (cpu_is_omap24xx()) {
86 omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;
87 omap_sram_io_desc[0].pfn = __phys_to_pfn(OMAP2_SRAM_PA);
88 }
89
79 omap_sram_io_desc[0].length = (omap_sram_size + PAGE_SIZE-1)/PAGE_SIZE; 90 omap_sram_io_desc[0].length = (omap_sram_size + PAGE_SIZE-1)/PAGE_SIZE;
80 omap_sram_io_desc[0].length *= PAGE_SIZE; 91 omap_sram_io_desc[0].length *= PAGE_SIZE;
81 iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc)); 92 iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
82 93
94 printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
95 omap_sram_io_desc[0].pfn, omap_sram_io_desc[0].virtual,
96 omap_sram_io_desc[0].length);
97
83 /* 98 /*
84 * Looks like we need to preserve some bootloader code at the 99 * Looks like we need to preserve some bootloader code at the
85 * beginning of SRAM for jumping to flash for reboot to work... 100 * beginning of SRAM for jumping to flash for reboot to work...
@@ -88,16 +103,6 @@ void __init omap_map_sram(void)
88 omap_sram_size - SRAM_BOOTLOADER_SZ); 103 omap_sram_size - SRAM_BOOTLOADER_SZ);
89} 104}
90 105
91static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl) = NULL;
92
93void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
94{
95 if (_omap_sram_reprogram_clock == NULL)
96 panic("Cannot use SRAM");
97
98 return _omap_sram_reprogram_clock(dpllctl, ckctl);
99}
100
101void * omap_sram_push(void * start, unsigned long size) 106void * omap_sram_push(void * start, unsigned long size)
102{ 107{
103 if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) { 108 if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) {
@@ -111,10 +116,94 @@ void * omap_sram_push(void * start, unsigned long size)
111 return (void *)omap_sram_ceil; 116 return (void *)omap_sram_ceil;
112} 117}
113 118
114void __init omap_sram_init(void) 119static void omap_sram_error(void)
120{
121 panic("Uninitialized SRAM function\n");
122}
123
124#ifdef CONFIG_ARCH_OMAP1
125
126static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
127
128void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
129{
130 if (!_omap_sram_reprogram_clock)
131 omap_sram_error();
132
133 return _omap_sram_reprogram_clock(dpllctl, ckctl);
134}
135
136int __init omap1_sram_init(void)
115{ 137{
116 omap_detect_sram();
117 omap_map_sram();
118 _omap_sram_reprogram_clock = omap_sram_push(sram_reprogram_clock, 138 _omap_sram_reprogram_clock = omap_sram_push(sram_reprogram_clock,
119 sram_reprogram_clock_sz); 139 sram_reprogram_clock_sz);
140
141 return 0;
142}
143
144#else
145#define omap1_sram_init() do {} while (0)
146#endif
147
148#ifdef CONFIG_ARCH_OMAP2
149
150static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
151 u32 base_cs, u32 force_unlock);
152
153void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
154 u32 base_cs, u32 force_unlock)
155{
156 if (!_omap2_sram_ddr_init)
157 omap_sram_error();
158
159 return _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
160 base_cs, force_unlock);
161}
162
163static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
164 u32 mem_type);
165
166void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
167{
168 if (!_omap2_sram_reprogram_sdrc)
169 omap_sram_error();
170
171 return _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
172}
173
174static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
175
176u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
177{
178 if (!_omap2_set_prcm)
179 omap_sram_error();
180
181 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
182}
183
184int __init omap2_sram_init(void)
185{
186 _omap2_sram_ddr_init = omap_sram_push(sram_ddr_init, sram_ddr_init_sz);
187
188 _omap2_sram_reprogram_sdrc = omap_sram_push(sram_reprogram_sdrc,
189 sram_reprogram_sdrc_sz);
190 _omap2_set_prcm = omap_sram_push(sram_set_prcm, sram_set_prcm_sz);
191
192 return 0;
193}
194#else
195#define omap2_sram_init() do {} while (0)
196#endif
197
198int __init omap_sram_init(void)
199{
200 omap_detect_sram();
201 omap_map_sram();
202
203 if (!cpu_is_omap24xx())
204 omap1_sram_init();
205 else
206 omap2_sram_init();
207
208 return 0;
120} 209}
diff --git a/arch/arm/plat-omap/sram.h b/arch/arm/plat-omap/sram.h
deleted file mode 100644
index 71984efa6ae8..000000000000
--- a/arch/arm/plat-omap/sram.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * linux/arch/arm/plat-omap/sram.h
3 *
4 * Interface for functions that need to be run in internal SRAM
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ARCH_ARM_OMAP_SRAM_H
12#define __ARCH_ARM_OMAP_SRAM_H
13
14extern void * omap_sram_push(void * start, unsigned long size);
15extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
16
17/* Do not use these */
18extern void sram_reprogram_clock(u32 ckctl, u32 dpllctl);
19extern unsigned long sram_reprogram_clock_sz;
20
21#endif
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index 205e2d0b826d..00afc7a8c2ab 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -91,6 +91,8 @@ EXPORT_SYMBOL(otg_set_transceiver);
91 91
92/*-------------------------------------------------------------------------*/ 92/*-------------------------------------------------------------------------*/
93 93
94#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP15XX)
95
94static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device) 96static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
95{ 97{
96 u32 syscon1 = 0; 98 u32 syscon1 = 0;
@@ -271,6 +273,8 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
271 return syscon1 << 24; 273 return syscon1 << 24;
272} 274}
273 275
276#endif
277
274/*-------------------------------------------------------------------------*/ 278/*-------------------------------------------------------------------------*/
275 279
276#if defined(CONFIG_USB_GADGET_OMAP) || \ 280#if defined(CONFIG_USB_GADGET_OMAP) || \
@@ -494,7 +498,7 @@ static inline void omap_otg_init(struct omap_usb_config *config) {}
494 498
495/*-------------------------------------------------------------------------*/ 499/*-------------------------------------------------------------------------*/
496 500
497#ifdef CONFIG_ARCH_OMAP1510 501#ifdef CONFIG_ARCH_OMAP15XX
498 502
499#define ULPD_DPLL_CTRL_REG __REG16(ULPD_DPLL_CTRL) 503#define ULPD_DPLL_CTRL_REG __REG16(ULPD_DPLL_CTRL)
500#define DPLL_IOB (1 << 13) 504#define DPLL_IOB (1 << 13)
@@ -507,7 +511,6 @@ static inline void omap_otg_init(struct omap_usb_config *config) {}
507 511
508static void __init omap_1510_usb_init(struct omap_usb_config *config) 512static void __init omap_1510_usb_init(struct omap_usb_config *config)
509{ 513{
510 int status;
511 unsigned int val; 514 unsigned int val;
512 515
513 omap_usb0_init(config->pins[0], is_usb0_device(config)); 516 omap_usb0_init(config->pins[0], is_usb0_device(config));
@@ -539,6 +542,8 @@ static void __init omap_1510_usb_init(struct omap_usb_config *config)
539 542
540#ifdef CONFIG_USB_GADGET_OMAP 543#ifdef CONFIG_USB_GADGET_OMAP
541 if (config->register_dev) { 544 if (config->register_dev) {
545 int status;
546
542 udc_device.dev.platform_data = config; 547 udc_device.dev.platform_data = config;
543 status = platform_device_register(&udc_device); 548 status = platform_device_register(&udc_device);
544 if (status) 549 if (status)
@@ -549,6 +554,8 @@ static void __init omap_1510_usb_init(struct omap_usb_config *config)
549 554
550#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 555#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
551 if (config->register_host) { 556 if (config->register_host) {
557 int status;
558
552 ohci_device.dev.platform_data = config; 559 ohci_device.dev.platform_data = config;
553 status = platform_device_register(&ohci_device); 560 status = platform_device_register(&ohci_device);
554 if (status) 561 if (status)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-12 09:05:01 -0500