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authorKevin Hilman <khilman@mvista.com>2007-11-13 02:24:05 -0500
committerTony Lindgren <tony@atomide.com>2008-04-14 12:57:12 -0400
commita57fb870c8c4864031d7568f91e882e93238c9cb (patch)
treef6b902a2d4db8658c37034cbffe7eb53623bda7f /arch/arm/plat-omap
parentf258b0c6fa6ca653c7f4e6e2846dbb7ed3af3446 (diff)
ARM: OMAP: Timer32K: Move timer32k to mach-omap1
Move now OMAP1-specific timer32k code to mach-omap1 since OMAP2/3 32k timers are done in gptimer code. Signed-off-by: Kevin Hilman <khilman@mvista.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r--arch/arm/plat-omap/Makefile4
-rw-r--r--arch/arm/plat-omap/timer32k.c201
2 files changed, 0 insertions, 205 deletions
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index d91424edf576..bc639a30d6d1 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -9,10 +9,6 @@ obj-m :=
9obj-n := 9obj-n :=
10obj- := 10obj- :=
11 11
12ifeq ($(CONFIG_ARCH_OMAP1),y)
13obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o
14endif
15
16# OCPI interconnect support for 1710, 1610 and 5912 12# OCPI interconnect support for 1710, 1610 and 5912
17obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o 13obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
18 14
diff --git a/arch/arm/plat-omap/timer32k.c b/arch/arm/plat-omap/timer32k.c
deleted file mode 100644
index 1f7365f5df24..000000000000
--- a/arch/arm/plat-omap/timer32k.c
+++ /dev/null
@@ -1,201 +0,0 @@
1/*
2 * linux/arch/arm/plat-omap/timer32k.c
3 *
4 * OMAP 32K Timer
5 *
6 * Copyright (C) 2004 - 2005 Nokia Corporation
7 * Partial timer rewrite and additional dynamic tick timer support by
8 * Tony Lindgen <tony@atomide.com> and
9 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
10 * OMAP Dual-mode timer framework support by Timo Teras
11 *
12 * MPU timer code based on the older MPU timer code for OMAP
13 * Copyright (C) 2000 RidgeRun, Inc.
14 * Author: Greg Lonnon <glonnon@ridgerun.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * You should have received a copy of the GNU General Public License along
33 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
35 */
36
37#include <linux/kernel.h>
38#include <linux/init.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
41#include <linux/sched.h>
42#include <linux/spinlock.h>
43
44#include <linux/err.h>
45#include <linux/clk.h>
46#include <linux/clocksource.h>
47#include <linux/clockchips.h>
48
49#include <asm/system.h>
50#include <asm/hardware.h>
51#include <asm/io.h>
52#include <asm/leds.h>
53#include <asm/irq.h>
54#include <asm/mach/irq.h>
55#include <asm/mach/time.h>
56#include <asm/arch/dmtimer.h>
57
58struct sys_timer omap_timer;
59
60/*
61 * ---------------------------------------------------------------------------
62 * 32KHz OS timer
63 *
64 * This currently works only on 16xx, as 1510 does not have the continuous
65 * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
66 * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
67 * on 1510 would be possible, but the timer would not be as accurate as
68 * with the 32KHz synchronized timer.
69 * ---------------------------------------------------------------------------
70 */
71
72#if defined(CONFIG_ARCH_OMAP16XX)
73#define TIMER_32K_SYNCHRONIZED 0xfffbc410
74#elif defined(CONFIG_ARCH_OMAP24XX)
75#define TIMER_32K_SYNCHRONIZED (OMAP24XX_32KSYNCT_BASE + 0x10)
76#else
77#error OMAP 32KHz timer does not currently work on 15XX!
78#endif
79
80/* 16xx specific defines */
81#define OMAP1_32K_TIMER_BASE 0xfffb9000
82#define OMAP1_32K_TIMER_CR 0x08
83#define OMAP1_32K_TIMER_TVR 0x00
84#define OMAP1_32K_TIMER_TCR 0x04
85
86#define OMAP_32K_TICKS_PER_SEC (32768)
87
88/*
89 * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
90 * so with HZ = 128, TVR = 255.
91 */
92#define OMAP_32K_TIMER_TICK_PERIOD ((OMAP_32K_TICKS_PER_SEC / HZ) - 1)
93
94#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
95 (((nr_jiffies) * (clock_rate)) / HZ)
96
97static inline void omap_32k_timer_write(int val, int reg)
98{
99 omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
100}
101
102static inline unsigned long omap_32k_timer_read(int reg)
103{
104 return omap_readl(OMAP1_32K_TIMER_BASE + reg) & 0xffffff;
105}
106
107static inline void omap_32k_timer_start(unsigned long load_val)
108{
109 if (!load_val)
110 load_val = 1;
111 omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR);
112 omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR);
113}
114
115static inline void omap_32k_timer_stop(void)
116{
117 omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR);
118}
119
120#define omap_32k_timer_ack_irq()
121
122static void omap_32k_timer_set_mode(enum clock_event_mode mode,
123 struct clock_event_device *evt)
124{
125 omap_32k_timer_stop();
126
127 switch (mode) {
128 case CLOCK_EVT_MODE_PERIODIC:
129 omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
130 break;
131 case CLOCK_EVT_MODE_ONESHOT:
132 case CLOCK_EVT_MODE_UNUSED:
133 case CLOCK_EVT_MODE_SHUTDOWN:
134 break;
135 case CLOCK_EVT_MODE_RESUME:
136 break;
137 }
138}
139
140static struct clock_event_device clockevent_32k_timer = {
141 .name = "32k-timer",
142 .features = CLOCK_EVT_FEAT_PERIODIC,
143 .shift = 32,
144 .set_mode = omap_32k_timer_set_mode,
145};
146
147/*
148 * The 32KHz synchronized timer is an additional timer on 16xx.
149 * It is always running.
150 */
151static inline unsigned long omap_32k_sync_timer_read(void)
152{
153 return omap_readl(TIMER_32K_SYNCHRONIZED);
154}
155
156static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
157{
158 struct clock_event_device *evt = &clockevent_32k_timer;
159 omap_32k_timer_ack_irq();
160
161 evt->event_handler(evt);
162
163 return IRQ_HANDLED;
164}
165
166static struct irqaction omap_32k_timer_irq = {
167 .name = "32KHz timer",
168 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
169 .handler = omap_32k_timer_interrupt,
170};
171
172static __init void omap_init_32k_timer(void)
173{
174 clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC,
175 NSEC_PER_SEC,
176 clockevent_32k_timer.shift);
177 clockevent_32k_timer.max_delta_ns =
178 clockevent_delta2ns(0xfffffffe, &clockevent_32k_timer);
179 clockevent_32k_timer.min_delta_ns =
180 clockevent_delta2ns(1, &clockevent_32k_timer);
181
182 clockevent_32k_timer.cpumask = cpumask_of_cpu(0);
183 clockevents_register_device(&clockevent_32k_timer);
184}
185
186/*
187 * ---------------------------------------------------------------------------
188 * Timer initialization
189 * ---------------------------------------------------------------------------
190 */
191static void __init omap_timer_init(void)
192{
193#ifdef CONFIG_OMAP_DM_TIMER
194 omap_dm_timer_init();
195#endif
196 omap_init_32k_timer();
197}
198
199struct sys_timer omap_timer = {
200 .init = omap_timer_init,
201};