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authorDavid Woodhouse <David.Woodhouse@intel.com>2009-09-20 08:55:36 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2009-09-20 08:55:36 -0400
commit6469f540ea37d53db089c8fea9c0c77a3d9353d4 (patch)
tree1dc9dc077150d57f4424cae49e711b5dd6e903a1 /arch/arm/plat-omap
parent304e6d5fe294b80e6d3107f99ec241816390ebcc (diff)
parent78f28b7c555359c67c2a0d23f7436e915329421e (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts: drivers/mtd/mtdcore.c Merged in order that I can apply the Nomadik nand/onenand support patches.
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r--arch/arm/plat-omap/Kconfig17
-rw-r--r--arch/arm/plat-omap/Makefile6
-rw-r--r--arch/arm/plat-omap/clock.c2
-rw-r--r--arch/arm/plat-omap/common.c95
-rw-r--r--arch/arm/plat-omap/debug-leds.c11
-rw-r--r--arch/arm/plat-omap/dma.c18
-rw-r--r--arch/arm/plat-omap/dmtimer.c5
-rw-r--r--arch/arm/plat-omap/gpio.c378
-rw-r--r--arch/arm/plat-omap/include/mach/board.h2
-rw-r--r--arch/arm/plat-omap/include/mach/clockdomain.h3
-rw-r--r--arch/arm/plat-omap/include/mach/control.h12
-rw-r--r--arch/arm/plat-omap/include/mach/dma.h88
-rw-r--r--arch/arm/plat-omap/include/mach/entry-macro.S8
-rw-r--r--arch/arm/plat-omap/include/mach/gpio.h2
-rw-r--r--arch/arm/plat-omap/include/mach/io.h97
-rw-r--r--arch/arm/plat-omap/include/mach/iommu.h6
-rw-r--r--arch/arm/plat-omap/include/mach/mcbsp.h59
-rw-r--r--arch/arm/plat-omap/include/mach/mtd-xip.h2
-rw-r--r--arch/arm/plat-omap/include/mach/mux.h31
-rw-r--r--arch/arm/plat-omap/include/mach/omap-pm.h301
-rw-r--r--arch/arm/plat-omap/include/mach/omap44xx.h8
-rw-r--r--arch/arm/plat-omap/include/mach/omap_device.h141
-rw-r--r--arch/arm/plat-omap/include/mach/omap_hwmod.h447
-rw-r--r--arch/arm/plat-omap/include/mach/powerdomain.h15
-rw-r--r--arch/arm/plat-omap/include/mach/sdrc.h15
-rw-r--r--arch/arm/plat-omap/include/mach/serial.h3
-rw-r--r--arch/arm/plat-omap/include/mach/system.h2
-rw-r--r--arch/arm/plat-omap/io.c62
-rw-r--r--arch/arm/plat-omap/iommu-debug.c415
-rw-r--r--arch/arm/plat-omap/iommu.c23
-rw-r--r--arch/arm/plat-omap/iovmm.c2
-rw-r--r--arch/arm/plat-omap/mcbsp.c403
-rw-r--r--arch/arm/plat-omap/omap-pm-noop.c296
-rw-r--r--arch/arm/plat-omap/omap_device.c687
-rw-r--r--arch/arm/plat-omap/sram.c20
35 files changed, 3353 insertions, 329 deletions
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index efe85d095190..64b3f52bd9b2 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -120,6 +120,10 @@ config OMAP_MBOX_FWK
120config OMAP_IOMMU 120config OMAP_IOMMU
121 tristate 121 tristate
122 122
123config OMAP_IOMMU_DEBUG
124 depends on OMAP_IOMMU
125 tristate
126
123choice 127choice
124 prompt "System timer" 128 prompt "System timer"
125 default OMAP_MPU_TIMER 129 default OMAP_MPU_TIMER
@@ -183,6 +187,19 @@ config OMAP_SERIAL_WAKE
183 to data on the serial RX line. This allows you to wake the 187 to data on the serial RX line. This allows you to wake the
184 system from serial console. 188 system from serial console.
185 189
190choice
191 prompt "OMAP PM layer selection"
192 depends on ARCH_OMAP
193 default OMAP_PM_NOOP
194
195config OMAP_PM_NONE
196 bool "No PM layer"
197
198config OMAP_PM_NOOP
199 bool "No-op/debug PM layer"
200
201endchoice
202
186endmenu 203endmenu
187 204
188endif 205endif
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index a83279523958..98f01910c2cf 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -12,8 +12,13 @@ obj- :=
12# OCPI interconnect support for 1710, 1610 and 5912 12# OCPI interconnect support for 1710, 1610 and 5912
13obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o 13obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
14 14
15# omap_device support (OMAP2+ only at the moment)
16obj-$(CONFIG_ARCH_OMAP2) += omap_device.o
17obj-$(CONFIG_ARCH_OMAP3) += omap_device.o
18
15obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o 19obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
16obj-$(CONFIG_OMAP_IOMMU) += iommu.o iovmm.o 20obj-$(CONFIG_OMAP_IOMMU) += iommu.o iovmm.o
21obj-$(CONFIG_OMAP_IOMMU_DEBUG) += iommu-debug.o
17 22
18obj-$(CONFIG_CPU_FREQ) += cpu-omap.o 23obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
19obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o 24obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
@@ -25,3 +30,4 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y)
25# OMAP mailbox framework 30# OMAP mailbox framework
26obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o 31obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o
27 32
33obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o \ No newline at end of file
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index e8c327a45a55..bf880e966d3b 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -488,7 +488,7 @@ static int __init clk_debugfs_init(void)
488 } 488 }
489 return 0; 489 return 0;
490err_out: 490err_out:
491 debugfs_remove(clk_debugfs_root); /* REVISIT: Cleanup correctly */ 491 debugfs_remove_recursive(clk_debugfs_root);
492 return err; 492 return err;
493} 493}
494late_initcall(clk_debugfs_init); 494late_initcall(clk_debugfs_init);
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index ebcf006406f9..3a4768d55895 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -54,50 +54,6 @@ static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
54 struct omap_board_config_kernel *kinfo = NULL; 54 struct omap_board_config_kernel *kinfo = NULL;
55 int i; 55 int i;
56 56
57#ifdef CONFIG_OMAP_BOOT_TAG
58 struct omap_board_config_entry *info = NULL;
59
60 if (omap_bootloader_tag_len > 4)
61 info = (struct omap_board_config_entry *) omap_bootloader_tag;
62 while (info != NULL) {
63 u8 *next;
64
65 if (info->tag == tag) {
66 if (skip == 0)
67 break;
68 skip--;
69 }
70
71 if ((info->len & 0x03) != 0) {
72 /* We bail out to avoid an alignment fault */
73 printk(KERN_ERR "OMAP peripheral config: Length (%d) not word-aligned (tag %04x)\n",
74 info->len, info->tag);
75 return NULL;
76 }
77 next = (u8 *) info + sizeof(*info) + info->len;
78 if (next >= omap_bootloader_tag + omap_bootloader_tag_len)
79 info = NULL;
80 else
81 info = (struct omap_board_config_entry *) next;
82 }
83 if (info != NULL) {
84 /* Check the length as a lame attempt to check for
85 * binary inconsistency. */
86 if (len != NO_LENGTH_CHECK) {
87 /* Word-align len */
88 if (len & 0x03)
89 len = (len + 3) & ~0x03;
90 if (info->len != len) {
91 printk(KERN_ERR "OMAP peripheral config: Length mismatch with tag %x (want %d, got %d)\n",
92 tag, len, info->len);
93 return NULL;
94 }
95 }
96 if (len_out != NULL)
97 *len_out = info->len;
98 return info->data;
99 }
100#endif
101 /* Try to find the config from the board-specific structures 57 /* Try to find the config from the board-specific structures
102 * in the kernel. */ 58 * in the kernel. */
103 for (i = 0; i < omap_board_config_size; i++) { 59 for (i = 0; i < omap_board_config_size; i++) {
@@ -127,50 +83,6 @@ const void *omap_get_var_config(u16 tag, size_t *len)
127} 83}
128EXPORT_SYMBOL(omap_get_var_config); 84EXPORT_SYMBOL(omap_get_var_config);
129 85
130static int __init omap_add_serial_console(void)
131{
132 const struct omap_serial_console_config *con_info;
133 const struct omap_uart_config *uart_info;
134 static char speed[11], *opt = NULL;
135 int line, i, uart_idx;
136
137 uart_info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
138 con_info = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
139 struct omap_serial_console_config);
140 if (uart_info == NULL || con_info == NULL)
141 return 0;
142
143 if (con_info->console_uart == 0)
144 return 0;
145
146 if (con_info->console_speed) {
147 snprintf(speed, sizeof(speed), "%u", con_info->console_speed);
148 opt = speed;
149 }
150
151 uart_idx = con_info->console_uart - 1;
152 if (uart_idx >= OMAP_MAX_NR_PORTS) {
153 printk(KERN_INFO "Console: external UART#%d. "
154 "Not adding it as console this time.\n",
155 uart_idx + 1);
156 return 0;
157 }
158 if (!(uart_info->enabled_uarts & (1 << uart_idx))) {
159 printk(KERN_ERR "Console: Selected UART#%d is "
160 "not enabled for this platform\n",
161 uart_idx + 1);
162 return -1;
163 }
164 line = 0;
165 for (i = 0; i < uart_idx; i++) {
166 if (uart_info->enabled_uarts & (1 << i))
167 line++;
168 }
169 return add_preferred_console("ttyS", line, opt);
170}
171console_initcall(omap_add_serial_console);
172
173
174/* 86/*
175 * 32KHz clocksource ... always available, on pretty most chips except 87 * 32KHz clocksource ... always available, on pretty most chips except
176 * OMAP 730 and 1510. Other timers could be used as clocksources, with 88 * OMAP 730 and 1510. Other timers could be used as clocksources, with
@@ -253,11 +165,8 @@ static struct clocksource clocksource_32k = {
253 */ 165 */
254unsigned long long sched_clock(void) 166unsigned long long sched_clock(void)
255{ 167{
256 unsigned long long ret; 168 return clocksource_cyc2ns(clocksource_32k.read(&clocksource_32k),
257 169 clocksource_32k.mult, clocksource_32k.shift);
258 ret = (unsigned long long)clocksource_32k.read(&clocksource_32k);
259 ret = (ret * clocksource_32k.mult_orig) >> clocksource_32k.shift;
260 return ret;
261} 170}
262 171
263static int __init omap_init_clocksource_32k(void) 172static int __init omap_init_clocksource_32k(void)
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index be4eefda4767..9395898dd49a 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -281,24 +281,27 @@ static int /* __init */ fpga_probe(struct platform_device *pdev)
281 return 0; 281 return 0;
282} 282}
283 283
284static int fpga_suspend_late(struct platform_device *pdev, pm_message_t mesg) 284static int fpga_suspend_noirq(struct device *dev)
285{ 285{
286 __raw_writew(~0, &fpga->leds); 286 __raw_writew(~0, &fpga->leds);
287 return 0; 287 return 0;
288} 288}
289 289
290static int fpga_resume_early(struct platform_device *pdev) 290static int fpga_resume_noirq(struct device *dev)
291{ 291{
292 __raw_writew(~hw_led_state, &fpga->leds); 292 __raw_writew(~hw_led_state, &fpga->leds);
293 return 0; 293 return 0;
294} 294}
295 295
296static struct dev_pm_ops fpga_dev_pm_ops = {
297 .suspend_noirq = fpga_suspend_noirq,
298 .resume_noirq = fpga_resume_noirq,
299};
296 300
297static struct platform_driver led_driver = { 301static struct platform_driver led_driver = {
298 .driver.name = "omap_dbg_led", 302 .driver.name = "omap_dbg_led",
303 .driver.pm = &fpga_dev_pm_ops,
299 .probe = fpga_probe, 304 .probe = fpga_probe,
300 .suspend_late = fpga_suspend_late,
301 .resume_early = fpga_resume_early,
302}; 305};
303 306
304static int __init fpga_init(void) 307static int __init fpga_init(void)
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index e3ac94f09006..fd3154ae69b1 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1127,6 +1127,11 @@ int omap_dma_running(void)
1127void omap_dma_link_lch(int lch_head, int lch_queue) 1127void omap_dma_link_lch(int lch_head, int lch_queue)
1128{ 1128{
1129 if (omap_dma_in_1510_mode()) { 1129 if (omap_dma_in_1510_mode()) {
1130 if (lch_head == lch_queue) {
1131 dma_write(dma_read(CCR(lch_head)) | (3 << 8),
1132 CCR(lch_head));
1133 return;
1134 }
1130 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); 1135 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1131 BUG(); 1136 BUG();
1132 return; 1137 return;
@@ -1149,6 +1154,11 @@ EXPORT_SYMBOL(omap_dma_link_lch);
1149void omap_dma_unlink_lch(int lch_head, int lch_queue) 1154void omap_dma_unlink_lch(int lch_head, int lch_queue)
1150{ 1155{
1151 if (omap_dma_in_1510_mode()) { 1156 if (omap_dma_in_1510_mode()) {
1157 if (lch_head == lch_queue) {
1158 dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
1159 CCR(lch_head));
1160 return;
1161 }
1152 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); 1162 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1153 BUG(); 1163 BUG();
1154 return; 1164 return;
@@ -2337,16 +2347,16 @@ static int __init omap_init_dma(void)
2337 int ch, r; 2347 int ch, r;
2338 2348
2339 if (cpu_class_is_omap1()) { 2349 if (cpu_class_is_omap1()) {
2340 omap_dma_base = IO_ADDRESS(OMAP1_DMA_BASE); 2350 omap_dma_base = OMAP1_IO_ADDRESS(OMAP1_DMA_BASE);
2341 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT; 2351 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2342 } else if (cpu_is_omap24xx()) { 2352 } else if (cpu_is_omap24xx()) {
2343 omap_dma_base = IO_ADDRESS(OMAP24XX_DMA4_BASE); 2353 omap_dma_base = OMAP2_IO_ADDRESS(OMAP24XX_DMA4_BASE);
2344 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; 2354 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2345 } else if (cpu_is_omap34xx()) { 2355 } else if (cpu_is_omap34xx()) {
2346 omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE); 2356 omap_dma_base = OMAP2_IO_ADDRESS(OMAP34XX_DMA4_BASE);
2347 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; 2357 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2348 } else if (cpu_is_omap44xx()) { 2358 } else if (cpu_is_omap44xx()) {
2349 omap_dma_base = IO_ADDRESS(OMAP44XX_DMA4_BASE); 2359 omap_dma_base = OMAP2_IO_ADDRESS(OMAP44XX_DMA4_BASE);
2350 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; 2360 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2351 } else { 2361 } else {
2352 pr_err("DMA init failed for unsupported omap\n"); 2362 pr_err("DMA init failed for unsupported omap\n");
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 7f50b6103dee..d325b54daeb5 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -774,7 +774,10 @@ int __init omap_dm_timer_init(void)
774 774
775 for (i = 0; i < dm_timer_count; i++) { 775 for (i = 0; i < dm_timer_count; i++) {
776 timer = &dm_timers[i]; 776 timer = &dm_timers[i];
777 timer->io_base = IO_ADDRESS(timer->phys_base); 777 if (cpu_class_is_omap1())
778 timer->io_base = OMAP1_IO_ADDRESS(timer->phys_base);
779 else
780 timer->io_base = OMAP2_IO_ADDRESS(timer->phys_base);
778#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ 781#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
779 defined(CONFIG_ARCH_OMAP4) 782 defined(CONFIG_ARCH_OMAP4)
780 if (cpu_class_is_omap2()) { 783 if (cpu_class_is_omap2()) {
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 9298bc0ab171..693839c89ad0 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -31,7 +31,7 @@
31/* 31/*
32 * OMAP1510 GPIO registers 32 * OMAP1510 GPIO registers
33 */ 33 */
34#define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000) 34#define OMAP1510_GPIO_BASE OMAP1_IO_ADDRESS(0xfffce000)
35#define OMAP1510_GPIO_DATA_INPUT 0x00 35#define OMAP1510_GPIO_DATA_INPUT 0x00
36#define OMAP1510_GPIO_DATA_OUTPUT 0x04 36#define OMAP1510_GPIO_DATA_OUTPUT 0x04
37#define OMAP1510_GPIO_DIR_CONTROL 0x08 37#define OMAP1510_GPIO_DIR_CONTROL 0x08
@@ -45,10 +45,10 @@
45/* 45/*
46 * OMAP1610 specific GPIO registers 46 * OMAP1610 specific GPIO registers
47 */ 47 */
48#define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400) 48#define OMAP1610_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbe400)
49#define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00) 49#define OMAP1610_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbec00)
50#define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400) 50#define OMAP1610_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbb400)
51#define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00) 51#define OMAP1610_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbbc00)
52#define OMAP1610_GPIO_REVISION 0x0000 52#define OMAP1610_GPIO_REVISION 0x0000
53#define OMAP1610_GPIO_SYSCONFIG 0x0010 53#define OMAP1610_GPIO_SYSCONFIG 0x0010
54#define OMAP1610_GPIO_SYSSTATUS 0x0014 54#define OMAP1610_GPIO_SYSSTATUS 0x0014
@@ -70,12 +70,12 @@
70/* 70/*
71 * OMAP730 specific GPIO registers 71 * OMAP730 specific GPIO registers
72 */ 72 */
73#define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000) 73#define OMAP730_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000)
74#define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800) 74#define OMAP730_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800)
75#define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000) 75#define OMAP730_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000)
76#define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800) 76#define OMAP730_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800)
77#define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000) 77#define OMAP730_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000)
78#define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800) 78#define OMAP730_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800)
79#define OMAP730_GPIO_DATA_INPUT 0x00 79#define OMAP730_GPIO_DATA_INPUT 0x00
80#define OMAP730_GPIO_DATA_OUTPUT 0x04 80#define OMAP730_GPIO_DATA_OUTPUT 0x04
81#define OMAP730_GPIO_DIR_CONTROL 0x08 81#define OMAP730_GPIO_DIR_CONTROL 0x08
@@ -86,12 +86,12 @@
86/* 86/*
87 * OMAP850 specific GPIO registers 87 * OMAP850 specific GPIO registers
88 */ 88 */
89#define OMAP850_GPIO1_BASE IO_ADDRESS(0xfffbc000) 89#define OMAP850_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000)
90#define OMAP850_GPIO2_BASE IO_ADDRESS(0xfffbc800) 90#define OMAP850_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800)
91#define OMAP850_GPIO3_BASE IO_ADDRESS(0xfffbd000) 91#define OMAP850_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000)
92#define OMAP850_GPIO4_BASE IO_ADDRESS(0xfffbd800) 92#define OMAP850_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800)
93#define OMAP850_GPIO5_BASE IO_ADDRESS(0xfffbe000) 93#define OMAP850_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000)
94#define OMAP850_GPIO6_BASE IO_ADDRESS(0xfffbe800) 94#define OMAP850_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800)
95#define OMAP850_GPIO_DATA_INPUT 0x00 95#define OMAP850_GPIO_DATA_INPUT 0x00
96#define OMAP850_GPIO_DATA_OUTPUT 0x04 96#define OMAP850_GPIO_DATA_OUTPUT 0x04
97#define OMAP850_GPIO_DIR_CONTROL 0x08 97#define OMAP850_GPIO_DIR_CONTROL 0x08
@@ -99,19 +99,21 @@
99#define OMAP850_GPIO_INT_MASK 0x10 99#define OMAP850_GPIO_INT_MASK 0x10
100#define OMAP850_GPIO_INT_STATUS 0x14 100#define OMAP850_GPIO_INT_STATUS 0x14
101 101
102#define OMAP1_MPUIO_VBASE OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE)
103
102/* 104/*
103 * omap24xx specific GPIO registers 105 * omap24xx specific GPIO registers
104 */ 106 */
105#define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000) 107#define OMAP242X_GPIO1_BASE OMAP2_IO_ADDRESS(0x48018000)
106#define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000) 108#define OMAP242X_GPIO2_BASE OMAP2_IO_ADDRESS(0x4801a000)
107#define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000) 109#define OMAP242X_GPIO3_BASE OMAP2_IO_ADDRESS(0x4801c000)
108#define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000) 110#define OMAP242X_GPIO4_BASE OMAP2_IO_ADDRESS(0x4801e000)
109 111
110#define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000) 112#define OMAP243X_GPIO1_BASE OMAP2_IO_ADDRESS(0x4900C000)
111#define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000) 113#define OMAP243X_GPIO2_BASE OMAP2_IO_ADDRESS(0x4900E000)
112#define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000) 114#define OMAP243X_GPIO3_BASE OMAP2_IO_ADDRESS(0x49010000)
113#define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000) 115#define OMAP243X_GPIO4_BASE OMAP2_IO_ADDRESS(0x49012000)
114#define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000) 116#define OMAP243X_GPIO5_BASE OMAP2_IO_ADDRESS(0x480B6000)
115 117
116#define OMAP24XX_GPIO_REVISION 0x0000 118#define OMAP24XX_GPIO_REVISION 0x0000
117#define OMAP24XX_GPIO_SYSCONFIG 0x0010 119#define OMAP24XX_GPIO_SYSCONFIG 0x0010
@@ -138,28 +140,52 @@
138#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 140#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
139#define OMAP24XX_GPIO_SETDATAOUT 0x0094 141#define OMAP24XX_GPIO_SETDATAOUT 0x0094
140 142
143#define OMAP4_GPIO_REVISION 0x0000
144#define OMAP4_GPIO_SYSCONFIG 0x0010
145#define OMAP4_GPIO_EOI 0x0020
146#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
147#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
148#define OMAP4_GPIO_IRQSTATUS0 0x002c
149#define OMAP4_GPIO_IRQSTATUS1 0x0030
150#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
151#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
152#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
153#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
154#define OMAP4_GPIO_IRQWAKEN0 0x0044
155#define OMAP4_GPIO_IRQWAKEN1 0x0048
156#define OMAP4_GPIO_SYSSTATUS 0x0104
157#define OMAP4_GPIO_CTRL 0x0130
158#define OMAP4_GPIO_OE 0x0134
159#define OMAP4_GPIO_DATAIN 0x0138
160#define OMAP4_GPIO_DATAOUT 0x013c
161#define OMAP4_GPIO_LEVELDETECT0 0x0140
162#define OMAP4_GPIO_LEVELDETECT1 0x0144
163#define OMAP4_GPIO_RISINGDETECT 0x0148
164#define OMAP4_GPIO_FALLINGDETECT 0x014c
165#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
166#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
167#define OMAP4_GPIO_CLEARDATAOUT 0x0190
168#define OMAP4_GPIO_SETDATAOUT 0x0194
141/* 169/*
142 * omap34xx specific GPIO registers 170 * omap34xx specific GPIO registers
143 */ 171 */
144 172
145#define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000) 173#define OMAP34XX_GPIO1_BASE OMAP2_IO_ADDRESS(0x48310000)
146#define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000) 174#define OMAP34XX_GPIO2_BASE OMAP2_IO_ADDRESS(0x49050000)
147#define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000) 175#define OMAP34XX_GPIO3_BASE OMAP2_IO_ADDRESS(0x49052000)
148#define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000) 176#define OMAP34XX_GPIO4_BASE OMAP2_IO_ADDRESS(0x49054000)
149#define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000) 177#define OMAP34XX_GPIO5_BASE OMAP2_IO_ADDRESS(0x49056000)
150#define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000) 178#define OMAP34XX_GPIO6_BASE OMAP2_IO_ADDRESS(0x49058000)
151 179
152/* 180/*
153 * OMAP44XX specific GPIO registers 181 * OMAP44XX specific GPIO registers
154 */ 182 */
155#define OMAP44XX_GPIO1_BASE IO_ADDRESS(0x4a310000) 183#define OMAP44XX_GPIO1_BASE OMAP2_IO_ADDRESS(0x4a310000)
156#define OMAP44XX_GPIO2_BASE IO_ADDRESS(0x48055000) 184#define OMAP44XX_GPIO2_BASE OMAP2_IO_ADDRESS(0x48055000)
157#define OMAP44XX_GPIO3_BASE IO_ADDRESS(0x48057000) 185#define OMAP44XX_GPIO3_BASE OMAP2_IO_ADDRESS(0x48057000)
158#define OMAP44XX_GPIO4_BASE IO_ADDRESS(0x48059000) 186#define OMAP44XX_GPIO4_BASE OMAP2_IO_ADDRESS(0x48059000)
159#define OMAP44XX_GPIO5_BASE IO_ADDRESS(0x4805B000) 187#define OMAP44XX_GPIO5_BASE OMAP2_IO_ADDRESS(0x4805B000)
160#define OMAP44XX_GPIO6_BASE IO_ADDRESS(0x4805D000) 188#define OMAP44XX_GPIO6_BASE OMAP2_IO_ADDRESS(0x4805D000)
161
162#define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
163 189
164struct gpio_bank { 190struct gpio_bank {
165 void __iomem *base; 191 void __iomem *base;
@@ -195,7 +221,7 @@ struct gpio_bank {
195 221
196#ifdef CONFIG_ARCH_OMAP16XX 222#ifdef CONFIG_ARCH_OMAP16XX
197static struct gpio_bank gpio_bank_1610[5] = { 223static struct gpio_bank gpio_bank_1610[5] = {
198 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO}, 224 { OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
199 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 }, 225 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
200 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 }, 226 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
201 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 }, 227 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
@@ -205,14 +231,14 @@ static struct gpio_bank gpio_bank_1610[5] = {
205 231
206#ifdef CONFIG_ARCH_OMAP15XX 232#ifdef CONFIG_ARCH_OMAP15XX
207static struct gpio_bank gpio_bank_1510[2] = { 233static struct gpio_bank gpio_bank_1510[2] = {
208 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, 234 { OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
209 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 } 235 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
210}; 236};
211#endif 237#endif
212 238
213#ifdef CONFIG_ARCH_OMAP730 239#ifdef CONFIG_ARCH_OMAP730
214static struct gpio_bank gpio_bank_730[7] = { 240static struct gpio_bank gpio_bank_730[7] = {
215 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, 241 { OMAP1_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
216 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 }, 242 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
217 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 }, 243 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
218 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 }, 244 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
@@ -224,7 +250,7 @@ static struct gpio_bank gpio_bank_730[7] = {
224 250
225#ifdef CONFIG_ARCH_OMAP850 251#ifdef CONFIG_ARCH_OMAP850
226static struct gpio_bank gpio_bank_850[7] = { 252static struct gpio_bank gpio_bank_850[7] = {
227 { OMAP_MPUIO_BASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, 253 { OMAP1_MPUIO_BASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
228 { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 }, 254 { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 },
229 { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 }, 255 { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 },
230 { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 }, 256 { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 },
@@ -386,12 +412,16 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
386 reg += OMAP850_GPIO_DIR_CONTROL; 412 reg += OMAP850_GPIO_DIR_CONTROL;
387 break; 413 break;
388#endif 414#endif
389#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 415#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
390 defined(CONFIG_ARCH_OMAP4)
391 case METHOD_GPIO_24XX: 416 case METHOD_GPIO_24XX:
392 reg += OMAP24XX_GPIO_OE; 417 reg += OMAP24XX_GPIO_OE;
393 break; 418 break;
394#endif 419#endif
420#if defined(CONFIG_ARCH_OMAP4)
421 case METHOD_GPIO_24XX:
422 reg += OMAP4_GPIO_OE;
423 break;
424#endif
395 default: 425 default:
396 WARN_ON(1); 426 WARN_ON(1);
397 return; 427 return;
@@ -459,8 +489,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
459 l &= ~(1 << gpio); 489 l &= ~(1 << gpio);
460 break; 490 break;
461#endif 491#endif
462#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 492#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
463 defined(CONFIG_ARCH_OMAP4)
464 case METHOD_GPIO_24XX: 493 case METHOD_GPIO_24XX:
465 if (enable) 494 if (enable)
466 reg += OMAP24XX_GPIO_SETDATAOUT; 495 reg += OMAP24XX_GPIO_SETDATAOUT;
@@ -469,6 +498,15 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
469 l = 1 << gpio; 498 l = 1 << gpio;
470 break; 499 break;
471#endif 500#endif
501#ifdef CONFIG_ARCH_OMAP4
502 case METHOD_GPIO_24XX:
503 if (enable)
504 reg += OMAP4_GPIO_SETDATAOUT;
505 else
506 reg += OMAP4_GPIO_CLEARDATAOUT;
507 l = 1 << gpio;
508 break;
509#endif
472 default: 510 default:
473 WARN_ON(1); 511 WARN_ON(1);
474 return; 512 return;
@@ -509,12 +547,16 @@ static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
509 reg += OMAP850_GPIO_DATA_INPUT; 547 reg += OMAP850_GPIO_DATA_INPUT;
510 break; 548 break;
511#endif 549#endif
512#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 550#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
513 defined(CONFIG_ARCH_OMAP4)
514 case METHOD_GPIO_24XX: 551 case METHOD_GPIO_24XX:
515 reg += OMAP24XX_GPIO_DATAIN; 552 reg += OMAP24XX_GPIO_DATAIN;
516 break; 553 break;
517#endif 554#endif
555#ifdef CONFIG_ARCH_OMAP4
556 case METHOD_GPIO_24XX:
557 reg += OMAP4_GPIO_DATAIN;
558 break;
559#endif
518 default: 560 default:
519 return -EINVAL; 561 return -EINVAL;
520 } 562 }
@@ -589,7 +631,11 @@ void omap_set_gpio_debounce(int gpio, int enable)
589 631
590 bank = get_gpio_bank(gpio); 632 bank = get_gpio_bank(gpio);
591 reg = bank->base; 633 reg = bank->base;
634#ifdef CONFIG_ARCH_OMAP4
635 reg += OMAP4_GPIO_DEBOUNCENABLE;
636#else
592 reg += OMAP24XX_GPIO_DEBOUNCE_EN; 637 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
638#endif
593 639
594 spin_lock_irqsave(&bank->lock, flags); 640 spin_lock_irqsave(&bank->lock, flags);
595 val = __raw_readl(reg); 641 val = __raw_readl(reg);
@@ -626,7 +672,11 @@ void omap_set_gpio_debounce_time(int gpio, int enc_time)
626 reg = bank->base; 672 reg = bank->base;
627 673
628 enc_time &= 0xff; 674 enc_time &= 0xff;
675#ifdef CONFIG_ARCH_OMAP4
676 reg += OMAP4_GPIO_DEBOUNCINGTIME;
677#else
629 reg += OMAP24XX_GPIO_DEBOUNCE_VAL; 678 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
679#endif
630 __raw_writel(enc_time, reg); 680 __raw_writel(enc_time, reg);
631} 681}
632EXPORT_SYMBOL(omap_set_gpio_debounce_time); 682EXPORT_SYMBOL(omap_set_gpio_debounce_time);
@@ -638,23 +688,46 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
638{ 688{
639 void __iomem *base = bank->base; 689 void __iomem *base = bank->base;
640 u32 gpio_bit = 1 << gpio; 690 u32 gpio_bit = 1 << gpio;
691 u32 val;
641 692
642 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, 693 if (cpu_is_omap44xx()) {
643 trigger & IRQ_TYPE_LEVEL_LOW); 694 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
644 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, 695 trigger & IRQ_TYPE_LEVEL_LOW);
645 trigger & IRQ_TYPE_LEVEL_HIGH); 696 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
646 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, 697 trigger & IRQ_TYPE_LEVEL_HIGH);
647 trigger & IRQ_TYPE_EDGE_RISING); 698 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
648 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, 699 trigger & IRQ_TYPE_EDGE_RISING);
649 trigger & IRQ_TYPE_EDGE_FALLING); 700 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
650 701 trigger & IRQ_TYPE_EDGE_FALLING);
702 } else {
703 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
704 trigger & IRQ_TYPE_LEVEL_LOW);
705 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
706 trigger & IRQ_TYPE_LEVEL_HIGH);
707 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
708 trigger & IRQ_TYPE_EDGE_RISING);
709 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
710 trigger & IRQ_TYPE_EDGE_FALLING);
711 }
651 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { 712 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
652 if (trigger != 0) 713 if (cpu_is_omap44xx()) {
653 __raw_writel(1 << gpio, bank->base 714 if (trigger != 0)
715 __raw_writel(1 << gpio, bank->base+
716 OMAP4_GPIO_IRQWAKEN0);
717 else {
718 val = __raw_readl(bank->base +
719 OMAP4_GPIO_IRQWAKEN0);
720 __raw_writel(val & (~(1 << gpio)), bank->base +
721 OMAP4_GPIO_IRQWAKEN0);
722 }
723 } else {
724 if (trigger != 0)
725 __raw_writel(1 << gpio, bank->base
654 + OMAP24XX_GPIO_SETWKUENA); 726 + OMAP24XX_GPIO_SETWKUENA);
655 else 727 else
656 __raw_writel(1 << gpio, bank->base 728 __raw_writel(1 << gpio, bank->base
657 + OMAP24XX_GPIO_CLEARWKUENA); 729 + OMAP24XX_GPIO_CLEARWKUENA);
730 }
658 } else { 731 } else {
659 if (trigger != 0) 732 if (trigger != 0)
660 bank->enabled_non_wakeup_gpios |= gpio_bit; 733 bank->enabled_non_wakeup_gpios |= gpio_bit;
@@ -662,9 +735,15 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
662 bank->enabled_non_wakeup_gpios &= ~gpio_bit; 735 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
663 } 736 }
664 737
665 bank->level_mask = 738 if (cpu_is_omap44xx()) {
666 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) | 739 bank->level_mask =
667 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); 740 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
741 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
742 } else {
743 bank->level_mask =
744 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
745 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
746 }
668} 747}
669#endif 748#endif
670 749
@@ -828,12 +907,16 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
828 reg += OMAP850_GPIO_INT_STATUS; 907 reg += OMAP850_GPIO_INT_STATUS;
829 break; 908 break;
830#endif 909#endif
831#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 910#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
832 defined(CONFIG_ARCH_OMAP4)
833 case METHOD_GPIO_24XX: 911 case METHOD_GPIO_24XX:
834 reg += OMAP24XX_GPIO_IRQSTATUS1; 912 reg += OMAP24XX_GPIO_IRQSTATUS1;
835 break; 913 break;
836#endif 914#endif
915#if defined(CONFIG_ARCH_OMAP4)
916 case METHOD_GPIO_24XX:
917 reg += OMAP4_GPIO_IRQSTATUS0;
918 break;
919#endif
837 default: 920 default:
838 WARN_ON(1); 921 WARN_ON(1);
839 return; 922 return;
@@ -843,12 +926,16 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
843 /* Workaround for clearing DSP GPIO interrupts to allow retention */ 926 /* Workaround for clearing DSP GPIO interrupts to allow retention */
844#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 927#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
845 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; 928 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
846 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 929#endif
930#if defined(CONFIG_ARCH_OMAP4)
931 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
932#endif
933 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
847 __raw_writel(gpio_mask, reg); 934 __raw_writel(gpio_mask, reg);
848 935
849 /* Flush posted write for the irq status to avoid spurious interrupts */ 936 /* Flush posted write for the irq status to avoid spurious interrupts */
850 __raw_readl(reg); 937 __raw_readl(reg);
851#endif 938 }
852} 939}
853 940
854static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) 941static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
@@ -898,13 +985,18 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
898 inv = 1; 985 inv = 1;
899 break; 986 break;
900#endif 987#endif
901#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 988#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
902 defined(CONFIG_ARCH_OMAP4)
903 case METHOD_GPIO_24XX: 989 case METHOD_GPIO_24XX:
904 reg += OMAP24XX_GPIO_IRQENABLE1; 990 reg += OMAP24XX_GPIO_IRQENABLE1;
905 mask = 0xffffffff; 991 mask = 0xffffffff;
906 break; 992 break;
907#endif 993#endif
994#if defined(CONFIG_ARCH_OMAP4)
995 case METHOD_GPIO_24XX:
996 reg += OMAP4_GPIO_IRQSTATUSSET0;
997 mask = 0xffffffff;
998 break;
999#endif
908 default: 1000 default:
909 WARN_ON(1); 1001 WARN_ON(1);
910 return 0; 1002 return 0;
@@ -972,8 +1064,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
972 l |= gpio_mask; 1064 l |= gpio_mask;
973 break; 1065 break;
974#endif 1066#endif
975#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1067#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
976 defined(CONFIG_ARCH_OMAP4)
977 case METHOD_GPIO_24XX: 1068 case METHOD_GPIO_24XX:
978 if (enable) 1069 if (enable)
979 reg += OMAP24XX_GPIO_SETIRQENABLE1; 1070 reg += OMAP24XX_GPIO_SETIRQENABLE1;
@@ -982,6 +1073,15 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
982 l = gpio_mask; 1073 l = gpio_mask;
983 break; 1074 break;
984#endif 1075#endif
1076#ifdef CONFIG_ARCH_OMAP4
1077 case METHOD_GPIO_24XX:
1078 if (enable)
1079 reg += OMAP4_GPIO_IRQSTATUSSET0;
1080 else
1081 reg += OMAP4_GPIO_IRQSTATUSCLR0;
1082 l = gpio_mask;
1083 break;
1084#endif
985 default: 1085 default:
986 WARN_ON(1); 1086 WARN_ON(1);
987 return; 1087 return;
@@ -1157,11 +1257,14 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1157 if (bank->method == METHOD_GPIO_850) 1257 if (bank->method == METHOD_GPIO_850)
1158 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS; 1258 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
1159#endif 1259#endif
1160#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1260#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1161 defined(CONFIG_ARCH_OMAP4)
1162 if (bank->method == METHOD_GPIO_24XX) 1261 if (bank->method == METHOD_GPIO_24XX)
1163 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; 1262 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1164#endif 1263#endif
1264#if defined(CONFIG_ARCH_OMAP4)
1265 if (bank->method == METHOD_GPIO_24XX)
1266 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1267#endif
1165 while(1) { 1268 while(1) {
1166 u32 isr_saved, level_mask = 0; 1269 u32 isr_saved, level_mask = 0;
1167 u32 enabled; 1270 u32 enabled;
@@ -1315,8 +1418,9 @@ static struct irq_chip mpuio_irq_chip = {
1315 1418
1316#include <linux/platform_device.h> 1419#include <linux/platform_device.h>
1317 1420
1318static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg) 1421static int omap_mpuio_suspend_noirq(struct device *dev)
1319{ 1422{
1423 struct platform_device *pdev = to_platform_device(dev);
1320 struct gpio_bank *bank = platform_get_drvdata(pdev); 1424 struct gpio_bank *bank = platform_get_drvdata(pdev);
1321 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; 1425 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1322 unsigned long flags; 1426 unsigned long flags;
@@ -1329,8 +1433,9 @@ static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t me
1329 return 0; 1433 return 0;
1330} 1434}
1331 1435
1332static int omap_mpuio_resume_early(struct platform_device *pdev) 1436static int omap_mpuio_resume_noirq(struct device *dev)
1333{ 1437{
1438 struct platform_device *pdev = to_platform_device(dev);
1334 struct gpio_bank *bank = platform_get_drvdata(pdev); 1439 struct gpio_bank *bank = platform_get_drvdata(pdev);
1335 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; 1440 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1336 unsigned long flags; 1441 unsigned long flags;
@@ -1342,14 +1447,18 @@ static int omap_mpuio_resume_early(struct platform_device *pdev)
1342 return 0; 1447 return 0;
1343} 1448}
1344 1449
1450static struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1451 .suspend_noirq = omap_mpuio_suspend_noirq,
1452 .resume_noirq = omap_mpuio_resume_noirq,
1453};
1454
1345/* use platform_driver for this, now that there's no longer any 1455/* use platform_driver for this, now that there's no longer any
1346 * point to sys_device (other than not disturbing old code). 1456 * point to sys_device (other than not disturbing old code).
1347 */ 1457 */
1348static struct platform_driver omap_mpuio_driver = { 1458static struct platform_driver omap_mpuio_driver = {
1349 .suspend_late = omap_mpuio_suspend_late,
1350 .resume_early = omap_mpuio_resume_early,
1351 .driver = { 1459 .driver = {
1352 .name = "mpuio", 1460 .name = "mpuio",
1461 .pm = &omap_mpuio_dev_pm_ops,
1353 }, 1462 },
1354}; 1463};
1355 1464
@@ -1638,7 +1747,7 @@ static int __init _omap_gpio_init(void)
1638 1747
1639 gpio_bank_count = OMAP34XX_NR_GPIOS; 1748 gpio_bank_count = OMAP34XX_NR_GPIOS;
1640 gpio_bank = gpio_bank_44xx; 1749 gpio_bank = gpio_bank_44xx;
1641 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); 1750 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1642 printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n", 1751 printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
1643 (rev >> 4) & 0x0f, rev & 0x0f); 1752 (rev >> 4) & 0x0f, rev & 0x0f);
1644 } 1753 }
@@ -1672,7 +1781,16 @@ static int __init _omap_gpio_init(void)
1672 static const u32 non_wakeup_gpios[] = { 1781 static const u32 non_wakeup_gpios[] = {
1673 0xe203ffc0, 0x08700040 1782 0xe203ffc0, 0x08700040
1674 }; 1783 };
1675 1784 if (cpu_is_omap44xx()) {
1785 __raw_writel(0xffffffff, bank->base +
1786 OMAP4_GPIO_IRQSTATUSCLR0);
1787 __raw_writew(0x0015, bank->base +
1788 OMAP4_GPIO_SYSCONFIG);
1789 __raw_writel(0x00000000, bank->base +
1790 OMAP4_GPIO_DEBOUNCENABLE);
1791 /* Initialize interface clock ungated, module enabled */
1792 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1793 } else {
1676 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1); 1794 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1677 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1); 1795 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1678 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG); 1796 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
@@ -1680,12 +1798,12 @@ static int __init _omap_gpio_init(void)
1680 1798
1681 /* Initialize interface clock ungated, module enabled */ 1799 /* Initialize interface clock ungated, module enabled */
1682 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); 1800 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1801 }
1683 if (i < ARRAY_SIZE(non_wakeup_gpios)) 1802 if (i < ARRAY_SIZE(non_wakeup_gpios))
1684 bank->non_wakeup_gpios = non_wakeup_gpios[i]; 1803 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1685 gpio_count = 32; 1804 gpio_count = 32;
1686 } 1805 }
1687#endif 1806#endif
1688
1689 /* REVISIT eventually switch from OMAP-specific gpio structs 1807 /* REVISIT eventually switch from OMAP-specific gpio structs
1690 * over to the generic ones 1808 * over to the generic ones
1691 */ 1809 */
@@ -1771,14 +1889,20 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1771 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1889 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1772 break; 1890 break;
1773#endif 1891#endif
1774#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1892#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1775 defined(CONFIG_ARCH_OMAP4)
1776 case METHOD_GPIO_24XX: 1893 case METHOD_GPIO_24XX:
1777 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; 1894 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1778 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1895 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1779 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; 1896 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1780 break; 1897 break;
1781#endif 1898#endif
1899#ifdef CONFIG_ARCH_OMAP4
1900 case METHOD_GPIO_24XX:
1901 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1902 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1903 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1904 break;
1905#endif
1782 default: 1906 default:
1783 continue; 1907 continue;
1784 } 1908 }
@@ -1813,13 +1937,18 @@ static int omap_gpio_resume(struct sys_device *dev)
1813 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1937 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1814 break; 1938 break;
1815#endif 1939#endif
1816#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1940#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1817 defined(CONFIG_ARCH_OMAP4)
1818 case METHOD_GPIO_24XX: 1941 case METHOD_GPIO_24XX:
1819 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1942 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1820 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; 1943 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1821 break; 1944 break;
1822#endif 1945#endif
1946#ifdef CONFIG_ARCH_OMAP4
1947 case METHOD_GPIO_24XX:
1948 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1949 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1950 break;
1951#endif
1823 default: 1952 default:
1824 continue; 1953 continue;
1825 } 1954 }
@@ -1863,21 +1992,29 @@ void omap2_gpio_prepare_for_retention(void)
1863 1992
1864 if (!(bank->enabled_non_wakeup_gpios)) 1993 if (!(bank->enabled_non_wakeup_gpios))
1865 continue; 1994 continue;
1866#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1995#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1867 defined(CONFIG_ARCH_OMAP4)
1868 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); 1996 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1869 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1997 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1870 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); 1998 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1871#endif 1999#endif
2000#ifdef CONFIG_ARCH_OMAP4
2001 bank->saved_datain = __raw_readl(bank->base +
2002 OMAP4_GPIO_DATAIN);
2003 l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT);
2004 l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT);
2005#endif
1872 bank->saved_fallingdetect = l1; 2006 bank->saved_fallingdetect = l1;
1873 bank->saved_risingdetect = l2; 2007 bank->saved_risingdetect = l2;
1874 l1 &= ~bank->enabled_non_wakeup_gpios; 2008 l1 &= ~bank->enabled_non_wakeup_gpios;
1875 l2 &= ~bank->enabled_non_wakeup_gpios; 2009 l2 &= ~bank->enabled_non_wakeup_gpios;
1876#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 2010#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1877 defined(CONFIG_ARCH_OMAP4)
1878 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT); 2011 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1879 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT); 2012 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1880#endif 2013#endif
2014#ifdef CONFIG_ARCH_OMAP4
2015 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
2016 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
2017#endif
1881 c++; 2018 c++;
1882 } 2019 }
1883 if (!c) { 2020 if (!c) {
@@ -1895,38 +2032,73 @@ void omap2_gpio_resume_after_retention(void)
1895 return; 2032 return;
1896 for (i = 0; i < gpio_bank_count; i++) { 2033 for (i = 0; i < gpio_bank_count; i++) {
1897 struct gpio_bank *bank = &gpio_bank[i]; 2034 struct gpio_bank *bank = &gpio_bank[i];
1898 u32 l; 2035 u32 l, gen, gen0, gen1;
1899 2036
1900 if (!(bank->enabled_non_wakeup_gpios)) 2037 if (!(bank->enabled_non_wakeup_gpios))
1901 continue; 2038 continue;
1902#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 2039#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1903 defined(CONFIG_ARCH_OMAP4)
1904 __raw_writel(bank->saved_fallingdetect, 2040 __raw_writel(bank->saved_fallingdetect,
1905 bank->base + OMAP24XX_GPIO_FALLINGDETECT); 2041 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1906 __raw_writel(bank->saved_risingdetect, 2042 __raw_writel(bank->saved_risingdetect,
1907 bank->base + OMAP24XX_GPIO_RISINGDETECT); 2043 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2044 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
2045#endif
2046#ifdef CONFIG_ARCH_OMAP4
2047 __raw_writel(bank->saved_fallingdetect,
2048 bank->base + OMAP4_GPIO_FALLINGDETECT);
2049 __raw_writel(bank->saved_risingdetect,
2050 bank->base + OMAP4_GPIO_RISINGDETECT);
2051 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1908#endif 2052#endif
1909 /* Check if any of the non-wakeup interrupt GPIOs have changed 2053 /* Check if any of the non-wakeup interrupt GPIOs have changed
1910 * state. If so, generate an IRQ by software. This is 2054 * state. If so, generate an IRQ by software. This is
1911 * horribly racy, but it's the best we can do to work around 2055 * horribly racy, but it's the best we can do to work around
1912 * this silicon bug. */ 2056 * this silicon bug. */
1913#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1914 defined(CONFIG_ARCH_OMAP4)
1915 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1916#endif
1917 l ^= bank->saved_datain; 2057 l ^= bank->saved_datain;
1918 l &= bank->non_wakeup_gpios; 2058 l &= bank->non_wakeup_gpios;
1919 if (l) { 2059
2060 /*
2061 * No need to generate IRQs for the rising edge for gpio IRQs
2062 * configured with falling edge only; and vice versa.
2063 */
2064 gen0 = l & bank->saved_fallingdetect;
2065 gen0 &= bank->saved_datain;
2066
2067 gen1 = l & bank->saved_risingdetect;
2068 gen1 &= ~(bank->saved_datain);
2069
2070 /* FIXME: Consider GPIO IRQs with level detections properly! */
2071 gen = l & (~(bank->saved_fallingdetect) &
2072 ~(bank->saved_risingdetect));
2073 /* Consider all GPIO IRQs needed to be updated */
2074 gen |= gen0 | gen1;
2075
2076 if (gen) {
1920 u32 old0, old1; 2077 u32 old0, old1;
1921#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 2078#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1922 defined(CONFIG_ARCH_OMAP4)
1923 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); 2079 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1924 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); 2080 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1925 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0); 2081 __raw_writel(old0 | gen, bank->base +
1926 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1); 2082 OMAP24XX_GPIO_LEVELDETECT0);
2083 __raw_writel(old1 | gen, bank->base +
2084 OMAP24XX_GPIO_LEVELDETECT1);
1927 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0); 2085 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1928 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1); 2086 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1929#endif 2087#endif
2088#ifdef CONFIG_ARCH_OMAP4
2089 old0 = __raw_readl(bank->base +
2090 OMAP4_GPIO_LEVELDETECT0);
2091 old1 = __raw_readl(bank->base +
2092 OMAP4_GPIO_LEVELDETECT1);
2093 __raw_writel(old0 | l, bank->base +
2094 OMAP4_GPIO_LEVELDETECT0);
2095 __raw_writel(old1 | l, bank->base +
2096 OMAP4_GPIO_LEVELDETECT1);
2097 __raw_writel(old0, bank->base +
2098 OMAP4_GPIO_LEVELDETECT0);
2099 __raw_writel(old1, bank->base +
2100 OMAP4_GPIO_LEVELDETECT1);
2101#endif
1930 } 2102 }
1931 } 2103 }
1932 2104
diff --git a/arch/arm/plat-omap/include/mach/board.h b/arch/arm/plat-omap/include/mach/board.h
index 50ea79a0efa2..8e913c322810 100644
--- a/arch/arm/plat-omap/include/mach/board.h
+++ b/arch/arm/plat-omap/include/mach/board.h
@@ -16,10 +16,8 @@
16 16
17/* Different peripheral ids */ 17/* Different peripheral ids */
18#define OMAP_TAG_CLOCK 0x4f01 18#define OMAP_TAG_CLOCK 0x4f01
19#define OMAP_TAG_SERIAL_CONSOLE 0x4f03
20#define OMAP_TAG_LCD 0x4f05 19#define OMAP_TAG_LCD 0x4f05
21#define OMAP_TAG_GPIO_SWITCH 0x4f06 20#define OMAP_TAG_GPIO_SWITCH 0x4f06
22#define OMAP_TAG_UART 0x4f07
23#define OMAP_TAG_FBMEM 0x4f08 21#define OMAP_TAG_FBMEM 0x4f08
24#define OMAP_TAG_STI_CONSOLE 0x4f09 22#define OMAP_TAG_STI_CONSOLE 0x4f09
25#define OMAP_TAG_CAMERA_SENSOR 0x4f0a 23#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
diff --git a/arch/arm/plat-omap/include/mach/clockdomain.h b/arch/arm/plat-omap/include/mach/clockdomain.h
index b9d0dd2da89b..99ebd886f134 100644
--- a/arch/arm/plat-omap/include/mach/clockdomain.h
+++ b/arch/arm/plat-omap/include/mach/clockdomain.h
@@ -95,7 +95,8 @@ int clkdm_register(struct clockdomain *clkdm);
95int clkdm_unregister(struct clockdomain *clkdm); 95int clkdm_unregister(struct clockdomain *clkdm);
96struct clockdomain *clkdm_lookup(const char *name); 96struct clockdomain *clkdm_lookup(const char *name);
97 97
98int clkdm_for_each(int (*fn)(struct clockdomain *clkdm)); 98int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
99 void *user);
99struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm); 100struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
100 101
101void omap2_clkdm_allow_idle(struct clockdomain *clkdm); 102void omap2_clkdm_allow_idle(struct clockdomain *clkdm);
diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h
index 8140dbccb7bc..826d317cdbec 100644
--- a/arch/arm/plat-omap/include/mach/control.h
+++ b/arch/arm/plat-omap/include/mach/control.h
@@ -20,15 +20,15 @@
20 20
21#ifndef __ASSEMBLY__ 21#ifndef __ASSEMBLY__
22#define OMAP242X_CTRL_REGADDR(reg) \ 22#define OMAP242X_CTRL_REGADDR(reg) \
23 IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 23 OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
24#define OMAP243X_CTRL_REGADDR(reg) \ 24#define OMAP243X_CTRL_REGADDR(reg) \
25 IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 25 OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
26#define OMAP343X_CTRL_REGADDR(reg) \ 26#define OMAP343X_CTRL_REGADDR(reg) \
27 IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 27 OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
28#else 28#else
29#define OMAP242X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 29#define OMAP242X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
30#define OMAP243X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 30#define OMAP243X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
31#define OMAP343X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 31#define OMAP343X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
32#endif /* __ASSEMBLY__ */ 32#endif /* __ASSEMBLY__ */
33 33
34/* 34/*
diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/mach/dma.h
index 7b939cc01962..72f680b7180d 100644
--- a/arch/arm/plat-omap/include/mach/dma.h
+++ b/arch/arm/plat-omap/include/mach/dma.h
@@ -122,6 +122,11 @@
122#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0) 122#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0)
123#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4) 123#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4)
124 124
125/* Additional registers available on OMAP4 */
126#define OMAP_DMA4_CDP(n) (0x60 * (n) + 0xd0)
127#define OMAP_DMA4_CNDP(n) (0x60 * (n) + 0xd4)
128#define OMAP_DMA4_CCDN(n) (0x60 * (n) + 0xd8)
129
125/* Dummy defines to keep multi-omap compiles happy */ 130/* Dummy defines to keep multi-omap compiles happy */
126#define OMAP1_DMA_REVISION 0 131#define OMAP1_DMA_REVISION 0
127#define OMAP1_DMA_IRQSTATUS_L0 0 132#define OMAP1_DMA_IRQSTATUS_L0 0
@@ -311,6 +316,89 @@
311#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ 316#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
312#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ 317#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */
313 318
319/* DMA request lines for 44xx */
320#define OMAP44XX_DMA_DSS_DISPC_REQ 6 /* S_DMA_5 */
321#define OMAP44XX_DMA_SYS_REQ2 7 /* S_DMA_6 */
322#define OMAP44XX_DMA_ISS_REQ1 9 /* S_DMA_8 */
323#define OMAP44XX_DMA_ISS_REQ2 10 /* S_DMA_9 */
324#define OMAP44XX_DMA_ISS_REQ3 12 /* S_DMA_11 */
325#define OMAP44XX_DMA_ISS_REQ4 13 /* S_DMA_12 */
326#define OMAP44XX_DMA_DSS_RFBI_REQ 14 /* S_DMA_13 */
327#define OMAP44XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
328#define OMAP44XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
329#define OMAP44XX_DMA_MCBSP2_TX 17 /* S_DMA_16 */
330#define OMAP44XX_DMA_MCBSP2_RX 18 /* S_DMA_17 */
331#define OMAP44XX_DMA_MCBSP3_TX 19 /* S_DMA_18 */
332#define OMAP44XX_DMA_MCBSP3_RX 20 /* S_DMA_19 */
333#define OMAP44XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
334#define OMAP44XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
335#define OMAP44XX_DMA_I2C3_TX 25 /* S_DMA_24 */
336#define OMAP44XX_DMA_I2C3_RX 26 /* S_DMA_25 */
337#define OMAP44XX_DMA_I2C1_TX 27 /* S_DMA_26 */
338#define OMAP44XX_DMA_I2C1_RX 28 /* S_DMA_27 */
339#define OMAP44XX_DMA_I2C2_TX 29 /* S_DMA_28 */
340#define OMAP44XX_DMA_I2C2_RX 30 /* S_DMA_29 */
341#define OMAP44XX_DMA_MCBSP4_TX 31 /* S_DMA_30 */
342#define OMAP44XX_DMA_MCBSP4_RX 32 /* S_DMA_31 */
343#define OMAP44XX_DMA_MCBSP1_TX 33 /* S_DMA_32 */
344#define OMAP44XX_DMA_MCBSP1_RX 34 /* S_DMA_33 */
345#define OMAP44XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
346#define OMAP44XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
347#define OMAP44XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
348#define OMAP44XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
349#define OMAP44XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
350#define OMAP44XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
351#define OMAP44XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
352#define OMAP44XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
353#define OMAP44XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
354#define OMAP44XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
355#define OMAP44XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
356#define OMAP44XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
357#define OMAP44XX_DMA_MMC2_TX 47 /* S_DMA_46 */
358#define OMAP44XX_DMA_MMC2_RX 48 /* S_DMA_47 */
359#define OMAP44XX_DMA_UART1_TX 49 /* S_DMA_48 */
360#define OMAP44XX_DMA_UART1_RX 50 /* S_DMA_49 */
361#define OMAP44XX_DMA_UART2_TX 51 /* S_DMA_50 */
362#define OMAP44XX_DMA_UART2_RX 52 /* S_DMA_51 */
363#define OMAP44XX_DMA_UART3_TX 53 /* S_DMA_52 */
364#define OMAP44XX_DMA_UART3_RX 54 /* S_DMA_53 */
365#define OMAP44XX_DMA_UART4_TX 55 /* S_DMA_54 */
366#define OMAP44XX_DMA_UART4_RX 56 /* S_DMA_55 */
367#define OMAP44XX_DMA_MMC4_TX 57 /* S_DMA_56 */
368#define OMAP44XX_DMA_MMC4_RX 58 /* S_DMA_57 */
369#define OMAP44XX_DMA_MMC5_TX 59 /* S_DMA_58 */
370#define OMAP44XX_DMA_MMC5_RX 60 /* S_DMA_59 */
371#define OMAP44XX_DMA_MMC1_TX 61 /* S_DMA_60 */
372#define OMAP44XX_DMA_MMC1_RX 62 /* S_DMA_61 */
373#define OMAP44XX_DMA_SYS_REQ3 64 /* S_DMA_63 */
374#define OMAP44XX_DMA_MCPDM_UP 65 /* S_DMA_64 */
375#define OMAP44XX_DMA_MCPDM_DL 66 /* S_DMA_65 */
376#define OMAP44XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
377#define OMAP44XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
378#define OMAP44XX_DMA_DSS_DSI1_REQ0 72 /* S_DMA_71 */
379#define OMAP44XX_DMA_DSS_DSI1_REQ1 73 /* S_DMA_72 */
380#define OMAP44XX_DMA_DSS_DSI1_REQ2 74 /* S_DMA_73 */
381#define OMAP44XX_DMA_DSS_DSI1_REQ3 75 /* S_DMA_74 */
382#define OMAP44XX_DMA_DSS_HDMI_REQ 76 /* S_DMA_75 */
383#define OMAP44XX_DMA_MMC3_TX 77 /* S_DMA_76 */
384#define OMAP44XX_DMA_MMC3_RX 78 /* S_DMA_77 */
385#define OMAP44XX_DMA_USIM_TX 79 /* S_DMA_78 */
386#define OMAP44XX_DMA_USIM_RX 80 /* S_DMA_79 */
387#define OMAP44XX_DMA_DSS_DSI2_REQ0 81 /* S_DMA_80 */
388#define OMAP44XX_DMA_DSS_DSI2_REQ1 82 /* S_DMA_81 */
389#define OMAP44XX_DMA_DSS_DSI2_REQ2 83 /* S_DMA_82 */
390#define OMAP44XX_DMA_DSS_DSI2_REQ3 84 /* S_DMA_83 */
391#define OMAP44XX_DMA_ABE_REQ0 101 /* S_DMA_100 */
392#define OMAP44XX_DMA_ABE_REQ1 102 /* S_DMA_101 */
393#define OMAP44XX_DMA_ABE_REQ2 103 /* S_DMA_102 */
394#define OMAP44XX_DMA_ABE_REQ3 104 /* S_DMA_103 */
395#define OMAP44XX_DMA_ABE_REQ4 105 /* S_DMA_104 */
396#define OMAP44XX_DMA_ABE_REQ5 106 /* S_DMA_105 */
397#define OMAP44XX_DMA_ABE_REQ6 107 /* S_DMA_106 */
398#define OMAP44XX_DMA_ABE_REQ7 108 /* S_DMA_107 */
399#define OMAP44XX_DMA_I2C4_TX 124 /* S_DMA_123 */
400#define OMAP44XX_DMA_I2C4_RX 125 /* S_DMA_124 */
401
314/*----------------------------------------------------------------------------*/ 402/*----------------------------------------------------------------------------*/
315 403
316/* Hardware registers for LCD DMA */ 404/* Hardware registers for LCD DMA */
diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S
index 56426ed45ef4..a5592991634d 100644
--- a/arch/arm/plat-omap/include/mach/entry-macro.S
+++ b/arch/arm/plat-omap/include/mach/entry-macro.S
@@ -41,7 +41,7 @@
41 .endm 41 .endm
42 42
43 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 43 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
44 ldr \base, =IO_ADDRESS(OMAP_IH1_BASE) 44 ldr \base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
45 ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET] 45 ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
46 ldr \tmp, [\base, #IRQ_MIR_REG_OFFSET] 46 ldr \tmp, [\base, #IRQ_MIR_REG_OFFSET]
47 mov \irqstat, #0xffffffff 47 mov \irqstat, #0xffffffff
@@ -53,7 +53,7 @@
53 cmp \irqnr, #0 53 cmp \irqnr, #0
54 ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET] 54 ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
55 cmpeq \irqnr, #INT_IH2_IRQ 55 cmpeq \irqnr, #INT_IH2_IRQ
56 ldreq \base, =IO_ADDRESS(OMAP_IH2_BASE) 56 ldreq \base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE)
57 ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET] 57 ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
58 addeqs \irqnr, \irqnr, #32 58 addeqs \irqnr, \irqnr, #32
591510: 591510:
@@ -68,9 +68,9 @@
68 68
69/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */ 69/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */
70#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430) 70#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430)
71#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE) 71#define OMAP2_VA_IC_BASE OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE)
72#elif defined(CONFIG_ARCH_OMAP34XX) 72#elif defined(CONFIG_ARCH_OMAP34XX)
73#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE) 73#define OMAP2_VA_IC_BASE OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE)
74#endif 74#endif
75#if defined(CONFIG_ARCH_OMAP4) 75#if defined(CONFIG_ARCH_OMAP4)
76#include <mach/omap44xx.h> 76#include <mach/omap44xx.h>
diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/mach/gpio.h
index 2b22a8799bc6..633ff688b928 100644
--- a/arch/arm/plat-omap/include/mach/gpio.h
+++ b/arch/arm/plat-omap/include/mach/gpio.h
@@ -29,7 +29,7 @@
29#include <linux/io.h> 29#include <linux/io.h>
30#include <mach/irqs.h> 30#include <mach/irqs.h>
31 31
32#define OMAP_MPUIO_BASE 0xfffb5000 32#define OMAP1_MPUIO_BASE 0xfffb5000
33 33
34#if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)) 34#if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850))
35 35
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h
index 21fb0efdda86..8d32df32b0b1 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/mach/io.h
@@ -54,17 +54,33 @@
54 * ---------------------------------------------------------------------------- 54 * ----------------------------------------------------------------------------
55 */ 55 */
56 56
57#if defined(CONFIG_ARCH_OMAP1) 57#ifdef __ASSEMBLER__
58#define IOMEM(x) (x)
59#else
60#define IOMEM(x) ((void __force __iomem *)(x))
61#endif
62
63#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
64#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
65
66#define OMAP2_IO_OFFSET 0x90000000
67#define OMAP2_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_IO_OFFSET) /* L3 and L4 */
68
69/*
70 * ----------------------------------------------------------------------------
71 * Omap1 specific IO mapping
72 * ----------------------------------------------------------------------------
73 */
58 74
59#define IO_PHYS 0xFFFB0000 75#define OMAP1_IO_PHYS 0xFFFB0000
60#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ 76#define OMAP1_IO_SIZE 0x40000
61#define IO_SIZE 0x40000 77#define OMAP1_IO_VIRT (OMAP1_IO_PHYS - OMAP1_IO_OFFSET)
62#define IO_VIRT (IO_PHYS - IO_OFFSET)
63#define __IO_ADDRESS(pa) ((pa) - IO_OFFSET)
64#define __OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET)
65#define io_v2p(va) ((va) + IO_OFFSET)
66 78
67#elif defined(CONFIG_ARCH_OMAP2) 79/*
80 * ----------------------------------------------------------------------------
81 * Omap2 specific IO mapping
82 * ----------------------------------------------------------------------------
83 */
68 84
69/* We map both L3 and L4 on OMAP2 */ 85/* We map both L3 and L4 on OMAP2 */
70#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 */ 86#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 */
@@ -87,11 +103,6 @@
87#define OMAP243X_SMS_VIRT 0xFC000000 103#define OMAP243X_SMS_VIRT 0xFC000000
88#define OMAP243X_SMS_SIZE SZ_1M 104#define OMAP243X_SMS_SIZE SZ_1M
89 105
90#define IO_OFFSET 0x90000000
91#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
92#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
93#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
94
95/* DSP */ 106/* DSP */
96#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */ 107#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
97#define DSP_MEM_24XX_VIRT 0xe0000000 108#define DSP_MEM_24XX_VIRT 0xe0000000
@@ -103,7 +114,11 @@
103#define DSP_MMU_24XX_VIRT 0xe2000000 114#define DSP_MMU_24XX_VIRT 0xe2000000
104#define DSP_MMU_24XX_SIZE SZ_4K 115#define DSP_MMU_24XX_SIZE SZ_4K
105 116
106#elif defined(CONFIG_ARCH_OMAP3) 117/*
118 * ----------------------------------------------------------------------------
119 * Omap3 specific IO mapping
120 * ----------------------------------------------------------------------------
121 */
107 122
108/* We map both L3 and L4 on OMAP3 */ 123/* We map both L3 and L4 on OMAP3 */
109#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 */ 124#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 */
@@ -143,12 +158,6 @@
143#define OMAP343X_SDRC_VIRT 0xFD000000 158#define OMAP343X_SDRC_VIRT 0xFD000000
144#define OMAP343X_SDRC_SIZE SZ_1M 159#define OMAP343X_SDRC_SIZE SZ_1M
145 160
146
147#define IO_OFFSET 0x90000000
148#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
149#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
150#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */
151
152/* DSP */ 161/* DSP */
153#define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */ 162#define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */
154#define DSP_MEM_34XX_VIRT 0xe0000000 163#define DSP_MEM_34XX_VIRT 0xe0000000
@@ -160,8 +169,12 @@
160#define DSP_MMU_34XX_VIRT 0xe2000000 169#define DSP_MMU_34XX_VIRT 0xe2000000
161#define DSP_MMU_34XX_SIZE SZ_4K 170#define DSP_MMU_34XX_SIZE SZ_4K
162 171
172/*
173 * ----------------------------------------------------------------------------
174 * Omap4 specific IO mapping
175 * ----------------------------------------------------------------------------
176 */
163 177
164#elif defined(CONFIG_ARCH_OMAP4)
165/* We map both L3 and L4 on OMAP4 */ 178/* We map both L3 and L4 on OMAP4 */
166#define L3_44XX_PHYS L3_44XX_BASE 179#define L3_44XX_PHYS L3_44XX_BASE
167#define L3_44XX_VIRT 0xd4000000 180#define L3_44XX_VIRT 0xd4000000
@@ -189,38 +202,24 @@
189#define OMAP44XX_GPMC_SIZE SZ_1M 202#define OMAP44XX_GPMC_SIZE SZ_1M
190 203
191 204
192#define IO_OFFSET 0x90000000 205/*
193#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ 206 * ----------------------------------------------------------------------------
194#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ 207 * Omap specific register access
195#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */ 208 * ----------------------------------------------------------------------------
196 209 */
197#endif
198
199#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))
200#define OMAP1_IO_ADDRESS(pa) IOMEM(__OMAP1_IO_ADDRESS(pa))
201#define OMAP2_IO_ADDRESS(pa) IOMEM(__OMAP2_IO_ADDRESS(pa))
202 210
203#ifdef __ASSEMBLER__ 211#ifndef __ASSEMBLER__
204#define IOMEM(x) (x)
205#else
206#define IOMEM(x) ((void __force __iomem *)(x))
207 212
208/* 213/*
209 * Functions to access the OMAP IO region 214 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
210 *
211 * NOTE: - Use omap_read/write[bwl] for physical register addresses
212 * - Use __raw_read/write[bwl]() for virtual register addresses
213 * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses
214 * - DO NOT use hardcoded virtual addresses to allow changing the
215 * IO address space again if needed
216 */ 215 */
217#define omap_readb(a) __raw_readb(IO_ADDRESS(a))
218#define omap_readw(a) __raw_readw(IO_ADDRESS(a))
219#define omap_readl(a) __raw_readl(IO_ADDRESS(a))
220 216
221#define omap_writeb(v,a) __raw_writeb(v, IO_ADDRESS(a)) 217extern u8 omap_readb(u32 pa);
222#define omap_writew(v,a) __raw_writew(v, IO_ADDRESS(a)) 218extern u16 omap_readw(u32 pa);
223#define omap_writel(v,a) __raw_writel(v, IO_ADDRESS(a)) 219extern u32 omap_readl(u32 pa);
220extern void omap_writeb(u8 v, u32 pa);
221extern void omap_writew(u16 v, u32 pa);
222extern void omap_writel(u32 v, u32 pa);
224 223
225struct omap_sdrc_params; 224struct omap_sdrc_params;
226 225
diff --git a/arch/arm/plat-omap/include/mach/iommu.h b/arch/arm/plat-omap/include/mach/iommu.h
index 769b00b4c34a..46d41ac83dbf 100644
--- a/arch/arm/plat-omap/include/mach/iommu.h
+++ b/arch/arm/plat-omap/include/mach/iommu.h
@@ -95,7 +95,7 @@ struct iommu_functions {
95 95
96 void (*save_ctx)(struct iommu *obj); 96 void (*save_ctx)(struct iommu *obj);
97 void (*restore_ctx)(struct iommu *obj); 97 void (*restore_ctx)(struct iommu *obj);
98 ssize_t (*dump_ctx)(struct iommu *obj, char *buf); 98 ssize_t (*dump_ctx)(struct iommu *obj, char *buf, ssize_t len);
99}; 99};
100 100
101struct iommu_platform_data { 101struct iommu_platform_data {
@@ -162,7 +162,7 @@ extern void uninstall_iommu_arch(const struct iommu_functions *ops);
162extern int foreach_iommu_device(void *data, 162extern int foreach_iommu_device(void *data,
163 int (*fn)(struct device *, void *)); 163 int (*fn)(struct device *, void *));
164 164
165extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf); 165extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len);
166extern size_t dump_tlb_entries(struct iommu *obj, char *buf); 166extern size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t len);
167 167
168#endif /* __MACH_IOMMU_H */ 168#endif /* __MACH_IOMMU_H */
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h
index bb154ea76769..e0d6eca222cc 100644
--- a/arch/arm/plat-omap/include/mach/mcbsp.h
+++ b/arch/arm/plat-omap/include/mach/mcbsp.h
@@ -53,6 +53,11 @@
53#define OMAP34XX_MCBSP4_BASE 0x49026000 53#define OMAP34XX_MCBSP4_BASE 0x49026000
54#define OMAP34XX_MCBSP5_BASE 0x48096000 54#define OMAP34XX_MCBSP5_BASE 0x48096000
55 55
56#define OMAP44XX_MCBSP1_BASE 0x49022000
57#define OMAP44XX_MCBSP2_BASE 0x49024000
58#define OMAP44XX_MCBSP3_BASE 0x49026000
59#define OMAP44XX_MCBSP4_BASE 0x48074000
60
56#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) 61#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
57 62
58#define OMAP_MCBSP_REG_DRR2 0x00 63#define OMAP_MCBSP_REG_DRR2 0x00
@@ -98,7 +103,8 @@
98#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX 103#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
99#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX 104#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
100 105
101#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 106#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
107 defined(CONFIG_ARCH_OMAP4)
102 108
103#define OMAP_MCBSP_REG_DRR2 0x00 109#define OMAP_MCBSP_REG_DRR2 0x00
104#define OMAP_MCBSP_REG_DRR1 0x04 110#define OMAP_MCBSP_REG_DRR1 0x04
@@ -134,6 +140,11 @@
134#define OMAP_MCBSP_REG_XCERG 0x74 140#define OMAP_MCBSP_REG_XCERG 0x74
135#define OMAP_MCBSP_REG_XCERH 0x78 141#define OMAP_MCBSP_REG_XCERH 0x78
136#define OMAP_MCBSP_REG_SYSCON 0x8C 142#define OMAP_MCBSP_REG_SYSCON 0x8C
143#define OMAP_MCBSP_REG_THRSH2 0x90
144#define OMAP_MCBSP_REG_THRSH1 0x94
145#define OMAP_MCBSP_REG_IRQST 0xA0
146#define OMAP_MCBSP_REG_IRQEN 0xA4
147#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
137#define OMAP_MCBSP_REG_XCCR 0xAC 148#define OMAP_MCBSP_REG_XCCR 0xAC
138#define OMAP_MCBSP_REG_RCCR 0xB0 149#define OMAP_MCBSP_REG_RCCR 0xB0
139 150
@@ -249,8 +260,27 @@
249#define RDISABLE 0x0001 260#define RDISABLE 0x0001
250 261
251/********************** McBSP SYSCONFIG bit definitions ********************/ 262/********************** McBSP SYSCONFIG bit definitions ********************/
263#define CLOCKACTIVITY(value) ((value)<<8)
264#define SIDLEMODE(value) ((value)<<3)
265#define ENAWAKEUP 0x0004
252#define SOFTRST 0x0002 266#define SOFTRST 0x0002
253 267
268/********************** McBSP DMA operating modes **************************/
269#define MCBSP_DMA_MODE_ELEMENT 0
270#define MCBSP_DMA_MODE_THRESHOLD 1
271#define MCBSP_DMA_MODE_FRAME 2
272
273/********************** McBSP WAKEUPEN bit definitions *********************/
274#define XEMPTYEOFEN 0x4000
275#define XRDYEN 0x0400
276#define XEOFEN 0x0200
277#define XFSXEN 0x0100
278#define XSYNCERREN 0x0080
279#define RRDYEN 0x0008
280#define REOFEN 0x0004
281#define RFSREN 0x0002
282#define RSYNCERREN 0x0001
283
254/* we don't do multichannel for now */ 284/* we don't do multichannel for now */
255struct omap_mcbsp_reg_cfg { 285struct omap_mcbsp_reg_cfg {
256 u16 spcr2; 286 u16 spcr2;
@@ -344,6 +374,9 @@ struct omap_mcbsp_platform_data {
344 u8 dma_rx_sync, dma_tx_sync; 374 u8 dma_rx_sync, dma_tx_sync;
345 u16 rx_irq, tx_irq; 375 u16 rx_irq, tx_irq;
346 struct omap_mcbsp_ops *ops; 376 struct omap_mcbsp_ops *ops;
377#ifdef CONFIG_ARCH_OMAP34XX
378 u16 buffer_size;
379#endif
347}; 380};
348 381
349struct omap_mcbsp { 382struct omap_mcbsp {
@@ -377,6 +410,11 @@ struct omap_mcbsp {
377 struct omap_mcbsp_platform_data *pdata; 410 struct omap_mcbsp_platform_data *pdata;
378 struct clk *iclk; 411 struct clk *iclk;
379 struct clk *fclk; 412 struct clk *fclk;
413#ifdef CONFIG_ARCH_OMAP34XX
414 int dma_op_mode;
415 u16 max_tx_thres;
416 u16 max_rx_thres;
417#endif
380}; 418};
381extern struct omap_mcbsp **mcbsp_ptr; 419extern struct omap_mcbsp **mcbsp_ptr;
382extern int omap_mcbsp_count; 420extern int omap_mcbsp_count;
@@ -385,10 +423,25 @@ int omap_mcbsp_init(void);
385void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, 423void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
386 int size); 424 int size);
387void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); 425void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
426#ifdef CONFIG_ARCH_OMAP34XX
427void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
428void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
429u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
430u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
431int omap_mcbsp_get_dma_op_mode(unsigned int id);
432#else
433static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
434{ }
435static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
436{ }
437static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
438static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
439static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
440#endif
388int omap_mcbsp_request(unsigned int id); 441int omap_mcbsp_request(unsigned int id);
389void omap_mcbsp_free(unsigned int id); 442void omap_mcbsp_free(unsigned int id);
390void omap_mcbsp_start(unsigned int id); 443void omap_mcbsp_start(unsigned int id, int tx, int rx);
391void omap_mcbsp_stop(unsigned int id); 444void omap_mcbsp_stop(unsigned int id, int tx, int rx);
392void omap_mcbsp_xmit_word(unsigned int id, u32 word); 445void omap_mcbsp_xmit_word(unsigned int id, u32 word);
393u32 omap_mcbsp_recv_word(unsigned int id); 446u32 omap_mcbsp_recv_word(unsigned int id);
394 447
diff --git a/arch/arm/plat-omap/include/mach/mtd-xip.h b/arch/arm/plat-omap/include/mach/mtd-xip.h
index 39b591ff54bb..f82a8dcaad94 100644
--- a/arch/arm/plat-omap/include/mach/mtd-xip.h
+++ b/arch/arm/plat-omap/include/mach/mtd-xip.h
@@ -25,7 +25,7 @@ typedef struct {
25} xip_omap_mpu_timer_regs_t; 25} xip_omap_mpu_timer_regs_t;
26 26
27#define xip_omap_mpu_timer_base(n) \ 27#define xip_omap_mpu_timer_base(n) \
28((volatile xip_omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ 28((volatile xip_omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
29 (n)*OMAP_MPU_TIMER_OFFSET)) 29 (n)*OMAP_MPU_TIMER_OFFSET))
30 30
31static inline unsigned long xip_omap_mpu_timer_read(int nr) 31static inline unsigned long xip_omap_mpu_timer_read(int nr)
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h
index 80281c458baf..98dfab651dfc 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -857,6 +857,37 @@ enum omap34xx_index {
857 /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */ 857 /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
858 H16_34XX_SDRC_CKE0, 858 H16_34XX_SDRC_CKE0,
859 H17_34XX_SDRC_CKE1, 859 H17_34XX_SDRC_CKE1,
860
861 /* MMC1 */
862 N28_3430_MMC1_CLK,
863 M27_3430_MMC1_CMD,
864 N27_3430_MMC1_DAT0,
865 N26_3430_MMC1_DAT1,
866 N25_3430_MMC1_DAT2,
867 P28_3430_MMC1_DAT3,
868 P27_3430_MMC1_DAT4,
869 P26_3430_MMC1_DAT5,
870 R27_3430_MMC1_DAT6,
871 R25_3430_MMC1_DAT7,
872
873 /* MMC2 */
874 AE2_3430_MMC2_CLK,
875 AG5_3430_MMC2_CMD,
876 AH5_3430_MMC2_DAT0,
877 AH4_3430_MMC2_DAT1,
878 AG4_3430_MMC2_DAT2,
879 AF4_3430_MMC2_DAT3,
880
881 /* MMC3 */
882 AF10_3430_MMC3_CLK,
883 AC3_3430_MMC3_CMD,
884 AE11_3430_MMC3_DAT0,
885 AH9_3430_MMC3_DAT1,
886 AF13_3430_MMC3_DAT2,
887 AF13_3430_MMC3_DAT3,
888
889 /* SYS_NIRQ T2 INT1 */
890 AF26_34XX_SYS_NIRQ,
860}; 891};
861 892
862struct omap_mux_cfg { 893struct omap_mux_cfg {
diff --git a/arch/arm/plat-omap/include/mach/omap-pm.h b/arch/arm/plat-omap/include/mach/omap-pm.h
new file mode 100644
index 000000000000..3ee41d711492
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/omap-pm.h
@@ -0,0 +1,301 @@
1/*
2 * omap-pm.h - OMAP power management interface
3 *
4 * Copyright (C) 2008-2009 Texas Instruments, Inc.
5 * Copyright (C) 2008-2009 Nokia Corporation
6 * Paul Walmsley
7 *
8 * Interface developed by (in alphabetical order): Karthik Dasu, Jouni
9 * Högander, Tony Lindgren, Rajendra Nayak, Sakari Poussa,
10 * Veeramanikandan Raju, Anand Sawant, Igor Stoppa, Paul Walmsley,
11 * Richard Woodruff
12 */
13
14#ifndef ASM_ARM_ARCH_OMAP_OMAP_PM_H
15#define ASM_ARM_ARCH_OMAP_OMAP_PM_H
16
17#include <linux/device.h>
18#include <linux/cpufreq.h>
19
20#include "powerdomain.h"
21
22/**
23 * struct omap_opp - clock frequency-to-OPP ID table for DSP, MPU
24 * @rate: target clock rate
25 * @opp_id: OPP ID
26 * @min_vdd: minimum VDD1 voltage (in millivolts) for this OPP
27 *
28 * Operating performance point data. Can vary by OMAP chip and board.
29 */
30struct omap_opp {
31 unsigned long rate;
32 u8 opp_id;
33 u16 min_vdd;
34};
35
36extern struct omap_opp *mpu_opps;
37extern struct omap_opp *dsp_opps;
38extern struct omap_opp *l3_opps;
39
40/*
41 * agent_id values for use with omap_pm_set_min_bus_tput():
42 *
43 * OCP_INITIATOR_AGENT is only valid for devices that can act as
44 * initiators -- it represents the device's L3 interconnect
45 * connection. OCP_TARGET_AGENT represents the device's L4
46 * interconnect connection.
47 */
48#define OCP_TARGET_AGENT 1
49#define OCP_INITIATOR_AGENT 2
50
51/**
52 * omap_pm_if_early_init - OMAP PM init code called before clock fw init
53 * @mpu_opp_table: array ptr to struct omap_opp for MPU
54 * @dsp_opp_table: array ptr to struct omap_opp for DSP
55 * @l3_opp_table : array ptr to struct omap_opp for CORE
56 *
57 * Initialize anything that must be configured before the clock
58 * framework starts. The "_if_" is to avoid name collisions with the
59 * PM idle-loop code.
60 */
61int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
62 struct omap_opp *dsp_opp_table,
63 struct omap_opp *l3_opp_table);
64
65/**
66 * omap_pm_if_init - OMAP PM init code called after clock fw init
67 *
68 * The main initialization code. OPP tables are passed in here. The
69 * "_if_" is to avoid name collisions with the PM idle-loop code.
70 */
71int __init omap_pm_if_init(void);
72
73/**
74 * omap_pm_if_exit - OMAP PM exit code
75 *
76 * Exit code; currently unused. The "_if_" is to avoid name
77 * collisions with the PM idle-loop code.
78 */
79void omap_pm_if_exit(void);
80
81/*
82 * Device-driver-originated constraints (via board-*.c files, platform_data)
83 */
84
85
86/**
87 * omap_pm_set_max_mpu_wakeup_lat - set the maximum MPU wakeup latency
88 * @dev: struct device * requesting the constraint
89 * @t: maximum MPU wakeup latency in microseconds
90 *
91 * Request that the maximum interrupt latency for the MPU to be no
92 * greater than 't' microseconds. "Interrupt latency" in this case is
93 * defined as the elapsed time from the occurrence of a hardware or
94 * timer interrupt to the time when the device driver's interrupt
95 * service routine has been entered by the MPU.
96 *
97 * It is intended that underlying PM code will use this information to
98 * determine what power state to put the MPU powerdomain into, and
99 * possibly the CORE powerdomain as well, since interrupt handling
100 * code currently runs from SDRAM. Advanced PM or board*.c code may
101 * also configure interrupt controller priorities, OCP bus priorities,
102 * CPU speed(s), etc.
103 *
104 * This function will not affect device wakeup latency, e.g., time
105 * elapsed from when a device driver enables a hardware device with
106 * clk_enable(), to when the device is ready for register access or
107 * other use. To control this device wakeup latency, use
108 * set_max_dev_wakeup_lat()
109 *
110 * Multiple calls to set_max_mpu_wakeup_lat() will replace the
111 * previous t value. To remove the latency target for the MPU, call
112 * with t = -1.
113 *
114 * No return value.
115 */
116void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
117
118
119/**
120 * omap_pm_set_min_bus_tput - set minimum bus throughput needed by device
121 * @dev: struct device * requesting the constraint
122 * @tbus_id: interconnect to operate on (OCP_{INITIATOR,TARGET}_AGENT)
123 * @r: minimum throughput (in KiB/s)
124 *
125 * Request that the minimum data throughput on the OCP interconnect
126 * attached to device 'dev' interconnect agent 'tbus_id' be no less
127 * than 'r' KiB/s.
128 *
129 * It is expected that the OMAP PM or bus code will use this
130 * information to set the interconnect clock to run at the lowest
131 * possible speed that satisfies all current system users. The PM or
132 * bus code will adjust the estimate based on its model of the bus, so
133 * device driver authors should attempt to specify an accurate
134 * quantity for their device use case, and let the PM or bus code
135 * overestimate the numbers as necessary to handle request/response
136 * latency, other competing users on the system, etc. On OMAP2/3, if
137 * a driver requests a minimum L4 interconnect speed constraint, the
138 * code will also need to add an minimum L3 interconnect speed
139 * constraint,
140 *
141 * Multiple calls to set_min_bus_tput() will replace the previous rate
142 * value for this device. To remove the interconnect throughput
143 * restriction for this device, call with r = 0.
144 *
145 * No return value.
146 */
147void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r);
148
149
150/**
151 * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency
152 * @dev: struct device *
153 * @t: maximum device wakeup latency in microseconds
154 *
155 * Request that the maximum amount of time necessary for a device to
156 * become accessible after its clocks are enabled should be no greater
157 * than 't' microseconds. Specifically, this represents the time from
158 * when a device driver enables device clocks with clk_enable(), to
159 * when the register reads and writes on the device will succeed.
160 * This function should be called before clk_disable() is called,
161 * since the power state transition decision may be made during
162 * clk_disable().
163 *
164 * It is intended that underlying PM code will use this information to
165 * determine what power state to put the powerdomain enclosing this
166 * device into.
167 *
168 * Multiple calls to set_max_dev_wakeup_lat() will replace the
169 * previous wakeup latency values for this device. To remove the wakeup
170 * latency restriction for this device, call with t = -1.
171 *
172 * No return value.
173 */
174void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t);
175
176
177/**
178 * omap_pm_set_max_sdma_lat - set the maximum system DMA transfer start latency
179 * @dev: struct device *
180 * @t: maximum DMA transfer start latency in microseconds
181 *
182 * Request that the maximum system DMA transfer start latency for this
183 * device 'dev' should be no greater than 't' microseconds. "DMA
184 * transfer start latency" here is defined as the elapsed time from
185 * when a device (e.g., McBSP) requests that a system DMA transfer
186 * start or continue, to the time at which data starts to flow into
187 * that device from the system DMA controller.
188 *
189 * It is intended that underlying PM code will use this information to
190 * determine what power state to put the CORE powerdomain into.
191 *
192 * Since system DMA transfers may not involve the MPU, this function
193 * will not affect MPU wakeup latency. Use set_max_cpu_lat() to do
194 * so. Similarly, this function will not affect device wakeup latency
195 * -- use set_max_dev_wakeup_lat() to affect that.
196 *
197 * Multiple calls to set_max_sdma_lat() will replace the previous t
198 * value for this device. To remove the maximum DMA latency for this
199 * device, call with t = -1.
200 *
201 * No return value.
202 */
203void omap_pm_set_max_sdma_lat(struct device *dev, long t);
204
205
206/*
207 * DSP Bridge-specific constraints
208 */
209
210/**
211 * omap_pm_dsp_get_opp_table - get OPP->DSP clock frequency table
212 *
213 * Intended for use by DSPBridge. Returns an array of OPP->DSP clock
214 * frequency entries. The final item in the array should have .rate =
215 * .opp_id = 0.
216 */
217const struct omap_opp *omap_pm_dsp_get_opp_table(void);
218
219/**
220 * omap_pm_dsp_set_min_opp - receive desired OPP target ID from DSP Bridge
221 * @opp_id: target DSP OPP ID
222 *
223 * Set a minimum OPP ID for the DSP. This is intended to be called
224 * only from the DSP Bridge MPU-side driver. Unfortunately, the only
225 * information that code receives from the DSP/BIOS load estimator is the
226 * target OPP ID; hence, this interface. No return value.
227 */
228void omap_pm_dsp_set_min_opp(u8 opp_id);
229
230/**
231 * omap_pm_dsp_get_opp - report the current DSP OPP ID
232 *
233 * Report the current OPP for the DSP. Since on OMAP3, the DSP and
234 * MPU share a single voltage domain, the OPP ID returned back may
235 * represent a higher DSP speed than the OPP requested via
236 * omap_pm_dsp_set_min_opp().
237 *
238 * Returns the current VDD1 OPP ID, or 0 upon error.
239 */
240u8 omap_pm_dsp_get_opp(void);
241
242
243/*
244 * CPUFreq-originated constraint
245 *
246 * In the future, this should be handled by custom OPP clocktype
247 * functions.
248 */
249
250/**
251 * omap_pm_cpu_get_freq_table - return a cpufreq_frequency_table array ptr
252 *
253 * Provide a frequency table usable by CPUFreq for the current chip/board.
254 * Returns a pointer to a struct cpufreq_frequency_table array or NULL
255 * upon error.
256 */
257struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void);
258
259/**
260 * omap_pm_cpu_set_freq - set the current minimum MPU frequency
261 * @f: MPU frequency in Hz
262 *
263 * Set the current minimum CPU frequency. The actual CPU frequency
264 * used could end up higher if the DSP requested a higher OPP.
265 * Intended to be called by plat-omap/cpu_omap.c:omap_target(). No
266 * return value.
267 */
268void omap_pm_cpu_set_freq(unsigned long f);
269
270/**
271 * omap_pm_cpu_get_freq - report the current CPU frequency
272 *
273 * Returns the current MPU frequency, or 0 upon error.
274 */
275unsigned long omap_pm_cpu_get_freq(void);
276
277
278/*
279 * Device context loss tracking
280 */
281
282/**
283 * omap_pm_get_dev_context_loss_count - return count of times dev has lost ctx
284 * @dev: struct device *
285 *
286 * This function returns the number of times that the device @dev has
287 * lost its internal context. This generally occurs on a powerdomain
288 * transition to OFF. Drivers use this as an optimization to avoid restoring
289 * context if the device hasn't lost it. To use, drivers should initially
290 * call this in their context save functions and store the result. Early in
291 * the driver's context restore function, the driver should call this function
292 * again, and compare the result to the stored counter. If they differ, the
293 * driver must restore device context. If the number of context losses
294 * exceeds the maximum positive integer, the function will wrap to 0 and
295 * continue counting. Returns the number of context losses for this device,
296 * or -EINVAL upon error.
297 */
298int omap_pm_get_dev_context_loss_count(struct device *dev);
299
300
301#endif
diff --git a/arch/arm/plat-omap/include/mach/omap44xx.h b/arch/arm/plat-omap/include/mach/omap44xx.h
index 15dec7f1c7c0..b3ba5ac7b4a4 100644
--- a/arch/arm/plat-omap/include/mach/omap44xx.h
+++ b/arch/arm/plat-omap/include/mach/omap44xx.h
@@ -33,14 +33,14 @@
33#define IRQ_SIR_IRQ 0x0040 33#define IRQ_SIR_IRQ 0x0040
34#define OMAP44XX_GIC_DIST_BASE 0x48241000 34#define OMAP44XX_GIC_DIST_BASE 0x48241000
35#define OMAP44XX_GIC_CPU_BASE 0x48240100 35#define OMAP44XX_GIC_CPU_BASE 0x48240100
36#define OMAP44XX_VA_GIC_CPU_BASE IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) 36#define OMAP44XX_VA_GIC_CPU_BASE OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
37#define OMAP44XX_SCU_BASE 0x48240000 37#define OMAP44XX_SCU_BASE 0x48240000
38#define OMAP44XX_VA_SCU_BASE IO_ADDRESS(OMAP44XX_SCU_BASE) 38#define OMAP44XX_VA_SCU_BASE OMAP2_IO_ADDRESS(OMAP44XX_SCU_BASE)
39#define OMAP44XX_LOCAL_TWD_BASE 0x48240600 39#define OMAP44XX_LOCAL_TWD_BASE 0x48240600
40#define OMAP44XX_VA_LOCAL_TWD_BASE IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE) 40#define OMAP44XX_VA_LOCAL_TWD_BASE OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE)
41#define OMAP44XX_LOCAL_TWD_SIZE 0x00000100 41#define OMAP44XX_LOCAL_TWD_SIZE 0x00000100
42#define OMAP44XX_WKUPGEN_BASE 0x48281000 42#define OMAP44XX_WKUPGEN_BASE 0x48281000
43#define OMAP44XX_VA_WKUPGEN_BASE IO_ADDRESS(OMAP44XX_WKUPGEN_BASE) 43#define OMAP44XX_VA_WKUPGEN_BASE OMAP2_IO_ADDRESS(OMAP44XX_WKUPGEN_BASE)
44 44
45#endif /* __ASM_ARCH_OMAP44XX_H */ 45#endif /* __ASM_ARCH_OMAP44XX_H */
46 46
diff --git a/arch/arm/plat-omap/include/mach/omap_device.h b/arch/arm/plat-omap/include/mach/omap_device.h
new file mode 100644
index 000000000000..bd0e136db337
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/omap_device.h
@@ -0,0 +1,141 @@
1/*
2 * omap_device headers
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Paul Walmsley
6 *
7 * Developed in collaboration with (alphabetical order): Benoit
8 * Cousson, Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram
9 * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard
10 * Woodruff
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * Eventually this type of functionality should either be
17 * a) implemented via arch-specific pointers in platform_device
18 * or
19 * b) implemented as a proper omap_bus/omap_device in Linux, no more
20 * platform_device
21 *
22 * omap_device differs from omap_hwmod in that it includes external
23 * (e.g., board- and system-level) integration details. omap_hwmod
24 * stores hardware data that is invariant for a given OMAP chip.
25 *
26 * To do:
27 * - GPIO integration
28 * - regulator integration
29 *
30 */
31#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
32#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
33
34#include <linux/kernel.h>
35#include <linux/platform_device.h>
36
37#include <mach/omap_hwmod.h>
38
39/* omap_device._state values */
40#define OMAP_DEVICE_STATE_UNKNOWN 0
41#define OMAP_DEVICE_STATE_ENABLED 1
42#define OMAP_DEVICE_STATE_IDLE 2
43#define OMAP_DEVICE_STATE_SHUTDOWN 3
44
45/**
46 * struct omap_device - omap_device wrapper for platform_devices
47 * @pdev: platform_device
48 * @hwmods: (one .. many per omap_device)
49 * @hwmods_cnt: ARRAY_SIZE() of @hwmods
50 * @pm_lats: ptr to an omap_device_pm_latency table
51 * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats
52 * @pm_lat_level: array index of the last odpl entry executed - -1 if never
53 * @dev_wakeup_lat: dev wakeup latency in microseconds
54 * @_dev_wakeup_lat_limit: dev wakeup latency limit in usec - set by OMAP PM
55 * @_state: one of OMAP_DEVICE_STATE_* (see above)
56 * @flags: device flags
57 *
58 * Integrates omap_hwmod data into Linux platform_device.
59 *
60 * Field names beginning with underscores are for the internal use of
61 * the omap_device code.
62 *
63 */
64struct omap_device {
65 struct platform_device pdev;
66 struct omap_hwmod **hwmods;
67 struct omap_device_pm_latency *pm_lats;
68 u32 dev_wakeup_lat;
69 u32 _dev_wakeup_lat_limit;
70 u8 pm_lats_cnt;
71 s8 pm_lat_level;
72 u8 hwmods_cnt;
73 u8 _state;
74};
75
76/* Device driver interface (call via platform_data fn ptrs) */
77
78int omap_device_enable(struct platform_device *pdev);
79int omap_device_idle(struct platform_device *pdev);
80int omap_device_shutdown(struct platform_device *pdev);
81
82/* Core code interface */
83
84int omap_device_count_resources(struct omap_device *od);
85int omap_device_fill_resources(struct omap_device *od, struct resource *res);
86
87struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
88 struct omap_hwmod *oh, void *pdata,
89 int pdata_len,
90 struct omap_device_pm_latency *pm_lats,
91 int pm_lats_cnt);
92
93struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
94 struct omap_hwmod **oh, int oh_cnt,
95 void *pdata, int pdata_len,
96 struct omap_device_pm_latency *pm_lats,
97 int pm_lats_cnt);
98
99int omap_device_register(struct omap_device *od);
100
101/* OMAP PM interface */
102int omap_device_align_pm_lat(struct platform_device *pdev,
103 u32 new_wakeup_lat_limit);
104struct powerdomain *omap_device_get_pwrdm(struct omap_device *od);
105
106/* Other */
107
108int omap_device_idle_hwmods(struct omap_device *od);
109int omap_device_enable_hwmods(struct omap_device *od);
110
111int omap_device_disable_clocks(struct omap_device *od);
112int omap_device_enable_clocks(struct omap_device *od);
113
114
115/*
116 * Entries should be kept in latency order ascending
117 *
118 * deact_lat is the maximum number of microseconds required to complete
119 * deactivate_func() at the device's slowest OPP.
120 *
121 * act_lat is the maximum number of microseconds required to complete
122 * activate_func() at the device's slowest OPP.
123 *
124 * This will result in some suboptimal power management decisions at fast
125 * OPPs, but avoids having to recompute all device power management decisions
126 * if the system shifts from a fast OPP to a slow OPP (in order to meet
127 * latency requirements).
128 *
129 * XXX should deactivate_func/activate_func() take platform_device pointers
130 * rather than omap_device pointers?
131 */
132struct omap_device_pm_latency {
133 u32 deactivate_lat;
134 int (*deactivate_func)(struct omap_device *od);
135 u32 activate_lat;
136 int (*activate_func)(struct omap_device *od);
137};
138
139
140#endif
141
diff --git a/arch/arm/plat-omap/include/mach/omap_hwmod.h b/arch/arm/plat-omap/include/mach/omap_hwmod.h
new file mode 100644
index 000000000000..1f79c20e2929
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/omap_hwmod.h
@@ -0,0 +1,447 @@
1/*
2 * omap_hwmod macros, structures
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Paul Walmsley
6 *
7 * Created in collaboration with (alphabetical order): Benoit Cousson,
8 * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari
9 * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * These headers and macros are used to define OMAP on-chip module
16 * data and their integration with other OMAP modules and Linux.
17 *
18 * References:
19 * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
20 * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
21 * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
22 * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
23 * - Open Core Protocol Specification 2.2
24 *
25 * To do:
26 * - add interconnect error log structures
27 * - add pinmuxing
28 * - init_conn_id_bit (CONNID_BIT_VECTOR)
29 * - implement default hwmod SMS/SDRC flags?
30 *
31 */
32#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
33#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
34
35#include <linux/kernel.h>
36#include <linux/ioport.h>
37
38#include <mach/cpu.h>
39
40struct omap_device;
41
42/* OCP SYSCONFIG bit shifts/masks */
43#define SYSC_MIDLEMODE_SHIFT 12
44#define SYSC_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT)
45#define SYSC_CLOCKACTIVITY_SHIFT 8
46#define SYSC_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT)
47#define SYSC_SIDLEMODE_SHIFT 3
48#define SYSC_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT)
49#define SYSC_ENAWAKEUP_SHIFT 2
50#define SYSC_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT)
51#define SYSC_SOFTRESET_SHIFT 1
52#define SYSC_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT)
53
54/* OCP SYSSTATUS bit shifts/masks */
55#define SYSS_RESETDONE_SHIFT 0
56#define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT)
57
58/* Master standby/slave idle mode flags */
59#define HWMOD_IDLEMODE_FORCE (1 << 0)
60#define HWMOD_IDLEMODE_NO (1 << 1)
61#define HWMOD_IDLEMODE_SMART (1 << 2)
62
63
64/**
65 * struct omap_hwmod_dma_info - MPU address space handled by the hwmod
66 * @name: name of the DMA channel (module local name)
67 * @dma_ch: DMA channel ID
68 *
69 * @name should be something short, e.g., "tx" or "rx". It is for use
70 * by platform_get_resource_byname(). It is defined locally to the
71 * hwmod.
72 */
73struct omap_hwmod_dma_info {
74 const char *name;
75 u16 dma_ch;
76};
77
78/**
79 * struct omap_hwmod_opt_clk - optional clocks used by this hwmod
80 * @role: "sys", "32k", "tv", etc -- for use in clk_get()
81 * @clkdev_dev_id: opt clock: clkdev dev_id string
82 * @clkdev_con_id: opt clock: clkdev con_id string
83 * @_clk: pointer to the struct clk (filled in at runtime)
84 *
85 * The module's interface clock and main functional clock should not
86 * be added as optional clocks.
87 */
88struct omap_hwmod_opt_clk {
89 const char *role;
90 const char *clkdev_dev_id;
91 const char *clkdev_con_id;
92 struct clk *_clk;
93};
94
95
96/* omap_hwmod_omap2_firewall.flags bits */
97#define OMAP_FIREWALL_L3 (1 << 0)
98#define OMAP_FIREWALL_L4 (1 << 1)
99
100/**
101 * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data
102 * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_*
103 * @l4_fw_region: L4 firewall region ID
104 * @l4_prot_group: L4 protection group ID
105 * @flags: (see omap_hwmod_omap2_firewall.flags macros above)
106 */
107struct omap_hwmod_omap2_firewall {
108 u8 l3_perm_bit;
109 u8 l4_fw_region;
110 u8 l4_prot_group;
111 u8 flags;
112};
113
114
115/*
116 * omap_hwmod_addr_space.flags bits
117 *
118 * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init.
119 * ADDR_TYPE_RT: Address space contains module register target data.
120 */
121#define ADDR_MAP_ON_INIT (1 << 0)
122#define ADDR_TYPE_RT (1 << 1)
123
124/**
125 * struct omap_hwmod_addr_space - MPU address space handled by the hwmod
126 * @pa_start: starting physical address
127 * @pa_end: ending physical address
128 * @flags: (see omap_hwmod_addr_space.flags macros above)
129 *
130 * Address space doesn't necessarily follow physical interconnect
131 * structure. GPMC is one example.
132 */
133struct omap_hwmod_addr_space {
134 u32 pa_start;
135 u32 pa_end;
136 u8 flags;
137};
138
139
140/*
141 * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this
142 * interface to interact with the hwmod. Used to add sleep dependencies
143 * when the module is enabled or disabled.
144 */
145#define OCP_USER_MPU (1 << 0)
146#define OCP_USER_SDMA (1 << 1)
147
148/* omap_hwmod_ocp_if.flags bits */
149#define OCPIF_HAS_IDLEST (1 << 0)
150#define OCPIF_SWSUP_IDLE (1 << 1)
151#define OCPIF_CAN_BURST (1 << 2)
152
153/**
154 * struct omap_hwmod_ocp_if - OCP interface data
155 * @master: struct omap_hwmod that initiates OCP transactions on this link
156 * @slave: struct omap_hwmod that responds to OCP transactions on this link
157 * @addr: address space associated with this link
158 * @clkdev_dev_id: interface clock: clkdev dev_id string
159 * @clkdev_con_id: interface clock: clkdev con_id string
160 * @_clk: pointer to the interface struct clk (filled in at runtime)
161 * @fw: interface firewall data
162 * @addr_cnt: ARRAY_SIZE(@addr)
163 * @width: OCP data width
164 * @thread_cnt: number of threads
165 * @max_burst_len: maximum burst length in @width sized words (0 if unlimited)
166 * @user: initiators using this interface (see OCP_USER_* macros above)
167 * @flags: OCP interface flags (see OCPIF_* macros above)
168 *
169 * It may also be useful to add a tag_cnt field for OCP2.x devices.
170 *
171 * Parameter names beginning with an underscore are managed internally by
172 * the omap_hwmod code and should not be set during initialization.
173 */
174struct omap_hwmod_ocp_if {
175 struct omap_hwmod *master;
176 struct omap_hwmod *slave;
177 struct omap_hwmod_addr_space *addr;
178 const char *clkdev_dev_id;
179 const char *clkdev_con_id;
180 struct clk *_clk;
181 union {
182 struct omap_hwmod_omap2_firewall omap2;
183 } fw;
184 u8 addr_cnt;
185 u8 width;
186 u8 thread_cnt;
187 u8 max_burst_len;
188 u8 user;
189 u8 flags;
190};
191
192
193/* Macros for use in struct omap_hwmod_sysconfig */
194
195/* Flags for use in omap_hwmod_sysconfig.idlemodes */
196#define MASTER_STANDBY_SHIFT 2
197#define SLAVE_IDLE_SHIFT 0
198#define SIDLE_FORCE (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT)
199#define SIDLE_NO (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT)
200#define SIDLE_SMART (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT)
201#define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
202#define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
203#define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
204
205/* omap_hwmod_sysconfig.sysc_flags capability flags */
206#define SYSC_HAS_AUTOIDLE (1 << 0)
207#define SYSC_HAS_SOFTRESET (1 << 1)
208#define SYSC_HAS_ENAWAKEUP (1 << 2)
209#define SYSC_HAS_EMUFREE (1 << 3)
210#define SYSC_HAS_CLOCKACTIVITY (1 << 4)
211#define SYSC_HAS_SIDLEMODE (1 << 5)
212#define SYSC_HAS_MIDLEMODE (1 << 6)
213#define SYSS_MISSING (1 << 7)
214
215/* omap_hwmod_sysconfig.clockact flags */
216#define CLOCKACT_TEST_BOTH 0x0
217#define CLOCKACT_TEST_MAIN 0x1
218#define CLOCKACT_TEST_ICLK 0x2
219#define CLOCKACT_TEST_NONE 0x3
220
221/**
222 * struct omap_hwmod_sysconfig - hwmod OCP_SYSCONFIG/OCP_SYSSTATUS data
223 * @rev_offs: IP block revision register offset (from module base addr)
224 * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
225 * @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
226 * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
227 * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
228 * @clockact: the default value of the module CLOCKACTIVITY bits
229 *
230 * @clockact describes to the module which clocks are likely to be
231 * disabled when the PRCM issues its idle request to the module. Some
232 * modules have separate clockdomains for the interface clock and main
233 * functional clock, and can check whether they should acknowledge the
234 * idle request based on the internal module functionality that has
235 * been associated with the clocks marked in @clockact. This field is
236 * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below)
237 *
238 */
239struct omap_hwmod_sysconfig {
240 u16 rev_offs;
241 u16 sysc_offs;
242 u16 syss_offs;
243 u8 idlemodes;
244 u8 sysc_flags;
245 u8 clockact;
246};
247
248/**
249 * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data
250 * @module_offs: PRCM submodule offset from the start of the PRM/CM
251 * @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3)
252 * @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs
253 * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3)
254 * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit
255 * @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit
256 *
257 * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST,
258 * WKEN, GRPSEL registers. In an ideal world, no extra information
259 * would be needed for IDLEST information, but alas, there are some
260 * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit
261 * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST)
262 */
263struct omap_hwmod_omap2_prcm {
264 s16 module_offs;
265 u8 prcm_reg_id;
266 u8 module_bit;
267 u8 idlest_reg_id;
268 u8 idlest_idle_bit;
269 u8 idlest_stdby_bit;
270};
271
272
273/**
274 * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
275 * @module_offs: PRCM submodule offset from the start of the PRM/CM1/CM2
276 * @device_offs: device register offset from @module_offs
277 * @submodule_wkdep_bit: bit shift of the WKDEP range
278 */
279struct omap_hwmod_omap4_prcm {
280 u32 module_offs;
281 u16 device_offs;
282 u8 submodule_wkdep_bit;
283};
284
285
286/*
287 * omap_hwmod.flags definitions
288 *
289 * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
290 * of idle, rather than relying on module smart-idle
291 * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
292 * of standby, rather than relying on module smart-standby
293 * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
294 * SDRAM controller, etc.
295 * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
296 * controller, etc.
297 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
298 */
299#define HWMOD_SWSUP_SIDLE (1 << 0)
300#define HWMOD_SWSUP_MSTANDBY (1 << 1)
301#define HWMOD_INIT_NO_RESET (1 << 2)
302#define HWMOD_INIT_NO_IDLE (1 << 3)
303#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 4)
304
305/*
306 * omap_hwmod._int_flags definitions
307 * These are for internal use only and are managed by the omap_hwmod code.
308 *
309 * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
310 * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
311 * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
312 */
313#define _HWMOD_NO_MPU_PORT (1 << 0)
314#define _HWMOD_WAKEUP_ENABLED (1 << 1)
315#define _HWMOD_SYSCONFIG_LOADED (1 << 2)
316
317/*
318 * omap_hwmod._state definitions
319 *
320 * INITIALIZED: reset (optionally), initialized, enabled, disabled
321 * (optionally)
322 *
323 *
324 */
325#define _HWMOD_STATE_UNKNOWN 0
326#define _HWMOD_STATE_REGISTERED 1
327#define _HWMOD_STATE_CLKS_INITED 2
328#define _HWMOD_STATE_INITIALIZED 3
329#define _HWMOD_STATE_ENABLED 4
330#define _HWMOD_STATE_IDLE 5
331#define _HWMOD_STATE_DISABLED 6
332
333/**
334 * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
335 * @name: name of the hwmod
336 * @od: struct omap_device currently associated with this hwmod (internal use)
337 * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
338 * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt)
339 * @prcm: PRCM data pertaining to this hwmod
340 * @clkdev_dev_id: main clock: clkdev dev_id string
341 * @clkdev_con_id: main clock: clkdev con_id string
342 * @_clk: pointer to the main struct clk (filled in at runtime)
343 * @opt_clks: other device clocks that drivers can request (0..*)
344 * @masters: ptr to array of OCP ifs that this hwmod can initiate on
345 * @slaves: ptr to array of OCP ifs that this hwmod can respond on
346 * @sysconfig: device SYSCONFIG/SYSSTATUS register data
347 * @dev_attr: arbitrary device attributes that can be passed to the driver
348 * @_sysc_cache: internal-use hwmod flags
349 * @_rt_va: cached register target start address (internal use)
350 * @_mpu_port_index: cached MPU register target slave ID (internal use)
351 * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6)
352 * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift
353 * @mpu_irqs_cnt: number of @mpu_irqs
354 * @sdma_chs_cnt: number of @sdma_chs
355 * @opt_clks_cnt: number of @opt_clks
356 * @master_cnt: number of @master entries
357 * @slaves_cnt: number of @slave entries
358 * @response_lat: device OCP response latency (in interface clock cycles)
359 * @_int_flags: internal-use hwmod flags
360 * @_state: internal-use hwmod state
361 * @flags: hwmod flags (documented below)
362 * @omap_chip: OMAP chips this hwmod is present on
363 * @node: list node for hwmod list (internal use)
364 *
365 * @clkdev_dev_id, @clkdev_con_id, and @clk all refer to this module's "main
366 * clock," which for our purposes is defined as "the functional clock needed
367 * for register accesses to complete." Modules may not have a main clock if
368 * the interface clock also serves as a main clock.
369 *
370 * Parameter names beginning with an underscore are managed internally by
371 * the omap_hwmod code and should not be set during initialization.
372 */
373struct omap_hwmod {
374 const char *name;
375 struct omap_device *od;
376 u8 *mpu_irqs;
377 struct omap_hwmod_dma_info *sdma_chs;
378 union {
379 struct omap_hwmod_omap2_prcm omap2;
380 struct omap_hwmod_omap4_prcm omap4;
381 } prcm;
382 const char *clkdev_dev_id;
383 const char *clkdev_con_id;
384 struct clk *_clk;
385 struct omap_hwmod_opt_clk *opt_clks;
386 struct omap_hwmod_ocp_if **masters; /* connect to *_IA */
387 struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */
388 struct omap_hwmod_sysconfig *sysconfig;
389 void *dev_attr;
390 u32 _sysc_cache;
391 void __iomem *_rt_va;
392 struct list_head node;
393 u16 flags;
394 u8 _mpu_port_index;
395 u8 msuspendmux_reg_id;
396 u8 msuspendmux_shift;
397 u8 response_lat;
398 u8 mpu_irqs_cnt;
399 u8 sdma_chs_cnt;
400 u8 opt_clks_cnt;
401 u8 masters_cnt;
402 u8 slaves_cnt;
403 u8 hwmods_cnt;
404 u8 _int_flags;
405 u8 _state;
406 const struct omap_chip_id omap_chip;
407};
408
409int omap_hwmod_init(struct omap_hwmod **ohs);
410int omap_hwmod_register(struct omap_hwmod *oh);
411int omap_hwmod_unregister(struct omap_hwmod *oh);
412struct omap_hwmod *omap_hwmod_lookup(const char *name);
413int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh));
414int omap_hwmod_late_init(void);
415
416int omap_hwmod_enable(struct omap_hwmod *oh);
417int omap_hwmod_idle(struct omap_hwmod *oh);
418int omap_hwmod_shutdown(struct omap_hwmod *oh);
419
420int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
421int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
422
423int omap_hwmod_reset(struct omap_hwmod *oh);
424void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
425
426void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs);
427u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs);
428
429int omap_hwmod_count_resources(struct omap_hwmod *oh);
430int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
431
432struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
433
434int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
435 struct omap_hwmod *init_oh);
436int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
437 struct omap_hwmod *init_oh);
438
439int omap_hwmod_set_clockact_both(struct omap_hwmod *oh);
440int omap_hwmod_set_clockact_main(struct omap_hwmod *oh);
441int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh);
442int omap_hwmod_set_clockact_none(struct omap_hwmod *oh);
443
444int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
445int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
446
447#endif
diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h b/arch/arm/plat-omap/include/mach/powerdomain.h
index 69c9e675d8ee..6271d8556a40 100644
--- a/arch/arm/plat-omap/include/mach/powerdomain.h
+++ b/arch/arm/plat-omap/include/mach/powerdomain.h
@@ -117,6 +117,13 @@ struct powerdomain {
117 117
118 struct list_head node; 118 struct list_head node;
119 119
120 int state;
121 unsigned state_counter[4];
122
123#ifdef CONFIG_PM_DEBUG
124 s64 timer;
125 s64 state_timer[4];
126#endif
120}; 127};
121 128
122 129
@@ -126,7 +133,8 @@ int pwrdm_register(struct powerdomain *pwrdm);
126int pwrdm_unregister(struct powerdomain *pwrdm); 133int pwrdm_unregister(struct powerdomain *pwrdm);
127struct powerdomain *pwrdm_lookup(const char *name); 134struct powerdomain *pwrdm_lookup(const char *name);
128 135
129int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm)); 136int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
137 void *user);
130 138
131int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); 139int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
132int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); 140int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
@@ -164,4 +172,9 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
164 172
165int pwrdm_wait_transition(struct powerdomain *pwrdm); 173int pwrdm_wait_transition(struct powerdomain *pwrdm);
166 174
175int pwrdm_state_switch(struct powerdomain *pwrdm);
176int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
177int pwrdm_pre_transition(void);
178int pwrdm_post_transition(void);
179
167#endif 180#endif
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h
index 0be18e4ff182..1c09c78a48f2 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/mach/sdrc.h
@@ -21,19 +21,28 @@
21/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */ 21/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
22 22
23#define SDRC_SYSCONFIG 0x010 23#define SDRC_SYSCONFIG 0x010
24#define SDRC_CS_CFG 0x040
25#define SDRC_SHARING 0x044
26#define SDRC_ERR_TYPE 0x04C
24#define SDRC_DLLA_CTRL 0x060 27#define SDRC_DLLA_CTRL 0x060
25#define SDRC_DLLA_STATUS 0x064 28#define SDRC_DLLA_STATUS 0x064
26#define SDRC_DLLB_CTRL 0x068 29#define SDRC_DLLB_CTRL 0x068
27#define SDRC_DLLB_STATUS 0x06C 30#define SDRC_DLLB_STATUS 0x06C
28#define SDRC_POWER 0x070 31#define SDRC_POWER 0x070
32#define SDRC_MCFG_0 0x080
29#define SDRC_MR_0 0x084 33#define SDRC_MR_0 0x084
34#define SDRC_EMR2_0 0x08c
30#define SDRC_ACTIM_CTRL_A_0 0x09c 35#define SDRC_ACTIM_CTRL_A_0 0x09c
31#define SDRC_ACTIM_CTRL_B_0 0x0a0 36#define SDRC_ACTIM_CTRL_B_0 0x0a0
32#define SDRC_RFR_CTRL_0 0x0a4 37#define SDRC_RFR_CTRL_0 0x0a4
38#define SDRC_MANUAL_0 0x0a8
39#define SDRC_MCFG_1 0x0B0
33#define SDRC_MR_1 0x0B4 40#define SDRC_MR_1 0x0B4
41#define SDRC_EMR2_1 0x0BC
34#define SDRC_ACTIM_CTRL_A_1 0x0C4 42#define SDRC_ACTIM_CTRL_A_1 0x0C4
35#define SDRC_ACTIM_CTRL_B_1 0x0C8 43#define SDRC_ACTIM_CTRL_B_1 0x0C8
36#define SDRC_RFR_CTRL_1 0x0D4 44#define SDRC_RFR_CTRL_1 0x0D4
45#define SDRC_MANUAL_1 0x0D8
37 46
38/* 47/*
39 * These values represent the number of memory clock cycles between 48 * These values represent the number of memory clock cycles between
@@ -71,11 +80,11 @@
71 */ 80 */
72 81
73#define OMAP242X_SMS_REGADDR(reg) \ 82#define OMAP242X_SMS_REGADDR(reg) \
74 (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg) 83 (void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
75#define OMAP243X_SMS_REGADDR(reg) \ 84#define OMAP243X_SMS_REGADDR(reg) \
76 (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg) 85 (void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
77#define OMAP343X_SMS_REGADDR(reg) \ 86#define OMAP343X_SMS_REGADDR(reg) \
78 (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg) 87 (void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
79 88
80/* SMS register offsets - read/write with sms_{read,write}_reg() */ 89/* SMS register offsets - read/write with sms_{read,write}_reg() */
81 90
diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/mach/serial.h
index def0529c75eb..e249186d26e2 100644
--- a/arch/arm/plat-omap/include/mach/serial.h
+++ b/arch/arm/plat-omap/include/mach/serial.h
@@ -13,6 +13,8 @@
13#ifndef __ASM_ARCH_SERIAL_H 13#ifndef __ASM_ARCH_SERIAL_H
14#define __ASM_ARCH_SERIAL_H 14#define __ASM_ARCH_SERIAL_H
15 15
16#include <linux/init.h>
17
16#if defined(CONFIG_ARCH_OMAP1) 18#if defined(CONFIG_ARCH_OMAP1)
17/* OMAP1 serial ports */ 19/* OMAP1 serial ports */
18#define OMAP_UART1_BASE 0xfffb0000 20#define OMAP_UART1_BASE 0xfffb0000
@@ -53,6 +55,7 @@
53 }) 55 })
54 56
55#ifndef __ASSEMBLER__ 57#ifndef __ASSEMBLER__
58extern void __init omap_serial_early_init(void);
56extern void omap_serial_init(void); 59extern void omap_serial_init(void);
57extern int omap_uart_can_sleep(void); 60extern int omap_uart_can_sleep(void);
58extern void omap_uart_check_wakeup(void); 61extern void omap_uart_check_wakeup(void);
diff --git a/arch/arm/plat-omap/include/mach/system.h b/arch/arm/plat-omap/include/mach/system.h
index 1060e345423b..ed8ec7477261 100644
--- a/arch/arm/plat-omap/include/mach/system.h
+++ b/arch/arm/plat-omap/include/mach/system.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copied from arch/arm/mach-sa1100/include/mach/system.h 2 * Copied from arch/arm/mach-sa1100/include/mach/system.h
3 * Copyright (c) 1999 Nicolas Pitre <nico@cam.org> 3 * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
4 */ 4 */
5#ifndef __ASM_ARCH_SYSTEM_H 5#ifndef __ASM_ARCH_SYSTEM_H
6#define __ASM_ARCH_SYSTEM_H 6#define __ASM_ARCH_SYSTEM_H
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index 9b42d72d96cf..b6defa23e77e 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -30,8 +30,8 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
30{ 30{
31#ifdef CONFIG_ARCH_OMAP1 31#ifdef CONFIG_ARCH_OMAP1
32 if (cpu_class_is_omap1()) { 32 if (cpu_class_is_omap1()) {
33 if (BETWEEN(p, IO_PHYS, IO_SIZE)) 33 if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE))
34 return XLATE(p, IO_PHYS, IO_VIRT); 34 return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT);
35 } 35 }
36 if (cpu_is_omap730()) { 36 if (cpu_is_omap730()) {
37 if (BETWEEN(p, OMAP730_DSP_BASE, OMAP730_DSP_SIZE)) 37 if (BETWEEN(p, OMAP730_DSP_BASE, OMAP730_DSP_SIZE))
@@ -132,3 +132,61 @@ void omap_iounmap(volatile void __iomem *addr)
132 __iounmap(addr); 132 __iounmap(addr);
133} 133}
134EXPORT_SYMBOL(omap_iounmap); 134EXPORT_SYMBOL(omap_iounmap);
135
136/*
137 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
138 */
139
140u8 omap_readb(u32 pa)
141{
142 if (cpu_class_is_omap1())
143 return __raw_readb(OMAP1_IO_ADDRESS(pa));
144 else
145 return __raw_readb(OMAP2_IO_ADDRESS(pa));
146}
147EXPORT_SYMBOL(omap_readb);
148
149u16 omap_readw(u32 pa)
150{
151 if (cpu_class_is_omap1())
152 return __raw_readw(OMAP1_IO_ADDRESS(pa));
153 else
154 return __raw_readw(OMAP2_IO_ADDRESS(pa));
155}
156EXPORT_SYMBOL(omap_readw);
157
158u32 omap_readl(u32 pa)
159{
160 if (cpu_class_is_omap1())
161 return __raw_readl(OMAP1_IO_ADDRESS(pa));
162 else
163 return __raw_readl(OMAP2_IO_ADDRESS(pa));
164}
165EXPORT_SYMBOL(omap_readl);
166
167void omap_writeb(u8 v, u32 pa)
168{
169 if (cpu_class_is_omap1())
170 __raw_writeb(v, OMAP1_IO_ADDRESS(pa));
171 else
172 __raw_writeb(v, OMAP2_IO_ADDRESS(pa));
173}
174EXPORT_SYMBOL(omap_writeb);
175
176void omap_writew(u16 v, u32 pa)
177{
178 if (cpu_class_is_omap1())
179 __raw_writew(v, OMAP1_IO_ADDRESS(pa));
180 else
181 __raw_writew(v, OMAP2_IO_ADDRESS(pa));
182}
183EXPORT_SYMBOL(omap_writew);
184
185void omap_writel(u32 v, u32 pa)
186{
187 if (cpu_class_is_omap1())
188 __raw_writel(v, OMAP1_IO_ADDRESS(pa));
189 else
190 __raw_writel(v, OMAP2_IO_ADDRESS(pa));
191}
192EXPORT_SYMBOL(omap_writel);
diff --git a/arch/arm/plat-omap/iommu-debug.c b/arch/arm/plat-omap/iommu-debug.c
new file mode 100644
index 000000000000..c799b3b0d709
--- /dev/null
+++ b/arch/arm/plat-omap/iommu-debug.c
@@ -0,0 +1,415 @@
1/*
2 * omap iommu: debugfs interface
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/err.h>
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/uaccess.h>
17#include <linux/platform_device.h>
18#include <linux/debugfs.h>
19
20#include <mach/iommu.h>
21#include <mach/iovmm.h>
22
23#include "iopgtable.h"
24
25#define MAXCOLUMN 100 /* for short messages */
26
27static DEFINE_MUTEX(iommu_debug_lock);
28
29static struct dentry *iommu_debug_root;
30
31static ssize_t debug_read_ver(struct file *file, char __user *userbuf,
32 size_t count, loff_t *ppos)
33{
34 u32 ver = iommu_arch_version();
35 char buf[MAXCOLUMN], *p = buf;
36
37 p += sprintf(p, "H/W version: %d.%d\n", (ver >> 4) & 0xf , ver & 0xf);
38
39 return simple_read_from_buffer(userbuf, count, ppos, buf, p - buf);
40}
41
42static ssize_t debug_read_regs(struct file *file, char __user *userbuf,
43 size_t count, loff_t *ppos)
44{
45 struct iommu *obj = file->private_data;
46 char *p, *buf;
47 ssize_t bytes;
48
49 buf = kmalloc(count, GFP_KERNEL);
50 if (!buf)
51 return -ENOMEM;
52 p = buf;
53
54 mutex_lock(&iommu_debug_lock);
55
56 bytes = iommu_dump_ctx(obj, p, count);
57 bytes = simple_read_from_buffer(userbuf, count, ppos, buf, bytes);
58
59 mutex_unlock(&iommu_debug_lock);
60 kfree(buf);
61
62 return bytes;
63}
64
65static ssize_t debug_read_tlb(struct file *file, char __user *userbuf,
66 size_t count, loff_t *ppos)
67{
68 struct iommu *obj = file->private_data;
69 char *p, *buf;
70 ssize_t bytes, rest;
71
72 buf = kmalloc(count, GFP_KERNEL);
73 if (!buf)
74 return -ENOMEM;
75 p = buf;
76
77 mutex_lock(&iommu_debug_lock);
78
79 p += sprintf(p, "%8s %8s\n", "cam:", "ram:");
80 p += sprintf(p, "-----------------------------------------\n");
81 rest = count - (p - buf);
82 p += dump_tlb_entries(obj, p, rest);
83
84 bytes = simple_read_from_buffer(userbuf, count, ppos, buf, p - buf);
85
86 mutex_unlock(&iommu_debug_lock);
87 kfree(buf);
88
89 return bytes;
90}
91
92static ssize_t debug_write_pagetable(struct file *file,
93 const char __user *userbuf, size_t count, loff_t *ppos)
94{
95 struct iotlb_entry e;
96 struct cr_regs cr;
97 int err;
98 struct iommu *obj = file->private_data;
99 char buf[MAXCOLUMN], *p = buf;
100
101 count = min(count, sizeof(buf));
102
103 mutex_lock(&iommu_debug_lock);
104 if (copy_from_user(p, userbuf, count)) {
105 mutex_unlock(&iommu_debug_lock);
106 return -EFAULT;
107 }
108
109 sscanf(p, "%x %x", &cr.cam, &cr.ram);
110 if (!cr.cam || !cr.ram) {
111 mutex_unlock(&iommu_debug_lock);
112 return -EINVAL;
113 }
114
115 iotlb_cr_to_e(&cr, &e);
116 err = iopgtable_store_entry(obj, &e);
117 if (err)
118 dev_err(obj->dev, "%s: fail to store cr\n", __func__);
119
120 mutex_unlock(&iommu_debug_lock);
121 return count;
122}
123
124#define dump_ioptable_entry_one(lv, da, val) \
125 ({ \
126 int __err = 0; \
127 ssize_t bytes; \
128 const int maxcol = 22; \
129 const char *str = "%d: %08x %08x\n"; \
130 bytes = snprintf(p, maxcol, str, lv, da, val); \
131 p += bytes; \
132 len -= bytes; \
133 if (len < maxcol) \
134 __err = -ENOMEM; \
135 __err; \
136 })
137
138static ssize_t dump_ioptable(struct iommu *obj, char *buf, ssize_t len)
139{
140 int i;
141 u32 *iopgd;
142 char *p = buf;
143
144 spin_lock(&obj->page_table_lock);
145
146 iopgd = iopgd_offset(obj, 0);
147 for (i = 0; i < PTRS_PER_IOPGD; i++, iopgd++) {
148 int j, err;
149 u32 *iopte;
150 u32 da;
151
152 if (!*iopgd)
153 continue;
154
155 if (!(*iopgd & IOPGD_TABLE)) {
156 da = i << IOPGD_SHIFT;
157
158 err = dump_ioptable_entry_one(1, da, *iopgd);
159 if (err)
160 goto out;
161 continue;
162 }
163
164 iopte = iopte_offset(iopgd, 0);
165
166 for (j = 0; j < PTRS_PER_IOPTE; j++, iopte++) {
167 if (!*iopte)
168 continue;
169
170 da = (i << IOPGD_SHIFT) + (j << IOPTE_SHIFT);
171 err = dump_ioptable_entry_one(2, da, *iopgd);
172 if (err)
173 goto out;
174 }
175 }
176out:
177 spin_unlock(&obj->page_table_lock);
178
179 return p - buf;
180}
181
182static ssize_t debug_read_pagetable(struct file *file, char __user *userbuf,
183 size_t count, loff_t *ppos)
184{
185 struct iommu *obj = file->private_data;
186 char *p, *buf;
187 size_t bytes;
188
189 buf = (char *)__get_free_page(GFP_KERNEL);
190 if (!buf)
191 return -ENOMEM;
192 p = buf;
193
194 p += sprintf(p, "L: %8s %8s\n", "da:", "pa:");
195 p += sprintf(p, "-----------------------------------------\n");
196
197 mutex_lock(&iommu_debug_lock);
198
199 bytes = PAGE_SIZE - (p - buf);
200 p += dump_ioptable(obj, p, bytes);
201
202 bytes = simple_read_from_buffer(userbuf, count, ppos, buf, p - buf);
203
204 mutex_unlock(&iommu_debug_lock);
205 free_page((unsigned long)buf);
206
207 return bytes;
208}
209
210static ssize_t debug_read_mmap(struct file *file, char __user *userbuf,
211 size_t count, loff_t *ppos)
212{
213 struct iommu *obj = file->private_data;
214 char *p, *buf;
215 struct iovm_struct *tmp;
216 int uninitialized_var(i);
217 ssize_t bytes;
218
219 buf = (char *)__get_free_page(GFP_KERNEL);
220 if (!buf)
221 return -ENOMEM;
222 p = buf;
223
224 p += sprintf(p, "%-3s %-8s %-8s %6s %8s\n",
225 "No", "start", "end", "size", "flags");
226 p += sprintf(p, "-------------------------------------------------\n");
227
228 mutex_lock(&iommu_debug_lock);
229
230 list_for_each_entry(tmp, &obj->mmap, list) {
231 size_t len;
232 const char *str = "%3d %08x-%08x %6x %8x\n";
233 const int maxcol = 39;
234
235 len = tmp->da_end - tmp->da_start;
236 p += snprintf(p, maxcol, str,
237 i, tmp->da_start, tmp->da_end, len, tmp->flags);
238
239 if (PAGE_SIZE - (p - buf) < maxcol)
240 break;
241 i++;
242 }
243
244 bytes = simple_read_from_buffer(userbuf, count, ppos, buf, p - buf);
245
246 mutex_unlock(&iommu_debug_lock);
247 free_page((unsigned long)buf);
248
249 return bytes;
250}
251
252static ssize_t debug_read_mem(struct file *file, char __user *userbuf,
253 size_t count, loff_t *ppos)
254{
255 struct iommu *obj = file->private_data;
256 char *p, *buf;
257 struct iovm_struct *area;
258 ssize_t bytes;
259
260 count = min_t(ssize_t, count, PAGE_SIZE);
261
262 buf = (char *)__get_free_page(GFP_KERNEL);
263 if (!buf)
264 return -ENOMEM;
265 p = buf;
266
267 mutex_lock(&iommu_debug_lock);
268
269 area = find_iovm_area(obj, (u32)ppos);
270 if (IS_ERR(area)) {
271 bytes = -EINVAL;
272 goto err_out;
273 }
274 memcpy(p, area->va, count);
275 p += count;
276
277 bytes = simple_read_from_buffer(userbuf, count, ppos, buf, p - buf);
278err_out:
279 mutex_unlock(&iommu_debug_lock);
280 free_page((unsigned long)buf);
281
282 return bytes;
283}
284
285static ssize_t debug_write_mem(struct file *file, const char __user *userbuf,
286 size_t count, loff_t *ppos)
287{
288 struct iommu *obj = file->private_data;
289 struct iovm_struct *area;
290 char *p, *buf;
291
292 count = min_t(size_t, count, PAGE_SIZE);
293
294 buf = (char *)__get_free_page(GFP_KERNEL);
295 if (!buf)
296 return -ENOMEM;
297 p = buf;
298
299 mutex_lock(&iommu_debug_lock);
300
301 if (copy_from_user(p, userbuf, count)) {
302 count = -EFAULT;
303 goto err_out;
304 }
305
306 area = find_iovm_area(obj, (u32)ppos);
307 if (IS_ERR(area)) {
308 count = -EINVAL;
309 goto err_out;
310 }
311 memcpy(area->va, p, count);
312err_out:
313 mutex_unlock(&iommu_debug_lock);
314 free_page((unsigned long)buf);
315
316 return count;
317}
318
319static int debug_open_generic(struct inode *inode, struct file *file)
320{
321 file->private_data = inode->i_private;
322 return 0;
323}
324
325#define DEBUG_FOPS(name) \
326 static const struct file_operations debug_##name##_fops = { \
327 .open = debug_open_generic, \
328 .read = debug_read_##name, \
329 .write = debug_write_##name, \
330 };
331
332#define DEBUG_FOPS_RO(name) \
333 static const struct file_operations debug_##name##_fops = { \
334 .open = debug_open_generic, \
335 .read = debug_read_##name, \
336 };
337
338DEBUG_FOPS_RO(ver);
339DEBUG_FOPS_RO(regs);
340DEBUG_FOPS_RO(tlb);
341DEBUG_FOPS(pagetable);
342DEBUG_FOPS_RO(mmap);
343DEBUG_FOPS(mem);
344
345#define __DEBUG_ADD_FILE(attr, mode) \
346 { \
347 struct dentry *dent; \
348 dent = debugfs_create_file(#attr, mode, parent, \
349 obj, &debug_##attr##_fops); \
350 if (!dent) \
351 return -ENOMEM; \
352 }
353
354#define DEBUG_ADD_FILE(name) __DEBUG_ADD_FILE(name, 600)
355#define DEBUG_ADD_FILE_RO(name) __DEBUG_ADD_FILE(name, 400)
356
357static int iommu_debug_register(struct device *dev, void *data)
358{
359 struct platform_device *pdev = to_platform_device(dev);
360 struct iommu *obj = platform_get_drvdata(pdev);
361 struct dentry *d, *parent;
362
363 if (!obj || !obj->dev)
364 return -EINVAL;
365
366 d = debugfs_create_dir(obj->name, iommu_debug_root);
367 if (!d)
368 return -ENOMEM;
369 parent = d;
370
371 d = debugfs_create_u8("nr_tlb_entries", 400, parent,
372 (u8 *)&obj->nr_tlb_entries);
373 if (!d)
374 return -ENOMEM;
375
376 DEBUG_ADD_FILE_RO(ver);
377 DEBUG_ADD_FILE_RO(regs);
378 DEBUG_ADD_FILE_RO(tlb);
379 DEBUG_ADD_FILE(pagetable);
380 DEBUG_ADD_FILE_RO(mmap);
381 DEBUG_ADD_FILE(mem);
382
383 return 0;
384}
385
386static int __init iommu_debug_init(void)
387{
388 struct dentry *d;
389 int err;
390
391 d = debugfs_create_dir("iommu", NULL);
392 if (!d)
393 return -ENOMEM;
394 iommu_debug_root = d;
395
396 err = foreach_iommu_device(d, iommu_debug_register);
397 if (err)
398 goto err_out;
399 return 0;
400
401err_out:
402 debugfs_remove_recursive(iommu_debug_root);
403 return err;
404}
405module_init(iommu_debug_init)
406
407static void __exit iommu_debugfs_exit(void)
408{
409 debugfs_remove_recursive(iommu_debug_root);
410}
411module_exit(iommu_debugfs_exit)
412
413MODULE_DESCRIPTION("omap iommu: debugfs interface");
414MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
415MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index 4a0301399013..4b6012707307 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -351,16 +351,14 @@ EXPORT_SYMBOL_GPL(flush_iotlb_all);
351 351
352#if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) 352#if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
353 353
354ssize_t iommu_dump_ctx(struct iommu *obj, char *buf) 354ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes)
355{ 355{
356 ssize_t bytes;
357
358 if (!obj || !buf) 356 if (!obj || !buf)
359 return -EINVAL; 357 return -EINVAL;
360 358
361 clk_enable(obj->clk); 359 clk_enable(obj->clk);
362 360
363 bytes = arch_iommu->dump_ctx(obj, buf); 361 bytes = arch_iommu->dump_ctx(obj, buf, bytes);
364 362
365 clk_disable(obj->clk); 363 clk_disable(obj->clk);
366 364
@@ -368,7 +366,7 @@ ssize_t iommu_dump_ctx(struct iommu *obj, char *buf)
368} 366}
369EXPORT_SYMBOL_GPL(iommu_dump_ctx); 367EXPORT_SYMBOL_GPL(iommu_dump_ctx);
370 368
371static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs) 369static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs, int num)
372{ 370{
373 int i; 371 int i;
374 struct iotlb_lock saved, l; 372 struct iotlb_lock saved, l;
@@ -379,7 +377,7 @@ static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs)
379 iotlb_lock_get(obj, &saved); 377 iotlb_lock_get(obj, &saved);
380 memcpy(&l, &saved, sizeof(saved)); 378 memcpy(&l, &saved, sizeof(saved));
381 379
382 for (i = 0; i < obj->nr_tlb_entries; i++) { 380 for (i = 0; i < num; i++) {
383 struct cr_regs tmp; 381 struct cr_regs tmp;
384 382
385 iotlb_lock_get(obj, &l); 383 iotlb_lock_get(obj, &l);
@@ -402,18 +400,21 @@ static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs)
402 * @obj: target iommu 400 * @obj: target iommu
403 * @buf: output buffer 401 * @buf: output buffer
404 **/ 402 **/
405size_t dump_tlb_entries(struct iommu *obj, char *buf) 403size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t bytes)
406{ 404{
407 int i, n; 405 int i, num;
408 struct cr_regs *cr; 406 struct cr_regs *cr;
409 char *p = buf; 407 char *p = buf;
410 408
411 cr = kcalloc(obj->nr_tlb_entries, sizeof(*cr), GFP_KERNEL); 409 num = bytes / sizeof(*cr);
410 num = min(obj->nr_tlb_entries, num);
411
412 cr = kcalloc(num, sizeof(*cr), GFP_KERNEL);
412 if (!cr) 413 if (!cr)
413 return 0; 414 return 0;
414 415
415 n = __dump_tlb_entries(obj, cr); 416 num = __dump_tlb_entries(obj, cr, num);
416 for (i = 0; i < n; i++) 417 for (i = 0; i < num; i++)
417 p += iotlb_dump_cr(obj, cr + i, p); 418 p += iotlb_dump_cr(obj, cr + i, p);
418 kfree(cr); 419 kfree(cr);
419 420
diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c
index 2fce2c151a95..6fc52fcbdc03 100644
--- a/arch/arm/plat-omap/iovmm.c
+++ b/arch/arm/plat-omap/iovmm.c
@@ -199,7 +199,7 @@ static void *vmap_sg(const struct sg_table *sgt)
199 va += bytes; 199 va += bytes;
200 } 200 }
201 201
202 flush_cache_vmap(new->addr, total); 202 flush_cache_vmap(new->addr, new->addr + total);
203 return new->addr; 203 return new->addr;
204 204
205err_out: 205err_out:
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index efa0e0111f38..88ac9768f1c1 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -191,13 +191,177 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
191 OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2); 191 OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
192 OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1); 192 OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
193 OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0); 193 OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
194 if (cpu_is_omap2430() || cpu_is_omap34xx()) { 194 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
195 OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr); 195 OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
196 OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr); 196 OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
197 } 197 }
198} 198}
199EXPORT_SYMBOL(omap_mcbsp_config); 199EXPORT_SYMBOL(omap_mcbsp_config);
200 200
201#ifdef CONFIG_ARCH_OMAP34XX
202/*
203 * omap_mcbsp_set_tx_threshold configures how to deal
204 * with transmit threshold. the threshold value and handler can be
205 * configure in here.
206 */
207void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
208{
209 struct omap_mcbsp *mcbsp;
210 void __iomem *io_base;
211
212 if (!cpu_is_omap34xx())
213 return;
214
215 if (!omap_mcbsp_check_valid_id(id)) {
216 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
217 return;
218 }
219 mcbsp = id_to_mcbsp_ptr(id);
220 io_base = mcbsp->io_base;
221
222 OMAP_MCBSP_WRITE(io_base, THRSH2, threshold);
223}
224EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
225
226/*
227 * omap_mcbsp_set_rx_threshold configures how to deal
228 * with receive threshold. the threshold value and handler can be
229 * configure in here.
230 */
231void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
232{
233 struct omap_mcbsp *mcbsp;
234 void __iomem *io_base;
235
236 if (!cpu_is_omap34xx())
237 return;
238
239 if (!omap_mcbsp_check_valid_id(id)) {
240 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
241 return;
242 }
243 mcbsp = id_to_mcbsp_ptr(id);
244 io_base = mcbsp->io_base;
245
246 OMAP_MCBSP_WRITE(io_base, THRSH1, threshold);
247}
248EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
249
250/*
251 * omap_mcbsp_get_max_tx_thres just return the current configured
252 * maximum threshold for transmission
253 */
254u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
255{
256 struct omap_mcbsp *mcbsp;
257
258 if (!omap_mcbsp_check_valid_id(id)) {
259 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
260 return -ENODEV;
261 }
262 mcbsp = id_to_mcbsp_ptr(id);
263
264 return mcbsp->max_tx_thres;
265}
266EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
267
268/*
269 * omap_mcbsp_get_max_rx_thres just return the current configured
270 * maximum threshold for reception
271 */
272u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
273{
274 struct omap_mcbsp *mcbsp;
275
276 if (!omap_mcbsp_check_valid_id(id)) {
277 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
278 return -ENODEV;
279 }
280 mcbsp = id_to_mcbsp_ptr(id);
281
282 return mcbsp->max_rx_thres;
283}
284EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
285
286/*
287 * omap_mcbsp_get_dma_op_mode just return the current configured
288 * operating mode for the mcbsp channel
289 */
290int omap_mcbsp_get_dma_op_mode(unsigned int id)
291{
292 struct omap_mcbsp *mcbsp;
293 int dma_op_mode;
294
295 if (!omap_mcbsp_check_valid_id(id)) {
296 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
297 return -ENODEV;
298 }
299 mcbsp = id_to_mcbsp_ptr(id);
300
301 spin_lock_irq(&mcbsp->lock);
302 dma_op_mode = mcbsp->dma_op_mode;
303 spin_unlock_irq(&mcbsp->lock);
304
305 return dma_op_mode;
306}
307EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
308
309static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
310{
311 /*
312 * Enable wakup behavior, smart idle and all wakeups
313 * REVISIT: some wakeups may be unnecessary
314 */
315 if (cpu_is_omap34xx()) {
316 u16 syscon;
317
318 syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
319 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
320
321 spin_lock_irq(&mcbsp->lock);
322 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
323 syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
324 CLOCKACTIVITY(0x02));
325 OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN,
326 XRDYEN | RRDYEN);
327 } else {
328 syscon |= SIDLEMODE(0x01);
329 }
330 spin_unlock_irq(&mcbsp->lock);
331
332 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
333 }
334}
335
336static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
337{
338 /*
339 * Disable wakup behavior, smart idle and all wakeups
340 */
341 if (cpu_is_omap34xx()) {
342 u16 syscon;
343
344 syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
345 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
346 /*
347 * HW bug workaround - If no_idle mode is taken, we need to
348 * go to smart_idle before going to always_idle, or the
349 * device will not hit retention anymore.
350 */
351 syscon |= SIDLEMODE(0x02);
352 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
353
354 syscon &= ~(SIDLEMODE(0x03));
355 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
356
357 OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN, 0);
358 }
359}
360#else
361static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
362static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
363#endif
364
201/* 365/*
202 * We can choose between IRQ based or polled IO. 366 * We can choose between IRQ based or polled IO.
203 * This needs to be called before omap_mcbsp_request(). 367 * This needs to be called before omap_mcbsp_request().
@@ -257,6 +421,9 @@ int omap_mcbsp_request(unsigned int id)
257 clk_enable(mcbsp->iclk); 421 clk_enable(mcbsp->iclk);
258 clk_enable(mcbsp->fclk); 422 clk_enable(mcbsp->fclk);
259 423
424 /* Do procedure specific to omap34xx arch, if applicable */
425 omap34xx_mcbsp_request(mcbsp);
426
260 /* 427 /*
261 * Make sure that transmitter, receiver and sample-rate generator are 428 * Make sure that transmitter, receiver and sample-rate generator are
262 * not running before activating IRQs. 429 * not running before activating IRQs.
@@ -305,6 +472,9 @@ void omap_mcbsp_free(unsigned int id)
305 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free) 472 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
306 mcbsp->pdata->ops->free(id); 473 mcbsp->pdata->ops->free(id);
307 474
475 /* Do procedure specific to omap34xx arch, if applicable */
476 omap34xx_mcbsp_free(mcbsp);
477
308 clk_disable(mcbsp->fclk); 478 clk_disable(mcbsp->fclk);
309 clk_disable(mcbsp->iclk); 479 clk_disable(mcbsp->iclk);
310 480
@@ -328,14 +498,15 @@ void omap_mcbsp_free(unsigned int id)
328EXPORT_SYMBOL(omap_mcbsp_free); 498EXPORT_SYMBOL(omap_mcbsp_free);
329 499
330/* 500/*
331 * Here we start the McBSP, by enabling the sample 501 * Here we start the McBSP, by enabling transmitter, receiver or both.
332 * generator, both transmitter and receivers, 502 * If no transmitter or receiver is active prior calling, then sample-rate
333 * and the frame sync. 503 * generator and frame sync are started.
334 */ 504 */
335void omap_mcbsp_start(unsigned int id) 505void omap_mcbsp_start(unsigned int id, int tx, int rx)
336{ 506{
337 struct omap_mcbsp *mcbsp; 507 struct omap_mcbsp *mcbsp;
338 void __iomem *io_base; 508 void __iomem *io_base;
509 int idle;
339 u16 w; 510 u16 w;
340 511
341 if (!omap_mcbsp_check_valid_id(id)) { 512 if (!omap_mcbsp_check_valid_id(id)) {
@@ -348,32 +519,58 @@ void omap_mcbsp_start(unsigned int id)
348 mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7; 519 mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
349 mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7; 520 mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
350 521
351 /* Start the sample generator */ 522 idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
352 w = OMAP_MCBSP_READ(io_base, SPCR2); 523 OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
353 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6)); 524
525 if (idle) {
526 /* Start the sample generator */
527 w = OMAP_MCBSP_READ(io_base, SPCR2);
528 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
529 }
354 530
355 /* Enable transmitter and receiver */ 531 /* Enable transmitter and receiver */
532 tx &= 1;
356 w = OMAP_MCBSP_READ(io_base, SPCR2); 533 w = OMAP_MCBSP_READ(io_base, SPCR2);
357 OMAP_MCBSP_WRITE(io_base, SPCR2, w | 1); 534 OMAP_MCBSP_WRITE(io_base, SPCR2, w | tx);
358 535
536 rx &= 1;
359 w = OMAP_MCBSP_READ(io_base, SPCR1); 537 w = OMAP_MCBSP_READ(io_base, SPCR1);
360 OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1); 538 OMAP_MCBSP_WRITE(io_base, SPCR1, w | rx);
361 539
362 udelay(100); 540 /*
541 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
542 * REVISIT: 100us may give enough time for two CLKSRG, however
543 * due to some unknown PM related, clock gating etc. reason it
544 * is now at 500us.
545 */
546 udelay(500);
363 547
364 /* Start frame sync */ 548 if (idle) {
365 w = OMAP_MCBSP_READ(io_base, SPCR2); 549 /* Start frame sync */
366 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7)); 550 w = OMAP_MCBSP_READ(io_base, SPCR2);
551 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
552 }
553
554 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
555 /* Release the transmitter and receiver */
556 w = OMAP_MCBSP_READ(io_base, XCCR);
557 w &= ~(tx ? XDISABLE : 0);
558 OMAP_MCBSP_WRITE(io_base, XCCR, w);
559 w = OMAP_MCBSP_READ(io_base, RCCR);
560 w &= ~(rx ? RDISABLE : 0);
561 OMAP_MCBSP_WRITE(io_base, RCCR, w);
562 }
367 563
368 /* Dump McBSP Regs */ 564 /* Dump McBSP Regs */
369 omap_mcbsp_dump_reg(id); 565 omap_mcbsp_dump_reg(id);
370} 566}
371EXPORT_SYMBOL(omap_mcbsp_start); 567EXPORT_SYMBOL(omap_mcbsp_start);
372 568
373void omap_mcbsp_stop(unsigned int id) 569void omap_mcbsp_stop(unsigned int id, int tx, int rx)
374{ 570{
375 struct omap_mcbsp *mcbsp; 571 struct omap_mcbsp *mcbsp;
376 void __iomem *io_base; 572 void __iomem *io_base;
573 int idle;
377 u16 w; 574 u16 w;
378 575
379 if (!omap_mcbsp_check_valid_id(id)) { 576 if (!omap_mcbsp_check_valid_id(id)) {
@@ -385,16 +582,33 @@ void omap_mcbsp_stop(unsigned int id)
385 io_base = mcbsp->io_base; 582 io_base = mcbsp->io_base;
386 583
387 /* Reset transmitter */ 584 /* Reset transmitter */
585 tx &= 1;
586 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
587 w = OMAP_MCBSP_READ(io_base, XCCR);
588 w |= (tx ? XDISABLE : 0);
589 OMAP_MCBSP_WRITE(io_base, XCCR, w);
590 }
388 w = OMAP_MCBSP_READ(io_base, SPCR2); 591 w = OMAP_MCBSP_READ(io_base, SPCR2);
389 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1)); 592 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~tx);
390 593
391 /* Reset receiver */ 594 /* Reset receiver */
595 rx &= 1;
596 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
597 w = OMAP_MCBSP_READ(io_base, RCCR);
598 w |= (tx ? RDISABLE : 0);
599 OMAP_MCBSP_WRITE(io_base, RCCR, w);
600 }
392 w = OMAP_MCBSP_READ(io_base, SPCR1); 601 w = OMAP_MCBSP_READ(io_base, SPCR1);
393 OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(1)); 602 OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~rx);
394 603
395 /* Reset the sample rate generator */ 604 idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
396 w = OMAP_MCBSP_READ(io_base, SPCR2); 605 OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
397 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6)); 606
607 if (idle) {
608 /* Reset the sample rate generator */
609 w = OMAP_MCBSP_READ(io_base, SPCR2);
610 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
611 }
398} 612}
399EXPORT_SYMBOL(omap_mcbsp_stop); 613EXPORT_SYMBOL(omap_mcbsp_stop);
400 614
@@ -883,6 +1097,149 @@ void omap_mcbsp_set_spi_mode(unsigned int id,
883} 1097}
884EXPORT_SYMBOL(omap_mcbsp_set_spi_mode); 1098EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
885 1099
1100#ifdef CONFIG_ARCH_OMAP34XX
1101#define max_thres(m) (mcbsp->pdata->buffer_size)
1102#define valid_threshold(m, val) ((val) <= max_thres(m))
1103#define THRESHOLD_PROP_BUILDER(prop) \
1104static ssize_t prop##_show(struct device *dev, \
1105 struct device_attribute *attr, char *buf) \
1106{ \
1107 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1108 \
1109 return sprintf(buf, "%u\n", mcbsp->prop); \
1110} \
1111 \
1112static ssize_t prop##_store(struct device *dev, \
1113 struct device_attribute *attr, \
1114 const char *buf, size_t size) \
1115{ \
1116 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1117 unsigned long val; \
1118 int status; \
1119 \
1120 status = strict_strtoul(buf, 0, &val); \
1121 if (status) \
1122 return status; \
1123 \
1124 if (!valid_threshold(mcbsp, val)) \
1125 return -EDOM; \
1126 \
1127 mcbsp->prop = val; \
1128 return size; \
1129} \
1130 \
1131static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1132
1133THRESHOLD_PROP_BUILDER(max_tx_thres);
1134THRESHOLD_PROP_BUILDER(max_rx_thres);
1135
1136static const char *dma_op_modes[] = {
1137 "element", "threshold", "frame",
1138};
1139
1140static ssize_t dma_op_mode_show(struct device *dev,
1141 struct device_attribute *attr, char *buf)
1142{
1143 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1144 int dma_op_mode, i = 0;
1145 ssize_t len = 0;
1146 const char * const *s;
1147
1148 spin_lock_irq(&mcbsp->lock);
1149 dma_op_mode = mcbsp->dma_op_mode;
1150 spin_unlock_irq(&mcbsp->lock);
1151
1152 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1153 if (dma_op_mode == i)
1154 len += sprintf(buf + len, "[%s] ", *s);
1155 else
1156 len += sprintf(buf + len, "%s ", *s);
1157 }
1158 len += sprintf(buf + len, "\n");
1159
1160 return len;
1161}
1162
1163static ssize_t dma_op_mode_store(struct device *dev,
1164 struct device_attribute *attr,
1165 const char *buf, size_t size)
1166{
1167 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1168 const char * const *s;
1169 int i = 0;
1170
1171 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1172 if (sysfs_streq(buf, *s))
1173 break;
1174
1175 if (i == ARRAY_SIZE(dma_op_modes))
1176 return -EINVAL;
1177
1178 spin_lock_irq(&mcbsp->lock);
1179 if (!mcbsp->free) {
1180 size = -EBUSY;
1181 goto unlock;
1182 }
1183 mcbsp->dma_op_mode = i;
1184
1185unlock:
1186 spin_unlock_irq(&mcbsp->lock);
1187
1188 return size;
1189}
1190
1191static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1192
1193static const struct attribute *additional_attrs[] = {
1194 &dev_attr_max_tx_thres.attr,
1195 &dev_attr_max_rx_thres.attr,
1196 &dev_attr_dma_op_mode.attr,
1197 NULL,
1198};
1199
1200static const struct attribute_group additional_attr_group = {
1201 .attrs = (struct attribute **)additional_attrs,
1202};
1203
1204static inline int __devinit omap_additional_add(struct device *dev)
1205{
1206 return sysfs_create_group(&dev->kobj, &additional_attr_group);
1207}
1208
1209static inline void __devexit omap_additional_remove(struct device *dev)
1210{
1211 sysfs_remove_group(&dev->kobj, &additional_attr_group);
1212}
1213
1214static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1215{
1216 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1217 if (cpu_is_omap34xx()) {
1218 mcbsp->max_tx_thres = max_thres(mcbsp);
1219 mcbsp->max_rx_thres = max_thres(mcbsp);
1220 /*
1221 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1222 * for mcbsp2 instances.
1223 */
1224 if (omap_additional_add(mcbsp->dev))
1225 dev_warn(mcbsp->dev,
1226 "Unable to create additional controls\n");
1227 } else {
1228 mcbsp->max_tx_thres = -EINVAL;
1229 mcbsp->max_rx_thres = -EINVAL;
1230 }
1231}
1232
1233static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1234{
1235 if (cpu_is_omap34xx())
1236 omap_additional_remove(mcbsp->dev);
1237}
1238#else
1239static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1240static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1241#endif /* CONFIG_ARCH_OMAP34XX */
1242
886/* 1243/*
887 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510. 1244 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
888 * 730 has only 2 McBSP, and both of them are MPU peripherals. 1245 * 730 has only 2 McBSP, and both of them are MPU peripherals.
@@ -953,6 +1310,10 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
953 mcbsp->dev = &pdev->dev; 1310 mcbsp->dev = &pdev->dev;
954 mcbsp_ptr[id] = mcbsp; 1311 mcbsp_ptr[id] = mcbsp;
955 platform_set_drvdata(pdev, mcbsp); 1312 platform_set_drvdata(pdev, mcbsp);
1313
1314 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1315 omap34xx_device_init(mcbsp);
1316
956 return 0; 1317 return 0;
957 1318
958err_fclk: 1319err_fclk:
@@ -976,6 +1337,8 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
976 mcbsp->pdata->ops->free) 1337 mcbsp->pdata->ops->free)
977 mcbsp->pdata->ops->free(mcbsp->id); 1338 mcbsp->pdata->ops->free(mcbsp->id);
978 1339
1340 omap34xx_device_exit(mcbsp);
1341
979 clk_disable(mcbsp->fclk); 1342 clk_disable(mcbsp->fclk);
980 clk_disable(mcbsp->iclk); 1343 clk_disable(mcbsp->iclk);
981 clk_put(mcbsp->fclk); 1344 clk_put(mcbsp->fclk);
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c
new file mode 100644
index 000000000000..e98f0a2a6c26
--- /dev/null
+++ b/arch/arm/plat-omap/omap-pm-noop.c
@@ -0,0 +1,296 @@
1/*
2 * omap-pm-noop.c - OMAP power management interface - dummy version
3 *
4 * This code implements the OMAP power management interface to
5 * drivers, CPUIdle, CPUFreq, and DSP Bridge. It is strictly for
6 * debug/demonstration use, as it does nothing but printk() whenever a
7 * function is called (when DEBUG is defined, below)
8 *
9 * Copyright (C) 2008-2009 Texas Instruments, Inc.
10 * Copyright (C) 2008-2009 Nokia Corporation
11 * Paul Walmsley
12 *
13 * Interface developed by (in alphabetical order):
14 * Karthik Dasu, Tony Lindgren, Rajendra Nayak, Sakari Poussa, Veeramanikandan
15 * Raju, Anand Sawant, Igor Stoppa, Paul Walmsley, Richard Woodruff
16 */
17
18#undef DEBUG
19
20#include <linux/init.h>
21#include <linux/cpufreq.h>
22#include <linux/device.h>
23
24/* Interface documentation is in mach/omap-pm.h */
25#include <mach/omap-pm.h>
26
27#include <mach/powerdomain.h>
28
29struct omap_opp *dsp_opps;
30struct omap_opp *mpu_opps;
31struct omap_opp *l3_opps;
32
33/*
34 * Device-driver-originated constraints (via board-*.c files)
35 */
36
37void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t)
38{
39 if (!dev || t < -1) {
40 WARN_ON(1);
41 return;
42 };
43
44 if (t == -1)
45 pr_debug("OMAP PM: remove max MPU wakeup latency constraint: "
46 "dev %s\n", dev_name(dev));
47 else
48 pr_debug("OMAP PM: add max MPU wakeup latency constraint: "
49 "dev %s, t = %ld usec\n", dev_name(dev), t);
50
51 /*
52 * For current Linux, this needs to map the MPU to a
53 * powerdomain, then go through the list of current max lat
54 * constraints on the MPU and find the smallest. If
55 * the latency constraint has changed, the code should
56 * recompute the state to enter for the next powerdomain
57 * state.
58 *
59 * TI CDP code can call constraint_set here.
60 */
61}
62
63void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r)
64{
65 if (!dev || (agent_id != OCP_INITIATOR_AGENT &&
66 agent_id != OCP_TARGET_AGENT)) {
67 WARN_ON(1);
68 return;
69 };
70
71 if (r == 0)
72 pr_debug("OMAP PM: remove min bus tput constraint: "
73 "dev %s for agent_id %d\n", dev_name(dev), agent_id);
74 else
75 pr_debug("OMAP PM: add min bus tput constraint: "
76 "dev %s for agent_id %d: rate %ld KiB\n",
77 dev_name(dev), agent_id, r);
78
79 /*
80 * This code should model the interconnect and compute the
81 * required clock frequency, convert that to a VDD2 OPP ID, then
82 * set the VDD2 OPP appropriately.
83 *
84 * TI CDP code can call constraint_set here on the VDD2 OPP.
85 */
86}
87
88void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t)
89{
90 if (!dev || t < -1) {
91 WARN_ON(1);
92 return;
93 };
94
95 if (t == -1)
96 pr_debug("OMAP PM: remove max device latency constraint: "
97 "dev %s\n", dev_name(dev));
98 else
99 pr_debug("OMAP PM: add max device latency constraint: "
100 "dev %s, t = %ld usec\n", dev_name(dev), t);
101
102 /*
103 * For current Linux, this needs to map the device to a
104 * powerdomain, then go through the list of current max lat
105 * constraints on that powerdomain and find the smallest. If
106 * the latency constraint has changed, the code should
107 * recompute the state to enter for the next powerdomain
108 * state. Conceivably, this code should also determine
109 * whether to actually disable the device clocks or not,
110 * depending on how long it takes to re-enable the clocks.
111 *
112 * TI CDP code can call constraint_set here.
113 */
114}
115
116void omap_pm_set_max_sdma_lat(struct device *dev, long t)
117{
118 if (!dev || t < -1) {
119 WARN_ON(1);
120 return;
121 };
122
123 if (t == -1)
124 pr_debug("OMAP PM: remove max DMA latency constraint: "
125 "dev %s\n", dev_name(dev));
126 else
127 pr_debug("OMAP PM: add max DMA latency constraint: "
128 "dev %s, t = %ld usec\n", dev_name(dev), t);
129
130 /*
131 * For current Linux PM QOS params, this code should scan the
132 * list of maximum CPU and DMA latencies and select the
133 * smallest, then set cpu_dma_latency pm_qos_param
134 * accordingly.
135 *
136 * For future Linux PM QOS params, with separate CPU and DMA
137 * latency params, this code should just set the dma_latency param.
138 *
139 * TI CDP code can call constraint_set here.
140 */
141
142}
143
144
145/*
146 * DSP Bridge-specific constraints
147 */
148
149const struct omap_opp *omap_pm_dsp_get_opp_table(void)
150{
151 pr_debug("OMAP PM: DSP request for OPP table\n");
152
153 /*
154 * Return DSP frequency table here: The final item in the
155 * array should have .rate = .opp_id = 0.
156 */
157
158 return NULL;
159}
160
161void omap_pm_dsp_set_min_opp(u8 opp_id)
162{
163 if (opp_id == 0) {
164 WARN_ON(1);
165 return;
166 }
167
168 pr_debug("OMAP PM: DSP requests minimum VDD1 OPP to be %d\n", opp_id);
169
170 /*
171 *
172 * For l-o dev tree, our VDD1 clk is keyed on OPP ID, so we
173 * can just test to see which is higher, the CPU's desired OPP
174 * ID or the DSP's desired OPP ID, and use whichever is
175 * highest.
176 *
177 * In CDP12.14+, the VDD1 OPP custom clock that controls the DSP
178 * rate is keyed on MPU speed, not the OPP ID. So we need to
179 * map the OPP ID to the MPU speed for use with clk_set_rate()
180 * if it is higher than the current OPP clock rate.
181 *
182 */
183}
184
185
186u8 omap_pm_dsp_get_opp(void)
187{
188 pr_debug("OMAP PM: DSP requests current DSP OPP ID\n");
189
190 /*
191 * For l-o dev tree, call clk_get_rate() on VDD1 OPP clock
192 *
193 * CDP12.14+:
194 * Call clk_get_rate() on the OPP custom clock, map that to an
195 * OPP ID using the tables defined in board-*.c/chip-*.c files.
196 */
197
198 return 0;
199}
200
201/*
202 * CPUFreq-originated constraint
203 *
204 * In the future, this should be handled by custom OPP clocktype
205 * functions.
206 */
207
208struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void)
209{
210 pr_debug("OMAP PM: CPUFreq request for frequency table\n");
211
212 /*
213 * Return CPUFreq frequency table here: loop over
214 * all VDD1 clkrates, pull out the mpu_ck frequencies, build
215 * table
216 */
217
218 return NULL;
219}
220
221void omap_pm_cpu_set_freq(unsigned long f)
222{
223 if (f == 0) {
224 WARN_ON(1);
225 return;
226 }
227
228 pr_debug("OMAP PM: CPUFreq requests CPU frequency to be set to %lu\n",
229 f);
230
231 /*
232 * For l-o dev tree, determine whether MPU freq or DSP OPP id
233 * freq is higher. Find the OPP ID corresponding to the
234 * higher frequency. Call clk_round_rate() and clk_set_rate()
235 * on the OPP custom clock.
236 *
237 * CDP should just be able to set the VDD1 OPP clock rate here.
238 */
239}
240
241unsigned long omap_pm_cpu_get_freq(void)
242{
243 pr_debug("OMAP PM: CPUFreq requests current CPU frequency\n");
244
245 /*
246 * Call clk_get_rate() on the mpu_ck.
247 */
248
249 return 0;
250}
251
252/*
253 * Device context loss tracking
254 */
255
256int omap_pm_get_dev_context_loss_count(struct device *dev)
257{
258 if (!dev) {
259 WARN_ON(1);
260 return -EINVAL;
261 };
262
263 pr_debug("OMAP PM: returning context loss count for dev %s\n",
264 dev_name(dev));
265
266 /*
267 * Map the device to the powerdomain. Return the powerdomain
268 * off counter.
269 */
270
271 return 0;
272}
273
274
275/* Should be called before clk framework init */
276int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
277 struct omap_opp *dsp_opp_table,
278 struct omap_opp *l3_opp_table)
279{
280 mpu_opps = mpu_opp_table;
281 dsp_opps = dsp_opp_table;
282 l3_opps = l3_opp_table;
283 return 0;
284}
285
286/* Must be called after clock framework is initialized */
287int __init omap_pm_if_init(void)
288{
289 return 0;
290}
291
292void omap_pm_if_exit(void)
293{
294 /* Deallocate CPUFreq frequency table here */
295}
296
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
new file mode 100644
index 000000000000..2c409fc6dd21
--- /dev/null
+++ b/arch/arm/plat-omap/omap_device.c
@@ -0,0 +1,687 @@
1/*
2 * omap_device implementation
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Paul Walmsley
6 *
7 * Developed in collaboration with (alphabetical order): Benoit
8 * Cousson, Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram
9 * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard
10 * Woodruff
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * This code provides a consistent interface for OMAP device drivers
17 * to control power management and interconnect properties of their
18 * devices.
19 *
20 * In the medium- to long-term, this code should either be
21 * a) implemented via arch-specific pointers in platform_data
22 * or
23 * b) implemented as a proper omap_bus/omap_device in Linux, no more
24 * platform_data func pointers
25 *
26 *
27 * Guidelines for usage by driver authors:
28 *
29 * 1. These functions are intended to be used by device drivers via
30 * function pointers in struct platform_data. As an example,
31 * omap_device_enable() should be passed to the driver as
32 *
33 * struct foo_driver_platform_data {
34 * ...
35 * int (*device_enable)(struct platform_device *pdev);
36 * ...
37 * }
38 *
39 * Note that the generic "device_enable" name is used, rather than
40 * "omap_device_enable". This is so other architectures can pass in their
41 * own enable/disable functions here.
42 *
43 * This should be populated during device setup:
44 *
45 * ...
46 * pdata->device_enable = omap_device_enable;
47 * ...
48 *
49 * 2. Drivers should first check to ensure the function pointer is not null
50 * before calling it, as in:
51 *
52 * if (pdata->device_enable)
53 * pdata->device_enable(pdev);
54 *
55 * This allows other architectures that don't use similar device_enable()/
56 * device_shutdown() functions to execute normally.
57 *
58 * ...
59 *
60 * Suggested usage by device drivers:
61 *
62 * During device initialization:
63 * device_enable()
64 *
65 * During device idle:
66 * (save remaining device context if necessary)
67 * device_idle();
68 *
69 * During device resume:
70 * device_enable();
71 * (restore context if necessary)
72 *
73 * During device shutdown:
74 * device_shutdown()
75 * (device must be reinitialized at this point to use it again)
76 *
77 */
78#undef DEBUG
79
80#include <linux/kernel.h>
81#include <linux/platform_device.h>
82#include <linux/err.h>
83#include <linux/io.h>
84
85#include <mach/omap_device.h>
86#include <mach/omap_hwmod.h>
87
88/* These parameters are passed to _omap_device_{de,}activate() */
89#define USE_WAKEUP_LAT 0
90#define IGNORE_WAKEUP_LAT 1
91
92/* XXX this should be moved into a separate file */
93#if defined(CONFIG_ARCH_OMAP2420)
94# define OMAP_32KSYNCT_BASE 0x48004000
95#elif defined(CONFIG_ARCH_OMAP2430)
96# define OMAP_32KSYNCT_BASE 0x49020000
97#elif defined(CONFIG_ARCH_OMAP3430)
98# define OMAP_32KSYNCT_BASE 0x48320000
99#else
100# error Unknown OMAP device
101#endif
102
103/* Private functions */
104
105/**
106 * _read_32ksynct - read the OMAP 32K sync timer
107 *
108 * Returns the current value of the 32KiHz synchronization counter.
109 * XXX this should be generalized to simply read the system clocksource.
110 * XXX this should be moved to a separate synctimer32k.c file
111 */
112static u32 _read_32ksynct(void)
113{
114 if (!cpu_class_is_omap2())
115 BUG();
116
117 return __raw_readl(OMAP2_IO_ADDRESS(OMAP_32KSYNCT_BASE + 0x010));
118}
119
120/**
121 * _omap_device_activate - increase device readiness
122 * @od: struct omap_device *
123 * @ignore_lat: increase to latency target (0) or full readiness (1)?
124 *
125 * Increase readiness of omap_device @od (thus decreasing device
126 * wakeup latency, but consuming more power). If @ignore_lat is
127 * IGNORE_WAKEUP_LAT, make the omap_device fully active. Otherwise,
128 * if @ignore_lat is USE_WAKEUP_LAT, and the device's maximum wakeup
129 * latency is greater than the requested maximum wakeup latency, step
130 * backwards in the omap_device_pm_latency table to ensure the
131 * device's maximum wakeup latency is less than or equal to the
132 * requested maximum wakeup latency. Returns 0.
133 */
134static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
135{
136 u32 a, b;
137
138 pr_debug("omap_device: %s: activating\n", od->pdev.name);
139
140 while (od->pm_lat_level > 0) {
141 struct omap_device_pm_latency *odpl;
142 int act_lat = 0;
143
144 od->pm_lat_level--;
145
146 odpl = od->pm_lats + od->pm_lat_level;
147
148 if (!ignore_lat &&
149 (od->dev_wakeup_lat <= od->_dev_wakeup_lat_limit))
150 break;
151
152 a = _read_32ksynct();
153
154 /* XXX check return code */
155 odpl->activate_func(od);
156
157 b = _read_32ksynct();
158
159 act_lat = (b - a) >> 15; /* 32KiHz cycles to microseconds */
160
161 pr_debug("omap_device: %s: pm_lat %d: activate: elapsed time "
162 "%d usec\n", od->pdev.name, od->pm_lat_level, act_lat);
163
164 WARN(act_lat > odpl->activate_lat, "omap_device: %s.%d: "
165 "activate step %d took longer than expected (%d > %d)\n",
166 od->pdev.name, od->pdev.id, od->pm_lat_level,
167 act_lat, odpl->activate_lat);
168
169 od->dev_wakeup_lat -= odpl->activate_lat;
170 }
171
172 return 0;
173}
174
175/**
176 * _omap_device_deactivate - decrease device readiness
177 * @od: struct omap_device *
178 * @ignore_lat: decrease to latency target (0) or full inactivity (1)?
179 *
180 * Decrease readiness of omap_device @od (thus increasing device
181 * wakeup latency, but conserving power). If @ignore_lat is
182 * IGNORE_WAKEUP_LAT, make the omap_device fully inactive. Otherwise,
183 * if @ignore_lat is USE_WAKEUP_LAT, and the device's maximum wakeup
184 * latency is less than the requested maximum wakeup latency, step
185 * forwards in the omap_device_pm_latency table to ensure the device's
186 * maximum wakeup latency is less than or equal to the requested
187 * maximum wakeup latency. Returns 0.
188 */
189static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
190{
191 u32 a, b;
192
193 pr_debug("omap_device: %s: deactivating\n", od->pdev.name);
194
195 while (od->pm_lat_level < od->pm_lats_cnt) {
196 struct omap_device_pm_latency *odpl;
197 int deact_lat = 0;
198
199 odpl = od->pm_lats + od->pm_lat_level;
200
201 if (!ignore_lat &&
202 ((od->dev_wakeup_lat + odpl->activate_lat) >
203 od->_dev_wakeup_lat_limit))
204 break;
205
206 a = _read_32ksynct();
207
208 /* XXX check return code */
209 odpl->deactivate_func(od);
210
211 b = _read_32ksynct();
212
213 deact_lat = (b - a) >> 15; /* 32KiHz cycles to microseconds */
214
215 pr_debug("omap_device: %s: pm_lat %d: deactivate: elapsed time "
216 "%d usec\n", od->pdev.name, od->pm_lat_level,
217 deact_lat);
218
219 WARN(deact_lat > odpl->deactivate_lat, "omap_device: %s.%d: "
220 "deactivate step %d took longer than expected (%d > %d)\n",
221 od->pdev.name, od->pdev.id, od->pm_lat_level,
222 deact_lat, odpl->deactivate_lat);
223
224 od->dev_wakeup_lat += odpl->activate_lat;
225
226 od->pm_lat_level++;
227 }
228
229 return 0;
230}
231
232static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
233{
234 return container_of(pdev, struct omap_device, pdev);
235}
236
237
238/* Public functions for use by core code */
239
240/**
241 * omap_device_count_resources - count number of struct resource entries needed
242 * @od: struct omap_device *
243 *
244 * Count the number of struct resource entries needed for this
245 * omap_device @od. Used by omap_device_build_ss() to determine how
246 * much memory to allocate before calling
247 * omap_device_fill_resources(). Returns the count.
248 */
249int omap_device_count_resources(struct omap_device *od)
250{
251 struct omap_hwmod *oh;
252 int c = 0;
253 int i;
254
255 for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
256 c += omap_hwmod_count_resources(oh);
257
258 pr_debug("omap_device: %s: counted %d total resources across %d "
259 "hwmods\n", od->pdev.name, c, od->hwmods_cnt);
260
261 return c;
262}
263
264/**
265 * omap_device_fill_resources - fill in array of struct resource
266 * @od: struct omap_device *
267 * @res: pointer to an array of struct resource to be filled in
268 *
269 * Populate one or more empty struct resource pointed to by @res with
270 * the resource data for this omap_device @od. Used by
271 * omap_device_build_ss() after calling omap_device_count_resources().
272 * Ideally this function would not be needed at all. If omap_device
273 * replaces platform_device, then we can specify our own
274 * get_resource()/ get_irq()/etc functions that use the underlying
275 * omap_hwmod information. Or if platform_device is extended to use
276 * subarchitecture-specific function pointers, the various
277 * platform_device functions can simply call omap_device internal
278 * functions to get device resources. Hacking around the existing
279 * platform_device code wastes memory. Returns 0.
280 */
281int omap_device_fill_resources(struct omap_device *od, struct resource *res)
282{
283 struct omap_hwmod *oh;
284 int c = 0;
285 int i, r;
286
287 for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) {
288 r = omap_hwmod_fill_resources(oh, res);
289 res += r;
290 c += r;
291 }
292
293 return 0;
294}
295
296/**
297 * omap_device_build - build and register an omap_device with one omap_hwmod
298 * @pdev_name: name of the platform_device driver to use
299 * @pdev_id: this platform_device's connection ID
300 * @oh: ptr to the single omap_hwmod that backs this omap_device
301 * @pdata: platform_data ptr to associate with the platform_device
302 * @pdata_len: amount of memory pointed to by @pdata
303 * @pm_lats: pointer to a omap_device_pm_latency array for this device
304 * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
305 *
306 * Convenience function for building and registering a single
307 * omap_device record, which in turn builds and registers a
308 * platform_device record. See omap_device_build_ss() for more
309 * information. Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise,
310 * passes along the return value of omap_device_build_ss().
311 */
312struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
313 struct omap_hwmod *oh, void *pdata,
314 int pdata_len,
315 struct omap_device_pm_latency *pm_lats,
316 int pm_lats_cnt)
317{
318 struct omap_hwmod *ohs[] = { oh };
319
320 if (!oh)
321 return ERR_PTR(-EINVAL);
322
323 return omap_device_build_ss(pdev_name, pdev_id, ohs, 1, pdata,
324 pdata_len, pm_lats, pm_lats_cnt);
325}
326
327/**
328 * omap_device_build_ss - build and register an omap_device with multiple hwmods
329 * @pdev_name: name of the platform_device driver to use
330 * @pdev_id: this platform_device's connection ID
331 * @oh: ptr to the single omap_hwmod that backs this omap_device
332 * @pdata: platform_data ptr to associate with the platform_device
333 * @pdata_len: amount of memory pointed to by @pdata
334 * @pm_lats: pointer to a omap_device_pm_latency array for this device
335 * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
336 *
337 * Convenience function for building and registering an omap_device
338 * subsystem record. Subsystem records consist of multiple
339 * omap_hwmods. This function in turn builds and registers a
340 * platform_device record. Returns an ERR_PTR() on error, or passes
341 * along the return value of omap_device_register().
342 */
343struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
344 struct omap_hwmod **ohs, int oh_cnt,
345 void *pdata, int pdata_len,
346 struct omap_device_pm_latency *pm_lats,
347 int pm_lats_cnt)
348{
349 int ret = -ENOMEM;
350 struct omap_device *od;
351 char *pdev_name2;
352 struct resource *res = NULL;
353 int res_count;
354 struct omap_hwmod **hwmods;
355
356 if (!ohs || oh_cnt == 0 || !pdev_name)
357 return ERR_PTR(-EINVAL);
358
359 if (!pdata && pdata_len > 0)
360 return ERR_PTR(-EINVAL);
361
362 pr_debug("omap_device: %s: building with %d hwmods\n", pdev_name,
363 oh_cnt);
364
365 od = kzalloc(sizeof(struct omap_device), GFP_KERNEL);
366 if (!od)
367 return ERR_PTR(-ENOMEM);
368
369 od->hwmods_cnt = oh_cnt;
370
371 hwmods = kzalloc(sizeof(struct omap_hwmod *) * oh_cnt,
372 GFP_KERNEL);
373 if (!hwmods)
374 goto odbs_exit1;
375
376 memcpy(hwmods, ohs, sizeof(struct omap_hwmod *) * oh_cnt);
377 od->hwmods = hwmods;
378
379 pdev_name2 = kzalloc(strlen(pdev_name) + 1, GFP_KERNEL);
380 if (!pdev_name2)
381 goto odbs_exit2;
382 strcpy(pdev_name2, pdev_name);
383
384 od->pdev.name = pdev_name2;
385 od->pdev.id = pdev_id;
386
387 res_count = omap_device_count_resources(od);
388 if (res_count > 0) {
389 res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
390 if (!res)
391 goto odbs_exit3;
392 }
393 omap_device_fill_resources(od, res);
394
395 od->pdev.num_resources = res_count;
396 od->pdev.resource = res;
397
398 platform_device_add_data(&od->pdev, pdata, pdata_len);
399
400 od->pm_lats = pm_lats;
401 od->pm_lats_cnt = pm_lats_cnt;
402
403 ret = omap_device_register(od);
404 if (ret)
405 goto odbs_exit4;
406
407 return od;
408
409odbs_exit4:
410 kfree(res);
411odbs_exit3:
412 kfree(pdev_name2);
413odbs_exit2:
414 kfree(hwmods);
415odbs_exit1:
416 kfree(od);
417
418 pr_err("omap_device: %s: build failed (%d)\n", pdev_name, ret);
419
420 return ERR_PTR(ret);
421}
422
423/**
424 * omap_device_register - register an omap_device with one omap_hwmod
425 * @od: struct omap_device * to register
426 *
427 * Register the omap_device structure. This currently just calls
428 * platform_device_register() on the underlying platform_device.
429 * Returns the return value of platform_device_register().
430 */
431int omap_device_register(struct omap_device *od)
432{
433 pr_debug("omap_device: %s: registering\n", od->pdev.name);
434
435 return platform_device_register(&od->pdev);
436}
437
438
439/* Public functions for use by device drivers through struct platform_data */
440
441/**
442 * omap_device_enable - fully activate an omap_device
443 * @od: struct omap_device * to activate
444 *
445 * Do whatever is necessary for the hwmods underlying omap_device @od
446 * to be accessible and ready to operate. This generally involves
447 * enabling clocks, setting SYSCONFIG registers; and in the future may
448 * involve remuxing pins. Device drivers should call this function
449 * (through platform_data function pointers) where they would normally
450 * enable clocks, etc. Returns -EINVAL if called when the omap_device
451 * is already enabled, or passes along the return value of
452 * _omap_device_activate().
453 */
454int omap_device_enable(struct platform_device *pdev)
455{
456 int ret;
457 struct omap_device *od;
458
459 od = _find_by_pdev(pdev);
460
461 if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
462 WARN(1, "omap_device: %s.%d: omap_device_enable() called from "
463 "invalid state\n", od->pdev.name, od->pdev.id);
464 return -EINVAL;
465 }
466
467 /* Enable everything if we're enabling this device from scratch */
468 if (od->_state == OMAP_DEVICE_STATE_UNKNOWN)
469 od->pm_lat_level = od->pm_lats_cnt;
470
471 ret = _omap_device_activate(od, IGNORE_WAKEUP_LAT);
472
473 od->dev_wakeup_lat = 0;
474 od->_dev_wakeup_lat_limit = INT_MAX;
475 od->_state = OMAP_DEVICE_STATE_ENABLED;
476
477 return ret;
478}
479
480/**
481 * omap_device_idle - idle an omap_device
482 * @od: struct omap_device * to idle
483 *
484 * Idle omap_device @od by calling as many .deactivate_func() entries
485 * in the omap_device's pm_lats table as is possible without exceeding
486 * the device's maximum wakeup latency limit, pm_lat_limit. Device
487 * drivers should call this function (through platform_data function
488 * pointers) where they would normally disable clocks after operations
489 * complete, etc.. Returns -EINVAL if the omap_device is not
490 * currently enabled, or passes along the return value of
491 * _omap_device_deactivate().
492 */
493int omap_device_idle(struct platform_device *pdev)
494{
495 int ret;
496 struct omap_device *od;
497
498 od = _find_by_pdev(pdev);
499
500 if (od->_state != OMAP_DEVICE_STATE_ENABLED) {
501 WARN(1, "omap_device: %s.%d: omap_device_idle() called from "
502 "invalid state\n", od->pdev.name, od->pdev.id);
503 return -EINVAL;
504 }
505
506 ret = _omap_device_deactivate(od, USE_WAKEUP_LAT);
507
508 od->_state = OMAP_DEVICE_STATE_IDLE;
509
510 return ret;
511}
512
513/**
514 * omap_device_shutdown - shut down an omap_device
515 * @od: struct omap_device * to shut down
516 *
517 * Shut down omap_device @od by calling all .deactivate_func() entries
518 * in the omap_device's pm_lats table and then shutting down all of
519 * the underlying omap_hwmods. Used when a device is being "removed"
520 * or a device driver is being unloaded. Returns -EINVAL if the
521 * omap_device is not currently enabled or idle, or passes along the
522 * return value of _omap_device_deactivate().
523 */
524int omap_device_shutdown(struct platform_device *pdev)
525{
526 int ret, i;
527 struct omap_device *od;
528 struct omap_hwmod *oh;
529
530 od = _find_by_pdev(pdev);
531
532 if (od->_state != OMAP_DEVICE_STATE_ENABLED &&
533 od->_state != OMAP_DEVICE_STATE_IDLE) {
534 WARN(1, "omap_device: %s.%d: omap_device_shutdown() called "
535 "from invalid state\n", od->pdev.name, od->pdev.id);
536 return -EINVAL;
537 }
538
539 ret = _omap_device_deactivate(od, IGNORE_WAKEUP_LAT);
540
541 for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
542 omap_hwmod_shutdown(oh);
543
544 od->_state = OMAP_DEVICE_STATE_SHUTDOWN;
545
546 return ret;
547}
548
549/**
550 * omap_device_align_pm_lat - activate/deactivate device to match wakeup lat lim
551 * @od: struct omap_device *
552 *
553 * When a device's maximum wakeup latency limit changes, call some of
554 * the .activate_func or .deactivate_func function pointers in the
555 * omap_device's pm_lats array to ensure that the device's maximum
556 * wakeup latency is less than or equal to the new latency limit.
557 * Intended to be called by OMAP PM code whenever a device's maximum
558 * wakeup latency limit changes (e.g., via
559 * omap_pm_set_dev_wakeup_lat()). Returns 0 if nothing needs to be
560 * done (e.g., if the omap_device is not currently idle, or if the
561 * wakeup latency is already current with the new limit) or passes
562 * along the return value of _omap_device_deactivate() or
563 * _omap_device_activate().
564 */
565int omap_device_align_pm_lat(struct platform_device *pdev,
566 u32 new_wakeup_lat_limit)
567{
568 int ret = -EINVAL;
569 struct omap_device *od;
570
571 od = _find_by_pdev(pdev);
572
573 if (new_wakeup_lat_limit == od->dev_wakeup_lat)
574 return 0;
575
576 od->_dev_wakeup_lat_limit = new_wakeup_lat_limit;
577
578 if (od->_state != OMAP_DEVICE_STATE_IDLE)
579 return 0;
580 else if (new_wakeup_lat_limit > od->dev_wakeup_lat)
581 ret = _omap_device_deactivate(od, USE_WAKEUP_LAT);
582 else if (new_wakeup_lat_limit < od->dev_wakeup_lat)
583 ret = _omap_device_activate(od, USE_WAKEUP_LAT);
584
585 return ret;
586}
587
588/**
589 * omap_device_get_pwrdm - return the powerdomain * associated with @od
590 * @od: struct omap_device *
591 *
592 * Return the powerdomain associated with the first underlying
593 * omap_hwmod for this omap_device. Intended for use by core OMAP PM
594 * code. Returns NULL on error or a struct powerdomain * upon
595 * success.
596 */
597struct powerdomain *omap_device_get_pwrdm(struct omap_device *od)
598{
599 /*
600 * XXX Assumes that all omap_hwmod powerdomains are identical.
601 * This may not necessarily be true. There should be a sanity
602 * check in here to WARN() if any difference appears.
603 */
604 if (!od->hwmods_cnt)
605 return NULL;
606
607 return omap_hwmod_get_pwrdm(od->hwmods[0]);
608}
609
610/*
611 * Public functions intended for use in omap_device_pm_latency
612 * .activate_func and .deactivate_func function pointers
613 */
614
615/**
616 * omap_device_enable_hwmods - call omap_hwmod_enable() on all hwmods
617 * @od: struct omap_device *od
618 *
619 * Enable all underlying hwmods. Returns 0.
620 */
621int omap_device_enable_hwmods(struct omap_device *od)
622{
623 struct omap_hwmod *oh;
624 int i;
625
626 for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
627 omap_hwmod_enable(oh);
628
629 /* XXX pass along return value here? */
630 return 0;
631}
632
633/**
634 * omap_device_idle_hwmods - call omap_hwmod_idle() on all hwmods
635 * @od: struct omap_device *od
636 *
637 * Idle all underlying hwmods. Returns 0.
638 */
639int omap_device_idle_hwmods(struct omap_device *od)
640{
641 struct omap_hwmod *oh;
642 int i;
643
644 for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
645 omap_hwmod_idle(oh);
646
647 /* XXX pass along return value here? */
648 return 0;
649}
650
651/**
652 * omap_device_disable_clocks - disable all main and interface clocks
653 * @od: struct omap_device *od
654 *
655 * Disable the main functional clock and interface clock for all of the
656 * omap_hwmods associated with the omap_device. Returns 0.
657 */
658int omap_device_disable_clocks(struct omap_device *od)
659{
660 struct omap_hwmod *oh;
661 int i;
662
663 for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
664 omap_hwmod_disable_clocks(oh);
665
666 /* XXX pass along return value here? */
667 return 0;
668}
669
670/**
671 * omap_device_enable_clocks - enable all main and interface clocks
672 * @od: struct omap_device *od
673 *
674 * Enable the main functional clock and interface clock for all of the
675 * omap_hwmods associated with the omap_device. Returns 0.
676 */
677int omap_device_enable_clocks(struct omap_device *od)
678{
679 struct omap_hwmod *oh;
680 int i;
681
682 for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
683 omap_hwmod_enable_clocks(oh);
684
685 /* XXX pass along return value here? */
686 return 0;
687}
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 5eae7876979c..925f64711c37 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -56,16 +56,16 @@
56#define SRAM_BOOTLOADER_SZ 0x80 56#define SRAM_BOOTLOADER_SZ 0x80
57#endif 57#endif
58 58
59#define OMAP24XX_VA_REQINFOPERM0 IO_ADDRESS(0x68005048) 59#define OMAP24XX_VA_REQINFOPERM0 OMAP2_IO_ADDRESS(0x68005048)
60#define OMAP24XX_VA_READPERM0 IO_ADDRESS(0x68005050) 60#define OMAP24XX_VA_READPERM0 OMAP2_IO_ADDRESS(0x68005050)
61#define OMAP24XX_VA_WRITEPERM0 IO_ADDRESS(0x68005058) 61#define OMAP24XX_VA_WRITEPERM0 OMAP2_IO_ADDRESS(0x68005058)
62 62
63#define OMAP34XX_VA_REQINFOPERM0 IO_ADDRESS(0x68012848) 63#define OMAP34XX_VA_REQINFOPERM0 OMAP2_IO_ADDRESS(0x68012848)
64#define OMAP34XX_VA_READPERM0 IO_ADDRESS(0x68012850) 64#define OMAP34XX_VA_READPERM0 OMAP2_IO_ADDRESS(0x68012850)
65#define OMAP34XX_VA_WRITEPERM0 IO_ADDRESS(0x68012858) 65#define OMAP34XX_VA_WRITEPERM0 OMAP2_IO_ADDRESS(0x68012858)
66#define OMAP34XX_VA_ADDR_MATCH2 IO_ADDRESS(0x68012880) 66#define OMAP34XX_VA_ADDR_MATCH2 OMAP2_IO_ADDRESS(0x68012880)
67#define OMAP34XX_VA_SMS_RG_ATT0 IO_ADDRESS(0x6C000048) 67#define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_IO_ADDRESS(0x6C000048)
68#define OMAP34XX_VA_CONTROL_STAT IO_ADDRESS(0x480022F0) 68#define OMAP34XX_VA_CONTROL_STAT OMAP2_IO_ADDRESS(0x480022F0)
69 69
70#define GP_DEVICE 0x300 70#define GP_DEVICE 0x300
71 71
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-20 17:46:15 -0500