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authorIngo Molnar <mingo@elte.hu>2009-09-15 06:18:15 -0400
committerIngo Molnar <mingo@elte.hu>2009-09-15 06:18:15 -0400
commitdca2d6ac09d9ef59ff46820d4f0c94b08a671202 (patch)
treefdec753b842dad09e3a4151954fab3eb5c43500d /arch/arm/plat-omap
parentd6a65dffb30d8636b1e5d4c201564ef401a246cf (diff)
parent18240904960a39e582ced8ba8ececb10b8c22dd3 (diff)
Merge branch 'linus' into tracing/hw-breakpoints
Conflicts: arch/x86/kernel/process_64.c Semantic conflict fixed in: arch/x86/kvm/x86.c Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r--arch/arm/plat-omap/debug-leds.c11
-rw-r--r--arch/arm/plat-omap/dma.c10
-rw-r--r--arch/arm/plat-omap/gpio.c263
-rw-r--r--arch/arm/plat-omap/include/mach/dma.h88
-rw-r--r--arch/arm/plat-omap/include/mach/mcbsp.h59
-rw-r--r--arch/arm/plat-omap/mcbsp.c403
6 files changed, 752 insertions, 82 deletions
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index be4eefda4767..9395898dd49a 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -281,24 +281,27 @@ static int /* __init */ fpga_probe(struct platform_device *pdev)
281 return 0; 281 return 0;
282} 282}
283 283
284static int fpga_suspend_late(struct platform_device *pdev, pm_message_t mesg) 284static int fpga_suspend_noirq(struct device *dev)
285{ 285{
286 __raw_writew(~0, &fpga->leds); 286 __raw_writew(~0, &fpga->leds);
287 return 0; 287 return 0;
288} 288}
289 289
290static int fpga_resume_early(struct platform_device *pdev) 290static int fpga_resume_noirq(struct device *dev)
291{ 291{
292 __raw_writew(~hw_led_state, &fpga->leds); 292 __raw_writew(~hw_led_state, &fpga->leds);
293 return 0; 293 return 0;
294} 294}
295 295
296static struct dev_pm_ops fpga_dev_pm_ops = {
297 .suspend_noirq = fpga_suspend_noirq,
298 .resume_noirq = fpga_resume_noirq,
299};
296 300
297static struct platform_driver led_driver = { 301static struct platform_driver led_driver = {
298 .driver.name = "omap_dbg_led", 302 .driver.name = "omap_dbg_led",
303 .driver.pm = &fpga_dev_pm_ops,
299 .probe = fpga_probe, 304 .probe = fpga_probe,
300 .suspend_late = fpga_suspend_late,
301 .resume_early = fpga_resume_early,
302}; 305};
303 306
304static int __init fpga_init(void) 307static int __init fpga_init(void)
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index e3ac94f09006..9b00f4cbc903 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1127,6 +1127,11 @@ int omap_dma_running(void)
1127void omap_dma_link_lch(int lch_head, int lch_queue) 1127void omap_dma_link_lch(int lch_head, int lch_queue)
1128{ 1128{
1129 if (omap_dma_in_1510_mode()) { 1129 if (omap_dma_in_1510_mode()) {
1130 if (lch_head == lch_queue) {
1131 dma_write(dma_read(CCR(lch_head)) | (3 << 8),
1132 CCR(lch_head));
1133 return;
1134 }
1130 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); 1135 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1131 BUG(); 1136 BUG();
1132 return; 1137 return;
@@ -1149,6 +1154,11 @@ EXPORT_SYMBOL(omap_dma_link_lch);
1149void omap_dma_unlink_lch(int lch_head, int lch_queue) 1154void omap_dma_unlink_lch(int lch_head, int lch_queue)
1150{ 1155{
1151 if (omap_dma_in_1510_mode()) { 1156 if (omap_dma_in_1510_mode()) {
1157 if (lch_head == lch_queue) {
1158 dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
1159 CCR(lch_head));
1160 return;
1161 }
1152 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); 1162 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1153 BUG(); 1163 BUG();
1154 return; 1164 return;
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 9298bc0ab171..176c86e5531d 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -138,6 +138,32 @@
138#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 138#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
139#define OMAP24XX_GPIO_SETDATAOUT 0x0094 139#define OMAP24XX_GPIO_SETDATAOUT 0x0094
140 140
141#define OMAP4_GPIO_REVISION 0x0000
142#define OMAP4_GPIO_SYSCONFIG 0x0010
143#define OMAP4_GPIO_EOI 0x0020
144#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
145#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
146#define OMAP4_GPIO_IRQSTATUS0 0x002c
147#define OMAP4_GPIO_IRQSTATUS1 0x0030
148#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
149#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
150#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
151#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
152#define OMAP4_GPIO_IRQWAKEN0 0x0044
153#define OMAP4_GPIO_IRQWAKEN1 0x0048
154#define OMAP4_GPIO_SYSSTATUS 0x0104
155#define OMAP4_GPIO_CTRL 0x0130
156#define OMAP4_GPIO_OE 0x0134
157#define OMAP4_GPIO_DATAIN 0x0138
158#define OMAP4_GPIO_DATAOUT 0x013c
159#define OMAP4_GPIO_LEVELDETECT0 0x0140
160#define OMAP4_GPIO_LEVELDETECT1 0x0144
161#define OMAP4_GPIO_RISINGDETECT 0x0148
162#define OMAP4_GPIO_FALLINGDETECT 0x014c
163#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
164#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
165#define OMAP4_GPIO_CLEARDATAOUT 0x0190
166#define OMAP4_GPIO_SETDATAOUT 0x0194
141/* 167/*
142 * omap34xx specific GPIO registers 168 * omap34xx specific GPIO registers
143 */ 169 */
@@ -386,12 +412,16 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
386 reg += OMAP850_GPIO_DIR_CONTROL; 412 reg += OMAP850_GPIO_DIR_CONTROL;
387 break; 413 break;
388#endif 414#endif
389#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 415#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
390 defined(CONFIG_ARCH_OMAP4)
391 case METHOD_GPIO_24XX: 416 case METHOD_GPIO_24XX:
392 reg += OMAP24XX_GPIO_OE; 417 reg += OMAP24XX_GPIO_OE;
393 break; 418 break;
394#endif 419#endif
420#if defined(CONFIG_ARCH_OMAP4)
421 case METHOD_GPIO_24XX:
422 reg += OMAP4_GPIO_OE;
423 break;
424#endif
395 default: 425 default:
396 WARN_ON(1); 426 WARN_ON(1);
397 return; 427 return;
@@ -459,8 +489,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
459 l &= ~(1 << gpio); 489 l &= ~(1 << gpio);
460 break; 490 break;
461#endif 491#endif
462#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 492#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
463 defined(CONFIG_ARCH_OMAP4)
464 case METHOD_GPIO_24XX: 493 case METHOD_GPIO_24XX:
465 if (enable) 494 if (enable)
466 reg += OMAP24XX_GPIO_SETDATAOUT; 495 reg += OMAP24XX_GPIO_SETDATAOUT;
@@ -469,6 +498,15 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
469 l = 1 << gpio; 498 l = 1 << gpio;
470 break; 499 break;
471#endif 500#endif
501#ifdef CONFIG_ARCH_OMAP4
502 case METHOD_GPIO_24XX:
503 if (enable)
504 reg += OMAP4_GPIO_SETDATAOUT;
505 else
506 reg += OMAP4_GPIO_CLEARDATAOUT;
507 l = 1 << gpio;
508 break;
509#endif
472 default: 510 default:
473 WARN_ON(1); 511 WARN_ON(1);
474 return; 512 return;
@@ -509,12 +547,16 @@ static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
509 reg += OMAP850_GPIO_DATA_INPUT; 547 reg += OMAP850_GPIO_DATA_INPUT;
510 break; 548 break;
511#endif 549#endif
512#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 550#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
513 defined(CONFIG_ARCH_OMAP4)
514 case METHOD_GPIO_24XX: 551 case METHOD_GPIO_24XX:
515 reg += OMAP24XX_GPIO_DATAIN; 552 reg += OMAP24XX_GPIO_DATAIN;
516 break; 553 break;
517#endif 554#endif
555#ifdef CONFIG_ARCH_OMAP4
556 case METHOD_GPIO_24XX:
557 reg += OMAP4_GPIO_DATAIN;
558 break;
559#endif
518 default: 560 default:
519 return -EINVAL; 561 return -EINVAL;
520 } 562 }
@@ -589,7 +631,11 @@ void omap_set_gpio_debounce(int gpio, int enable)
589 631
590 bank = get_gpio_bank(gpio); 632 bank = get_gpio_bank(gpio);
591 reg = bank->base; 633 reg = bank->base;
634#ifdef CONFIG_ARCH_OMAP4
635 reg += OMAP4_GPIO_DEBOUNCENABLE;
636#else
592 reg += OMAP24XX_GPIO_DEBOUNCE_EN; 637 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
638#endif
593 639
594 spin_lock_irqsave(&bank->lock, flags); 640 spin_lock_irqsave(&bank->lock, flags);
595 val = __raw_readl(reg); 641 val = __raw_readl(reg);
@@ -626,7 +672,11 @@ void omap_set_gpio_debounce_time(int gpio, int enc_time)
626 reg = bank->base; 672 reg = bank->base;
627 673
628 enc_time &= 0xff; 674 enc_time &= 0xff;
675#ifdef CONFIG_ARCH_OMAP4
676 reg += OMAP4_GPIO_DEBOUNCINGTIME;
677#else
629 reg += OMAP24XX_GPIO_DEBOUNCE_VAL; 678 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
679#endif
630 __raw_writel(enc_time, reg); 680 __raw_writel(enc_time, reg);
631} 681}
632EXPORT_SYMBOL(omap_set_gpio_debounce_time); 682EXPORT_SYMBOL(omap_set_gpio_debounce_time);
@@ -638,23 +688,46 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
638{ 688{
639 void __iomem *base = bank->base; 689 void __iomem *base = bank->base;
640 u32 gpio_bit = 1 << gpio; 690 u32 gpio_bit = 1 << gpio;
691 u32 val;
641 692
642 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, 693 if (cpu_is_omap44xx()) {
643 trigger & IRQ_TYPE_LEVEL_LOW); 694 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
644 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, 695 trigger & IRQ_TYPE_LEVEL_LOW);
645 trigger & IRQ_TYPE_LEVEL_HIGH); 696 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
646 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, 697 trigger & IRQ_TYPE_LEVEL_HIGH);
647 trigger & IRQ_TYPE_EDGE_RISING); 698 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
648 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, 699 trigger & IRQ_TYPE_EDGE_RISING);
649 trigger & IRQ_TYPE_EDGE_FALLING); 700 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
650 701 trigger & IRQ_TYPE_EDGE_FALLING);
702 } else {
703 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
704 trigger & IRQ_TYPE_LEVEL_LOW);
705 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
706 trigger & IRQ_TYPE_LEVEL_HIGH);
707 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
708 trigger & IRQ_TYPE_EDGE_RISING);
709 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
710 trigger & IRQ_TYPE_EDGE_FALLING);
711 }
651 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { 712 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
652 if (trigger != 0) 713 if (cpu_is_omap44xx()) {
653 __raw_writel(1 << gpio, bank->base 714 if (trigger != 0)
715 __raw_writel(1 << gpio, bank->base+
716 OMAP4_GPIO_IRQWAKEN0);
717 else {
718 val = __raw_readl(bank->base +
719 OMAP4_GPIO_IRQWAKEN0);
720 __raw_writel(val & (~(1 << gpio)), bank->base +
721 OMAP4_GPIO_IRQWAKEN0);
722 }
723 } else {
724 if (trigger != 0)
725 __raw_writel(1 << gpio, bank->base
654 + OMAP24XX_GPIO_SETWKUENA); 726 + OMAP24XX_GPIO_SETWKUENA);
655 else 727 else
656 __raw_writel(1 << gpio, bank->base 728 __raw_writel(1 << gpio, bank->base
657 + OMAP24XX_GPIO_CLEARWKUENA); 729 + OMAP24XX_GPIO_CLEARWKUENA);
730 }
658 } else { 731 } else {
659 if (trigger != 0) 732 if (trigger != 0)
660 bank->enabled_non_wakeup_gpios |= gpio_bit; 733 bank->enabled_non_wakeup_gpios |= gpio_bit;
@@ -662,9 +735,15 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
662 bank->enabled_non_wakeup_gpios &= ~gpio_bit; 735 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
663 } 736 }
664 737
665 bank->level_mask = 738 if (cpu_is_omap44xx()) {
666 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) | 739 bank->level_mask =
667 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); 740 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
741 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
742 } else {
743 bank->level_mask =
744 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
745 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
746 }
668} 747}
669#endif 748#endif
670 749
@@ -828,12 +907,16 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
828 reg += OMAP850_GPIO_INT_STATUS; 907 reg += OMAP850_GPIO_INT_STATUS;
829 break; 908 break;
830#endif 909#endif
831#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 910#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
832 defined(CONFIG_ARCH_OMAP4)
833 case METHOD_GPIO_24XX: 911 case METHOD_GPIO_24XX:
834 reg += OMAP24XX_GPIO_IRQSTATUS1; 912 reg += OMAP24XX_GPIO_IRQSTATUS1;
835 break; 913 break;
836#endif 914#endif
915#if defined(CONFIG_ARCH_OMAP4)
916 case METHOD_GPIO_24XX:
917 reg += OMAP4_GPIO_IRQSTATUS0;
918 break;
919#endif
837 default: 920 default:
838 WARN_ON(1); 921 WARN_ON(1);
839 return; 922 return;
@@ -843,12 +926,16 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
843 /* Workaround for clearing DSP GPIO interrupts to allow retention */ 926 /* Workaround for clearing DSP GPIO interrupts to allow retention */
844#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 927#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
845 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; 928 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
846 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 929#endif
930#if defined(CONFIG_ARCH_OMAP4)
931 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
932#endif
933 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
847 __raw_writel(gpio_mask, reg); 934 __raw_writel(gpio_mask, reg);
848 935
849 /* Flush posted write for the irq status to avoid spurious interrupts */ 936 /* Flush posted write for the irq status to avoid spurious interrupts */
850 __raw_readl(reg); 937 __raw_readl(reg);
851#endif 938 }
852} 939}
853 940
854static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) 941static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
@@ -898,13 +985,18 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
898 inv = 1; 985 inv = 1;
899 break; 986 break;
900#endif 987#endif
901#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 988#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
902 defined(CONFIG_ARCH_OMAP4)
903 case METHOD_GPIO_24XX: 989 case METHOD_GPIO_24XX:
904 reg += OMAP24XX_GPIO_IRQENABLE1; 990 reg += OMAP24XX_GPIO_IRQENABLE1;
905 mask = 0xffffffff; 991 mask = 0xffffffff;
906 break; 992 break;
907#endif 993#endif
994#if defined(CONFIG_ARCH_OMAP4)
995 case METHOD_GPIO_24XX:
996 reg += OMAP4_GPIO_IRQSTATUSSET0;
997 mask = 0xffffffff;
998 break;
999#endif
908 default: 1000 default:
909 WARN_ON(1); 1001 WARN_ON(1);
910 return 0; 1002 return 0;
@@ -972,8 +1064,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
972 l |= gpio_mask; 1064 l |= gpio_mask;
973 break; 1065 break;
974#endif 1066#endif
975#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1067#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
976 defined(CONFIG_ARCH_OMAP4)
977 case METHOD_GPIO_24XX: 1068 case METHOD_GPIO_24XX:
978 if (enable) 1069 if (enable)
979 reg += OMAP24XX_GPIO_SETIRQENABLE1; 1070 reg += OMAP24XX_GPIO_SETIRQENABLE1;
@@ -982,6 +1073,15 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
982 l = gpio_mask; 1073 l = gpio_mask;
983 break; 1074 break;
984#endif 1075#endif
1076#ifdef CONFIG_ARCH_OMAP4
1077 case METHOD_GPIO_24XX:
1078 if (enable)
1079 reg += OMAP4_GPIO_IRQSTATUSSET0;
1080 else
1081 reg += OMAP4_GPIO_IRQSTATUSCLR0;
1082 l = gpio_mask;
1083 break;
1084#endif
985 default: 1085 default:
986 WARN_ON(1); 1086 WARN_ON(1);
987 return; 1087 return;
@@ -1157,11 +1257,14 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1157 if (bank->method == METHOD_GPIO_850) 1257 if (bank->method == METHOD_GPIO_850)
1158 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS; 1258 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
1159#endif 1259#endif
1160#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1260#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1161 defined(CONFIG_ARCH_OMAP4)
1162 if (bank->method == METHOD_GPIO_24XX) 1261 if (bank->method == METHOD_GPIO_24XX)
1163 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; 1262 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1164#endif 1263#endif
1264#if defined(CONFIG_ARCH_OMAP4)
1265 if (bank->method == METHOD_GPIO_24XX)
1266 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1267#endif
1165 while(1) { 1268 while(1) {
1166 u32 isr_saved, level_mask = 0; 1269 u32 isr_saved, level_mask = 0;
1167 u32 enabled; 1270 u32 enabled;
@@ -1315,8 +1418,9 @@ static struct irq_chip mpuio_irq_chip = {
1315 1418
1316#include <linux/platform_device.h> 1419#include <linux/platform_device.h>
1317 1420
1318static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg) 1421static int omap_mpuio_suspend_noirq(struct device *dev)
1319{ 1422{
1423 struct platform_device *pdev = to_platform_device(dev);
1320 struct gpio_bank *bank = platform_get_drvdata(pdev); 1424 struct gpio_bank *bank = platform_get_drvdata(pdev);
1321 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; 1425 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1322 unsigned long flags; 1426 unsigned long flags;
@@ -1329,8 +1433,9 @@ static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t me
1329 return 0; 1433 return 0;
1330} 1434}
1331 1435
1332static int omap_mpuio_resume_early(struct platform_device *pdev) 1436static int omap_mpuio_resume_noirq(struct device *dev)
1333{ 1437{
1438 struct platform_device *pdev = to_platform_device(dev);
1334 struct gpio_bank *bank = platform_get_drvdata(pdev); 1439 struct gpio_bank *bank = platform_get_drvdata(pdev);
1335 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; 1440 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1336 unsigned long flags; 1441 unsigned long flags;
@@ -1342,14 +1447,18 @@ static int omap_mpuio_resume_early(struct platform_device *pdev)
1342 return 0; 1447 return 0;
1343} 1448}
1344 1449
1450static struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1451 .suspend_noirq = omap_mpuio_suspend_noirq,
1452 .resume_noirq = omap_mpuio_resume_noirq,
1453};
1454
1345/* use platform_driver for this, now that there's no longer any 1455/* use platform_driver for this, now that there's no longer any
1346 * point to sys_device (other than not disturbing old code). 1456 * point to sys_device (other than not disturbing old code).
1347 */ 1457 */
1348static struct platform_driver omap_mpuio_driver = { 1458static struct platform_driver omap_mpuio_driver = {
1349 .suspend_late = omap_mpuio_suspend_late,
1350 .resume_early = omap_mpuio_resume_early,
1351 .driver = { 1459 .driver = {
1352 .name = "mpuio", 1460 .name = "mpuio",
1461 .pm = &omap_mpuio_dev_pm_ops,
1353 }, 1462 },
1354}; 1463};
1355 1464
@@ -1638,7 +1747,7 @@ static int __init _omap_gpio_init(void)
1638 1747
1639 gpio_bank_count = OMAP34XX_NR_GPIOS; 1748 gpio_bank_count = OMAP34XX_NR_GPIOS;
1640 gpio_bank = gpio_bank_44xx; 1749 gpio_bank = gpio_bank_44xx;
1641 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); 1750 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1642 printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n", 1751 printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
1643 (rev >> 4) & 0x0f, rev & 0x0f); 1752 (rev >> 4) & 0x0f, rev & 0x0f);
1644 } 1753 }
@@ -1672,7 +1781,16 @@ static int __init _omap_gpio_init(void)
1672 static const u32 non_wakeup_gpios[] = { 1781 static const u32 non_wakeup_gpios[] = {
1673 0xe203ffc0, 0x08700040 1782 0xe203ffc0, 0x08700040
1674 }; 1783 };
1675 1784 if (cpu_is_omap44xx()) {
1785 __raw_writel(0xffffffff, bank->base +
1786 OMAP4_GPIO_IRQSTATUSCLR0);
1787 __raw_writew(0x0015, bank->base +
1788 OMAP4_GPIO_SYSCONFIG);
1789 __raw_writel(0x00000000, bank->base +
1790 OMAP4_GPIO_DEBOUNCENABLE);
1791 /* Initialize interface clock ungated, module enabled */
1792 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1793 } else {
1676 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1); 1794 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1677 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1); 1795 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1678 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG); 1796 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
@@ -1680,12 +1798,12 @@ static int __init _omap_gpio_init(void)
1680 1798
1681 /* Initialize interface clock ungated, module enabled */ 1799 /* Initialize interface clock ungated, module enabled */
1682 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); 1800 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1801 }
1683 if (i < ARRAY_SIZE(non_wakeup_gpios)) 1802 if (i < ARRAY_SIZE(non_wakeup_gpios))
1684 bank->non_wakeup_gpios = non_wakeup_gpios[i]; 1803 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1685 gpio_count = 32; 1804 gpio_count = 32;
1686 } 1805 }
1687#endif 1806#endif
1688
1689 /* REVISIT eventually switch from OMAP-specific gpio structs 1807 /* REVISIT eventually switch from OMAP-specific gpio structs
1690 * over to the generic ones 1808 * over to the generic ones
1691 */ 1809 */
@@ -1771,14 +1889,20 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1771 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1889 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1772 break; 1890 break;
1773#endif 1891#endif
1774#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1892#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1775 defined(CONFIG_ARCH_OMAP4)
1776 case METHOD_GPIO_24XX: 1893 case METHOD_GPIO_24XX:
1777 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; 1894 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1778 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1895 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1779 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; 1896 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1780 break; 1897 break;
1781#endif 1898#endif
1899#ifdef CONFIG_ARCH_OMAP4
1900 case METHOD_GPIO_24XX:
1901 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1902 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1903 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1904 break;
1905#endif
1782 default: 1906 default:
1783 continue; 1907 continue;
1784 } 1908 }
@@ -1813,13 +1937,18 @@ static int omap_gpio_resume(struct sys_device *dev)
1813 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1937 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1814 break; 1938 break;
1815#endif 1939#endif
1816#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1940#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1817 defined(CONFIG_ARCH_OMAP4)
1818 case METHOD_GPIO_24XX: 1941 case METHOD_GPIO_24XX:
1819 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1942 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1820 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; 1943 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1821 break; 1944 break;
1822#endif 1945#endif
1946#ifdef CONFIG_ARCH_OMAP4
1947 case METHOD_GPIO_24XX:
1948 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1949 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1950 break;
1951#endif
1823 default: 1952 default:
1824 continue; 1953 continue;
1825 } 1954 }
@@ -1863,21 +1992,29 @@ void omap2_gpio_prepare_for_retention(void)
1863 1992
1864 if (!(bank->enabled_non_wakeup_gpios)) 1993 if (!(bank->enabled_non_wakeup_gpios))
1865 continue; 1994 continue;
1866#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1995#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1867 defined(CONFIG_ARCH_OMAP4)
1868 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); 1996 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1869 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1997 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1870 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); 1998 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1871#endif 1999#endif
2000#ifdef CONFIG_ARCH_OMAP4
2001 bank->saved_datain = __raw_readl(bank->base +
2002 OMAP4_GPIO_DATAIN);
2003 l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT);
2004 l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT);
2005#endif
1872 bank->saved_fallingdetect = l1; 2006 bank->saved_fallingdetect = l1;
1873 bank->saved_risingdetect = l2; 2007 bank->saved_risingdetect = l2;
1874 l1 &= ~bank->enabled_non_wakeup_gpios; 2008 l1 &= ~bank->enabled_non_wakeup_gpios;
1875 l2 &= ~bank->enabled_non_wakeup_gpios; 2009 l2 &= ~bank->enabled_non_wakeup_gpios;
1876#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 2010#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1877 defined(CONFIG_ARCH_OMAP4)
1878 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT); 2011 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1879 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT); 2012 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1880#endif 2013#endif
2014#ifdef CONFIG_ARCH_OMAP4
2015 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
2016 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
2017#endif
1881 c++; 2018 c++;
1882 } 2019 }
1883 if (!c) { 2020 if (!c) {
@@ -1899,27 +2036,29 @@ void omap2_gpio_resume_after_retention(void)
1899 2036
1900 if (!(bank->enabled_non_wakeup_gpios)) 2037 if (!(bank->enabled_non_wakeup_gpios))
1901 continue; 2038 continue;
1902#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 2039#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1903 defined(CONFIG_ARCH_OMAP4)
1904 __raw_writel(bank->saved_fallingdetect, 2040 __raw_writel(bank->saved_fallingdetect,
1905 bank->base + OMAP24XX_GPIO_FALLINGDETECT); 2041 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1906 __raw_writel(bank->saved_risingdetect, 2042 __raw_writel(bank->saved_risingdetect,
1907 bank->base + OMAP24XX_GPIO_RISINGDETECT); 2043 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2044 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
2045#endif
2046#ifdef CONFIG_ARCH_OMAP4
2047 __raw_writel(bank->saved_fallingdetect,
2048 bank->base + OMAP4_GPIO_FALLINGDETECT);
2049 __raw_writel(bank->saved_risingdetect,
2050 bank->base + OMAP4_GPIO_RISINGDETECT);
2051 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1908#endif 2052#endif
1909 /* Check if any of the non-wakeup interrupt GPIOs have changed 2053 /* Check if any of the non-wakeup interrupt GPIOs have changed
1910 * state. If so, generate an IRQ by software. This is 2054 * state. If so, generate an IRQ by software. This is
1911 * horribly racy, but it's the best we can do to work around 2055 * horribly racy, but it's the best we can do to work around
1912 * this silicon bug. */ 2056 * this silicon bug. */
1913#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1914 defined(CONFIG_ARCH_OMAP4)
1915 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1916#endif
1917 l ^= bank->saved_datain; 2057 l ^= bank->saved_datain;
1918 l &= bank->non_wakeup_gpios; 2058 l &= bank->non_wakeup_gpios;
1919 if (l) { 2059 if (l) {
1920 u32 old0, old1; 2060 u32 old0, old1;
1921#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 2061#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1922 defined(CONFIG_ARCH_OMAP4)
1923 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); 2062 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1924 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); 2063 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1925 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0); 2064 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
@@ -1927,6 +2066,20 @@ void omap2_gpio_resume_after_retention(void)
1927 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0); 2066 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1928 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1); 2067 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1929#endif 2068#endif
2069#ifdef CONFIG_ARCH_OMAP4
2070 old0 = __raw_readl(bank->base +
2071 OMAP4_GPIO_LEVELDETECT0);
2072 old1 = __raw_readl(bank->base +
2073 OMAP4_GPIO_LEVELDETECT1);
2074 __raw_writel(old0 | l, bank->base +
2075 OMAP4_GPIO_LEVELDETECT0);
2076 __raw_writel(old1 | l, bank->base +
2077 OMAP4_GPIO_LEVELDETECT1);
2078 __raw_writel(old0, bank->base +
2079 OMAP4_GPIO_LEVELDETECT0);
2080 __raw_writel(old1, bank->base +
2081 OMAP4_GPIO_LEVELDETECT1);
2082#endif
1930 } 2083 }
1931 } 2084 }
1932 2085
diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/mach/dma.h
index 7b939cc01962..72f680b7180d 100644
--- a/arch/arm/plat-omap/include/mach/dma.h
+++ b/arch/arm/plat-omap/include/mach/dma.h
@@ -122,6 +122,11 @@
122#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0) 122#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0)
123#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4) 123#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4)
124 124
125/* Additional registers available on OMAP4 */
126#define OMAP_DMA4_CDP(n) (0x60 * (n) + 0xd0)
127#define OMAP_DMA4_CNDP(n) (0x60 * (n) + 0xd4)
128#define OMAP_DMA4_CCDN(n) (0x60 * (n) + 0xd8)
129
125/* Dummy defines to keep multi-omap compiles happy */ 130/* Dummy defines to keep multi-omap compiles happy */
126#define OMAP1_DMA_REVISION 0 131#define OMAP1_DMA_REVISION 0
127#define OMAP1_DMA_IRQSTATUS_L0 0 132#define OMAP1_DMA_IRQSTATUS_L0 0
@@ -311,6 +316,89 @@
311#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ 316#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
312#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ 317#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */
313 318
319/* DMA request lines for 44xx */
320#define OMAP44XX_DMA_DSS_DISPC_REQ 6 /* S_DMA_5 */
321#define OMAP44XX_DMA_SYS_REQ2 7 /* S_DMA_6 */
322#define OMAP44XX_DMA_ISS_REQ1 9 /* S_DMA_8 */
323#define OMAP44XX_DMA_ISS_REQ2 10 /* S_DMA_9 */
324#define OMAP44XX_DMA_ISS_REQ3 12 /* S_DMA_11 */
325#define OMAP44XX_DMA_ISS_REQ4 13 /* S_DMA_12 */
326#define OMAP44XX_DMA_DSS_RFBI_REQ 14 /* S_DMA_13 */
327#define OMAP44XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
328#define OMAP44XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
329#define OMAP44XX_DMA_MCBSP2_TX 17 /* S_DMA_16 */
330#define OMAP44XX_DMA_MCBSP2_RX 18 /* S_DMA_17 */
331#define OMAP44XX_DMA_MCBSP3_TX 19 /* S_DMA_18 */
332#define OMAP44XX_DMA_MCBSP3_RX 20 /* S_DMA_19 */
333#define OMAP44XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
334#define OMAP44XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
335#define OMAP44XX_DMA_I2C3_TX 25 /* S_DMA_24 */
336#define OMAP44XX_DMA_I2C3_RX 26 /* S_DMA_25 */
337#define OMAP44XX_DMA_I2C1_TX 27 /* S_DMA_26 */
338#define OMAP44XX_DMA_I2C1_RX 28 /* S_DMA_27 */
339#define OMAP44XX_DMA_I2C2_TX 29 /* S_DMA_28 */
340#define OMAP44XX_DMA_I2C2_RX 30 /* S_DMA_29 */
341#define OMAP44XX_DMA_MCBSP4_TX 31 /* S_DMA_30 */
342#define OMAP44XX_DMA_MCBSP4_RX 32 /* S_DMA_31 */
343#define OMAP44XX_DMA_MCBSP1_TX 33 /* S_DMA_32 */
344#define OMAP44XX_DMA_MCBSP1_RX 34 /* S_DMA_33 */
345#define OMAP44XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
346#define OMAP44XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
347#define OMAP44XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
348#define OMAP44XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
349#define OMAP44XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
350#define OMAP44XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
351#define OMAP44XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
352#define OMAP44XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
353#define OMAP44XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
354#define OMAP44XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
355#define OMAP44XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
356#define OMAP44XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
357#define OMAP44XX_DMA_MMC2_TX 47 /* S_DMA_46 */
358#define OMAP44XX_DMA_MMC2_RX 48 /* S_DMA_47 */
359#define OMAP44XX_DMA_UART1_TX 49 /* S_DMA_48 */
360#define OMAP44XX_DMA_UART1_RX 50 /* S_DMA_49 */
361#define OMAP44XX_DMA_UART2_TX 51 /* S_DMA_50 */
362#define OMAP44XX_DMA_UART2_RX 52 /* S_DMA_51 */
363#define OMAP44XX_DMA_UART3_TX 53 /* S_DMA_52 */
364#define OMAP44XX_DMA_UART3_RX 54 /* S_DMA_53 */
365#define OMAP44XX_DMA_UART4_TX 55 /* S_DMA_54 */
366#define OMAP44XX_DMA_UART4_RX 56 /* S_DMA_55 */
367#define OMAP44XX_DMA_MMC4_TX 57 /* S_DMA_56 */
368#define OMAP44XX_DMA_MMC4_RX 58 /* S_DMA_57 */
369#define OMAP44XX_DMA_MMC5_TX 59 /* S_DMA_58 */
370#define OMAP44XX_DMA_MMC5_RX 60 /* S_DMA_59 */
371#define OMAP44XX_DMA_MMC1_TX 61 /* S_DMA_60 */
372#define OMAP44XX_DMA_MMC1_RX 62 /* S_DMA_61 */
373#define OMAP44XX_DMA_SYS_REQ3 64 /* S_DMA_63 */
374#define OMAP44XX_DMA_MCPDM_UP 65 /* S_DMA_64 */
375#define OMAP44XX_DMA_MCPDM_DL 66 /* S_DMA_65 */
376#define OMAP44XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
377#define OMAP44XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
378#define OMAP44XX_DMA_DSS_DSI1_REQ0 72 /* S_DMA_71 */
379#define OMAP44XX_DMA_DSS_DSI1_REQ1 73 /* S_DMA_72 */
380#define OMAP44XX_DMA_DSS_DSI1_REQ2 74 /* S_DMA_73 */
381#define OMAP44XX_DMA_DSS_DSI1_REQ3 75 /* S_DMA_74 */
382#define OMAP44XX_DMA_DSS_HDMI_REQ 76 /* S_DMA_75 */
383#define OMAP44XX_DMA_MMC3_TX 77 /* S_DMA_76 */
384#define OMAP44XX_DMA_MMC3_RX 78 /* S_DMA_77 */
385#define OMAP44XX_DMA_USIM_TX 79 /* S_DMA_78 */
386#define OMAP44XX_DMA_USIM_RX 80 /* S_DMA_79 */
387#define OMAP44XX_DMA_DSS_DSI2_REQ0 81 /* S_DMA_80 */
388#define OMAP44XX_DMA_DSS_DSI2_REQ1 82 /* S_DMA_81 */
389#define OMAP44XX_DMA_DSS_DSI2_REQ2 83 /* S_DMA_82 */
390#define OMAP44XX_DMA_DSS_DSI2_REQ3 84 /* S_DMA_83 */
391#define OMAP44XX_DMA_ABE_REQ0 101 /* S_DMA_100 */
392#define OMAP44XX_DMA_ABE_REQ1 102 /* S_DMA_101 */
393#define OMAP44XX_DMA_ABE_REQ2 103 /* S_DMA_102 */
394#define OMAP44XX_DMA_ABE_REQ3 104 /* S_DMA_103 */
395#define OMAP44XX_DMA_ABE_REQ4 105 /* S_DMA_104 */
396#define OMAP44XX_DMA_ABE_REQ5 106 /* S_DMA_105 */
397#define OMAP44XX_DMA_ABE_REQ6 107 /* S_DMA_106 */
398#define OMAP44XX_DMA_ABE_REQ7 108 /* S_DMA_107 */
399#define OMAP44XX_DMA_I2C4_TX 124 /* S_DMA_123 */
400#define OMAP44XX_DMA_I2C4_RX 125 /* S_DMA_124 */
401
314/*----------------------------------------------------------------------------*/ 402/*----------------------------------------------------------------------------*/
315 403
316/* Hardware registers for LCD DMA */ 404/* Hardware registers for LCD DMA */
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h
index bb154ea76769..e0d6eca222cc 100644
--- a/arch/arm/plat-omap/include/mach/mcbsp.h
+++ b/arch/arm/plat-omap/include/mach/mcbsp.h
@@ -53,6 +53,11 @@
53#define OMAP34XX_MCBSP4_BASE 0x49026000 53#define OMAP34XX_MCBSP4_BASE 0x49026000
54#define OMAP34XX_MCBSP5_BASE 0x48096000 54#define OMAP34XX_MCBSP5_BASE 0x48096000
55 55
56#define OMAP44XX_MCBSP1_BASE 0x49022000
57#define OMAP44XX_MCBSP2_BASE 0x49024000
58#define OMAP44XX_MCBSP3_BASE 0x49026000
59#define OMAP44XX_MCBSP4_BASE 0x48074000
60
56#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) 61#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
57 62
58#define OMAP_MCBSP_REG_DRR2 0x00 63#define OMAP_MCBSP_REG_DRR2 0x00
@@ -98,7 +103,8 @@
98#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX 103#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
99#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX 104#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
100 105
101#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 106#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
107 defined(CONFIG_ARCH_OMAP4)
102 108
103#define OMAP_MCBSP_REG_DRR2 0x00 109#define OMAP_MCBSP_REG_DRR2 0x00
104#define OMAP_MCBSP_REG_DRR1 0x04 110#define OMAP_MCBSP_REG_DRR1 0x04
@@ -134,6 +140,11 @@
134#define OMAP_MCBSP_REG_XCERG 0x74 140#define OMAP_MCBSP_REG_XCERG 0x74
135#define OMAP_MCBSP_REG_XCERH 0x78 141#define OMAP_MCBSP_REG_XCERH 0x78
136#define OMAP_MCBSP_REG_SYSCON 0x8C 142#define OMAP_MCBSP_REG_SYSCON 0x8C
143#define OMAP_MCBSP_REG_THRSH2 0x90
144#define OMAP_MCBSP_REG_THRSH1 0x94
145#define OMAP_MCBSP_REG_IRQST 0xA0
146#define OMAP_MCBSP_REG_IRQEN 0xA4
147#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
137#define OMAP_MCBSP_REG_XCCR 0xAC 148#define OMAP_MCBSP_REG_XCCR 0xAC
138#define OMAP_MCBSP_REG_RCCR 0xB0 149#define OMAP_MCBSP_REG_RCCR 0xB0
139 150
@@ -249,8 +260,27 @@
249#define RDISABLE 0x0001 260#define RDISABLE 0x0001
250 261
251/********************** McBSP SYSCONFIG bit definitions ********************/ 262/********************** McBSP SYSCONFIG bit definitions ********************/
263#define CLOCKACTIVITY(value) ((value)<<8)
264#define SIDLEMODE(value) ((value)<<3)
265#define ENAWAKEUP 0x0004
252#define SOFTRST 0x0002 266#define SOFTRST 0x0002
253 267
268/********************** McBSP DMA operating modes **************************/
269#define MCBSP_DMA_MODE_ELEMENT 0
270#define MCBSP_DMA_MODE_THRESHOLD 1
271#define MCBSP_DMA_MODE_FRAME 2
272
273/********************** McBSP WAKEUPEN bit definitions *********************/
274#define XEMPTYEOFEN 0x4000
275#define XRDYEN 0x0400
276#define XEOFEN 0x0200
277#define XFSXEN 0x0100
278#define XSYNCERREN 0x0080
279#define RRDYEN 0x0008
280#define REOFEN 0x0004
281#define RFSREN 0x0002
282#define RSYNCERREN 0x0001
283
254/* we don't do multichannel for now */ 284/* we don't do multichannel for now */
255struct omap_mcbsp_reg_cfg { 285struct omap_mcbsp_reg_cfg {
256 u16 spcr2; 286 u16 spcr2;
@@ -344,6 +374,9 @@ struct omap_mcbsp_platform_data {
344 u8 dma_rx_sync, dma_tx_sync; 374 u8 dma_rx_sync, dma_tx_sync;
345 u16 rx_irq, tx_irq; 375 u16 rx_irq, tx_irq;
346 struct omap_mcbsp_ops *ops; 376 struct omap_mcbsp_ops *ops;
377#ifdef CONFIG_ARCH_OMAP34XX
378 u16 buffer_size;
379#endif
347}; 380};
348 381
349struct omap_mcbsp { 382struct omap_mcbsp {
@@ -377,6 +410,11 @@ struct omap_mcbsp {
377 struct omap_mcbsp_platform_data *pdata; 410 struct omap_mcbsp_platform_data *pdata;
378 struct clk *iclk; 411 struct clk *iclk;
379 struct clk *fclk; 412 struct clk *fclk;
413#ifdef CONFIG_ARCH_OMAP34XX
414 int dma_op_mode;
415 u16 max_tx_thres;
416 u16 max_rx_thres;
417#endif
380}; 418};
381extern struct omap_mcbsp **mcbsp_ptr; 419extern struct omap_mcbsp **mcbsp_ptr;
382extern int omap_mcbsp_count; 420extern int omap_mcbsp_count;
@@ -385,10 +423,25 @@ int omap_mcbsp_init(void);
385void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, 423void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
386 int size); 424 int size);
387void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); 425void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
426#ifdef CONFIG_ARCH_OMAP34XX
427void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
428void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
429u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
430u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
431int omap_mcbsp_get_dma_op_mode(unsigned int id);
432#else
433static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
434{ }
435static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
436{ }
437static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
438static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
439static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
440#endif
388int omap_mcbsp_request(unsigned int id); 441int omap_mcbsp_request(unsigned int id);
389void omap_mcbsp_free(unsigned int id); 442void omap_mcbsp_free(unsigned int id);
390void omap_mcbsp_start(unsigned int id); 443void omap_mcbsp_start(unsigned int id, int tx, int rx);
391void omap_mcbsp_stop(unsigned int id); 444void omap_mcbsp_stop(unsigned int id, int tx, int rx);
392void omap_mcbsp_xmit_word(unsigned int id, u32 word); 445void omap_mcbsp_xmit_word(unsigned int id, u32 word);
393u32 omap_mcbsp_recv_word(unsigned int id); 446u32 omap_mcbsp_recv_word(unsigned int id);
394 447
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index efa0e0111f38..88ac9768f1c1 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -191,13 +191,177 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
191 OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2); 191 OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
192 OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1); 192 OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
193 OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0); 193 OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
194 if (cpu_is_omap2430() || cpu_is_omap34xx()) { 194 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
195 OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr); 195 OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
196 OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr); 196 OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
197 } 197 }
198} 198}
199EXPORT_SYMBOL(omap_mcbsp_config); 199EXPORT_SYMBOL(omap_mcbsp_config);
200 200
201#ifdef CONFIG_ARCH_OMAP34XX
202/*
203 * omap_mcbsp_set_tx_threshold configures how to deal
204 * with transmit threshold. the threshold value and handler can be
205 * configure in here.
206 */
207void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
208{
209 struct omap_mcbsp *mcbsp;
210 void __iomem *io_base;
211
212 if (!cpu_is_omap34xx())
213 return;
214
215 if (!omap_mcbsp_check_valid_id(id)) {
216 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
217 return;
218 }
219 mcbsp = id_to_mcbsp_ptr(id);
220 io_base = mcbsp->io_base;
221
222 OMAP_MCBSP_WRITE(io_base, THRSH2, threshold);
223}
224EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
225
226/*
227 * omap_mcbsp_set_rx_threshold configures how to deal
228 * with receive threshold. the threshold value and handler can be
229 * configure in here.
230 */
231void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
232{
233 struct omap_mcbsp *mcbsp;
234 void __iomem *io_base;
235
236 if (!cpu_is_omap34xx())
237 return;
238
239 if (!omap_mcbsp_check_valid_id(id)) {
240 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
241 return;
242 }
243 mcbsp = id_to_mcbsp_ptr(id);
244 io_base = mcbsp->io_base;
245
246 OMAP_MCBSP_WRITE(io_base, THRSH1, threshold);
247}
248EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
249
250/*
251 * omap_mcbsp_get_max_tx_thres just return the current configured
252 * maximum threshold for transmission
253 */
254u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
255{
256 struct omap_mcbsp *mcbsp;
257
258 if (!omap_mcbsp_check_valid_id(id)) {
259 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
260 return -ENODEV;
261 }
262 mcbsp = id_to_mcbsp_ptr(id);
263
264 return mcbsp->max_tx_thres;
265}
266EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
267
268/*
269 * omap_mcbsp_get_max_rx_thres just return the current configured
270 * maximum threshold for reception
271 */
272u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
273{
274 struct omap_mcbsp *mcbsp;
275
276 if (!omap_mcbsp_check_valid_id(id)) {
277 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
278 return -ENODEV;
279 }
280 mcbsp = id_to_mcbsp_ptr(id);
281
282 return mcbsp->max_rx_thres;
283}
284EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
285
286/*
287 * omap_mcbsp_get_dma_op_mode just return the current configured
288 * operating mode for the mcbsp channel
289 */
290int omap_mcbsp_get_dma_op_mode(unsigned int id)
291{
292 struct omap_mcbsp *mcbsp;
293 int dma_op_mode;
294
295 if (!omap_mcbsp_check_valid_id(id)) {
296 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
297 return -ENODEV;
298 }
299 mcbsp = id_to_mcbsp_ptr(id);
300
301 spin_lock_irq(&mcbsp->lock);
302 dma_op_mode = mcbsp->dma_op_mode;
303 spin_unlock_irq(&mcbsp->lock);
304
305 return dma_op_mode;
306}
307EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
308
309static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
310{
311 /*
312 * Enable wakup behavior, smart idle and all wakeups
313 * REVISIT: some wakeups may be unnecessary
314 */
315 if (cpu_is_omap34xx()) {
316 u16 syscon;
317
318 syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
319 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
320
321 spin_lock_irq(&mcbsp->lock);
322 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
323 syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
324 CLOCKACTIVITY(0x02));
325 OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN,
326 XRDYEN | RRDYEN);
327 } else {
328 syscon |= SIDLEMODE(0x01);
329 }
330 spin_unlock_irq(&mcbsp->lock);
331
332 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
333 }
334}
335
336static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
337{
338 /*
339 * Disable wakup behavior, smart idle and all wakeups
340 */
341 if (cpu_is_omap34xx()) {
342 u16 syscon;
343
344 syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
345 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
346 /*
347 * HW bug workaround - If no_idle mode is taken, we need to
348 * go to smart_idle before going to always_idle, or the
349 * device will not hit retention anymore.
350 */
351 syscon |= SIDLEMODE(0x02);
352 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
353
354 syscon &= ~(SIDLEMODE(0x03));
355 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
356
357 OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN, 0);
358 }
359}
360#else
361static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
362static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
363#endif
364
201/* 365/*
202 * We can choose between IRQ based or polled IO. 366 * We can choose between IRQ based or polled IO.
203 * This needs to be called before omap_mcbsp_request(). 367 * This needs to be called before omap_mcbsp_request().
@@ -257,6 +421,9 @@ int omap_mcbsp_request(unsigned int id)
257 clk_enable(mcbsp->iclk); 421 clk_enable(mcbsp->iclk);
258 clk_enable(mcbsp->fclk); 422 clk_enable(mcbsp->fclk);
259 423
424 /* Do procedure specific to omap34xx arch, if applicable */
425 omap34xx_mcbsp_request(mcbsp);
426
260 /* 427 /*
261 * Make sure that transmitter, receiver and sample-rate generator are 428 * Make sure that transmitter, receiver and sample-rate generator are
262 * not running before activating IRQs. 429 * not running before activating IRQs.
@@ -305,6 +472,9 @@ void omap_mcbsp_free(unsigned int id)
305 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free) 472 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
306 mcbsp->pdata->ops->free(id); 473 mcbsp->pdata->ops->free(id);
307 474
475 /* Do procedure specific to omap34xx arch, if applicable */
476 omap34xx_mcbsp_free(mcbsp);
477
308 clk_disable(mcbsp->fclk); 478 clk_disable(mcbsp->fclk);
309 clk_disable(mcbsp->iclk); 479 clk_disable(mcbsp->iclk);
310 480
@@ -328,14 +498,15 @@ void omap_mcbsp_free(unsigned int id)
328EXPORT_SYMBOL(omap_mcbsp_free); 498EXPORT_SYMBOL(omap_mcbsp_free);
329 499
330/* 500/*
331 * Here we start the McBSP, by enabling the sample 501 * Here we start the McBSP, by enabling transmitter, receiver or both.
332 * generator, both transmitter and receivers, 502 * If no transmitter or receiver is active prior calling, then sample-rate
333 * and the frame sync. 503 * generator and frame sync are started.
334 */ 504 */
335void omap_mcbsp_start(unsigned int id) 505void omap_mcbsp_start(unsigned int id, int tx, int rx)
336{ 506{
337 struct omap_mcbsp *mcbsp; 507 struct omap_mcbsp *mcbsp;
338 void __iomem *io_base; 508 void __iomem *io_base;
509 int idle;
339 u16 w; 510 u16 w;
340 511
341 if (!omap_mcbsp_check_valid_id(id)) { 512 if (!omap_mcbsp_check_valid_id(id)) {
@@ -348,32 +519,58 @@ void omap_mcbsp_start(unsigned int id)
348 mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7; 519 mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
349 mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7; 520 mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
350 521
351 /* Start the sample generator */ 522 idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
352 w = OMAP_MCBSP_READ(io_base, SPCR2); 523 OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
353 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6)); 524
525 if (idle) {
526 /* Start the sample generator */
527 w = OMAP_MCBSP_READ(io_base, SPCR2);
528 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
529 }
354 530
355 /* Enable transmitter and receiver */ 531 /* Enable transmitter and receiver */
532 tx &= 1;
356 w = OMAP_MCBSP_READ(io_base, SPCR2); 533 w = OMAP_MCBSP_READ(io_base, SPCR2);
357 OMAP_MCBSP_WRITE(io_base, SPCR2, w | 1); 534 OMAP_MCBSP_WRITE(io_base, SPCR2, w | tx);
358 535
536 rx &= 1;
359 w = OMAP_MCBSP_READ(io_base, SPCR1); 537 w = OMAP_MCBSP_READ(io_base, SPCR1);
360 OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1); 538 OMAP_MCBSP_WRITE(io_base, SPCR1, w | rx);
361 539
362 udelay(100); 540 /*
541 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
542 * REVISIT: 100us may give enough time for two CLKSRG, however
543 * due to some unknown PM related, clock gating etc. reason it
544 * is now at 500us.
545 */
546 udelay(500);
363 547
364 /* Start frame sync */ 548 if (idle) {
365 w = OMAP_MCBSP_READ(io_base, SPCR2); 549 /* Start frame sync */
366 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7)); 550 w = OMAP_MCBSP_READ(io_base, SPCR2);
551 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
552 }
553
554 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
555 /* Release the transmitter and receiver */
556 w = OMAP_MCBSP_READ(io_base, XCCR);
557 w &= ~(tx ? XDISABLE : 0);
558 OMAP_MCBSP_WRITE(io_base, XCCR, w);
559 w = OMAP_MCBSP_READ(io_base, RCCR);
560 w &= ~(rx ? RDISABLE : 0);
561 OMAP_MCBSP_WRITE(io_base, RCCR, w);
562 }
367 563
368 /* Dump McBSP Regs */ 564 /* Dump McBSP Regs */
369 omap_mcbsp_dump_reg(id); 565 omap_mcbsp_dump_reg(id);
370} 566}
371EXPORT_SYMBOL(omap_mcbsp_start); 567EXPORT_SYMBOL(omap_mcbsp_start);
372 568
373void omap_mcbsp_stop(unsigned int id) 569void omap_mcbsp_stop(unsigned int id, int tx, int rx)
374{ 570{
375 struct omap_mcbsp *mcbsp; 571 struct omap_mcbsp *mcbsp;
376 void __iomem *io_base; 572 void __iomem *io_base;
573 int idle;
377 u16 w; 574 u16 w;
378 575
379 if (!omap_mcbsp_check_valid_id(id)) { 576 if (!omap_mcbsp_check_valid_id(id)) {
@@ -385,16 +582,33 @@ void omap_mcbsp_stop(unsigned int id)
385 io_base = mcbsp->io_base; 582 io_base = mcbsp->io_base;
386 583
387 /* Reset transmitter */ 584 /* Reset transmitter */
585 tx &= 1;
586 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
587 w = OMAP_MCBSP_READ(io_base, XCCR);
588 w |= (tx ? XDISABLE : 0);
589 OMAP_MCBSP_WRITE(io_base, XCCR, w);
590 }
388 w = OMAP_MCBSP_READ(io_base, SPCR2); 591 w = OMAP_MCBSP_READ(io_base, SPCR2);
389 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1)); 592 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~tx);
390 593
391 /* Reset receiver */ 594 /* Reset receiver */
595 rx &= 1;
596 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
597 w = OMAP_MCBSP_READ(io_base, RCCR);
598 w |= (tx ? RDISABLE : 0);
599 OMAP_MCBSP_WRITE(io_base, RCCR, w);
600 }
392 w = OMAP_MCBSP_READ(io_base, SPCR1); 601 w = OMAP_MCBSP_READ(io_base, SPCR1);
393 OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(1)); 602 OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~rx);
394 603
395 /* Reset the sample rate generator */ 604 idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
396 w = OMAP_MCBSP_READ(io_base, SPCR2); 605 OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
397 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6)); 606
607 if (idle) {
608 /* Reset the sample rate generator */
609 w = OMAP_MCBSP_READ(io_base, SPCR2);
610 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
611 }
398} 612}
399EXPORT_SYMBOL(omap_mcbsp_stop); 613EXPORT_SYMBOL(omap_mcbsp_stop);
400 614
@@ -883,6 +1097,149 @@ void omap_mcbsp_set_spi_mode(unsigned int id,
883} 1097}
884EXPORT_SYMBOL(omap_mcbsp_set_spi_mode); 1098EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
885 1099
1100#ifdef CONFIG_ARCH_OMAP34XX
1101#define max_thres(m) (mcbsp->pdata->buffer_size)
1102#define valid_threshold(m, val) ((val) <= max_thres(m))
1103#define THRESHOLD_PROP_BUILDER(prop) \
1104static ssize_t prop##_show(struct device *dev, \
1105 struct device_attribute *attr, char *buf) \
1106{ \
1107 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1108 \
1109 return sprintf(buf, "%u\n", mcbsp->prop); \
1110} \
1111 \
1112static ssize_t prop##_store(struct device *dev, \
1113 struct device_attribute *attr, \
1114 const char *buf, size_t size) \
1115{ \
1116 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1117 unsigned long val; \
1118 int status; \
1119 \
1120 status = strict_strtoul(buf, 0, &val); \
1121 if (status) \
1122 return status; \
1123 \
1124 if (!valid_threshold(mcbsp, val)) \
1125 return -EDOM; \
1126 \
1127 mcbsp->prop = val; \
1128 return size; \
1129} \
1130 \
1131static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1132
1133THRESHOLD_PROP_BUILDER(max_tx_thres);
1134THRESHOLD_PROP_BUILDER(max_rx_thres);
1135
1136static const char *dma_op_modes[] = {
1137 "element", "threshold", "frame",
1138};
1139
1140static ssize_t dma_op_mode_show(struct device *dev,
1141 struct device_attribute *attr, char *buf)
1142{
1143 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1144 int dma_op_mode, i = 0;
1145 ssize_t len = 0;
1146 const char * const *s;
1147
1148 spin_lock_irq(&mcbsp->lock);
1149 dma_op_mode = mcbsp->dma_op_mode;
1150 spin_unlock_irq(&mcbsp->lock);
1151
1152 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1153 if (dma_op_mode == i)
1154 len += sprintf(buf + len, "[%s] ", *s);
1155 else
1156 len += sprintf(buf + len, "%s ", *s);
1157 }
1158 len += sprintf(buf + len, "\n");
1159
1160 return len;
1161}
1162
1163static ssize_t dma_op_mode_store(struct device *dev,
1164 struct device_attribute *attr,
1165 const char *buf, size_t size)
1166{
1167 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1168 const char * const *s;
1169 int i = 0;
1170
1171 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1172 if (sysfs_streq(buf, *s))
1173 break;
1174
1175 if (i == ARRAY_SIZE(dma_op_modes))
1176 return -EINVAL;
1177
1178 spin_lock_irq(&mcbsp->lock);
1179 if (!mcbsp->free) {
1180 size = -EBUSY;
1181 goto unlock;
1182 }
1183 mcbsp->dma_op_mode = i;
1184
1185unlock:
1186 spin_unlock_irq(&mcbsp->lock);
1187
1188 return size;
1189}
1190
1191static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1192
1193static const struct attribute *additional_attrs[] = {
1194 &dev_attr_max_tx_thres.attr,
1195 &dev_attr_max_rx_thres.attr,
1196 &dev_attr_dma_op_mode.attr,
1197 NULL,
1198};
1199
1200static const struct attribute_group additional_attr_group = {
1201 .attrs = (struct attribute **)additional_attrs,
1202};
1203
1204static inline int __devinit omap_additional_add(struct device *dev)
1205{
1206 return sysfs_create_group(&dev->kobj, &additional_attr_group);
1207}
1208
1209static inline void __devexit omap_additional_remove(struct device *dev)
1210{
1211 sysfs_remove_group(&dev->kobj, &additional_attr_group);
1212}
1213
1214static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1215{
1216 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1217 if (cpu_is_omap34xx()) {
1218 mcbsp->max_tx_thres = max_thres(mcbsp);
1219 mcbsp->max_rx_thres = max_thres(mcbsp);
1220 /*
1221 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1222 * for mcbsp2 instances.
1223 */
1224 if (omap_additional_add(mcbsp->dev))
1225 dev_warn(mcbsp->dev,
1226 "Unable to create additional controls\n");
1227 } else {
1228 mcbsp->max_tx_thres = -EINVAL;
1229 mcbsp->max_rx_thres = -EINVAL;
1230 }
1231}
1232
1233static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1234{
1235 if (cpu_is_omap34xx())
1236 omap_additional_remove(mcbsp->dev);
1237}
1238#else
1239static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1240static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1241#endif /* CONFIG_ARCH_OMAP34XX */
1242
886/* 1243/*
887 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510. 1244 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
888 * 730 has only 2 McBSP, and both of them are MPU peripherals. 1245 * 730 has only 2 McBSP, and both of them are MPU peripherals.
@@ -953,6 +1310,10 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
953 mcbsp->dev = &pdev->dev; 1310 mcbsp->dev = &pdev->dev;
954 mcbsp_ptr[id] = mcbsp; 1311 mcbsp_ptr[id] = mcbsp;
955 platform_set_drvdata(pdev, mcbsp); 1312 platform_set_drvdata(pdev, mcbsp);
1313
1314 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1315 omap34xx_device_init(mcbsp);
1316
956 return 0; 1317 return 0;
957 1318
958err_fclk: 1319err_fclk:
@@ -976,6 +1337,8 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
976 mcbsp->pdata->ops->free) 1337 mcbsp->pdata->ops->free)
977 mcbsp->pdata->ops->free(mcbsp->id); 1338 mcbsp->pdata->ops->free(mcbsp->id);
978 1339
1340 omap34xx_device_exit(mcbsp);
1341
979 clk_disable(mcbsp->fclk); 1342 clk_disable(mcbsp->fclk);
980 clk_disable(mcbsp->iclk); 1343 clk_disable(mcbsp->iclk);
981 clk_put(mcbsp->fclk); 1344 clk_put(mcbsp->fclk);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 17:48:01 -0500