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authorRajendra Nayak <rnayak@ti.com>2008-09-26 08:19:02 -0400
committerKevin Hilman <khilman@deeprootsystems.com>2009-11-11 17:42:24 -0500
commitc96631e13888e9be3a80aae291ed671d4d573ec9 (patch)
treef27784eb60630d7a3ac64508350967d7c5f97101 /arch/arm/plat-omap
parent8014078684377257e3a83ac45db95711929850c5 (diff)
OMAP3: PM: SCM context save/restore
Add context save and restore for the System Control Module to suport off-mode. ETK and debobs definitions added by Peter De Schrijver. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r--arch/arm/plat-omap/include/plat/control.h49
1 files changed, 47 insertions, 2 deletions
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
index 1076dd967390..8ca73471ba45 100644
--- a/arch/arm/plat-omap/include/plat/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -146,8 +146,51 @@
146#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) 146#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
147#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) 147#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
148#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) 148#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
149#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02b0) 149#define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \
150#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4) 150 + ((i) >> 1) * 4 + (!(i) & 1) * 2)
151#define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4)
152#define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8)
153#define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0)
154#define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4)
155#define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8)
156#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
157#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0)
158#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4)
159#define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8)
160#define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0)
161#define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4)
162
163
164/* 34xx PADCONF register offsets */
165#define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
166 (i)*2)
167#define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0)
168#define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1)
169#define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2)
170#define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3)
171#define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4)
172#define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5)
173#define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6)
174#define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7)
175#define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8)
176#define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9)
177#define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10)
178#define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11)
179#define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12)
180#define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13)
181#define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14)
182#define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15)
183#define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16)
184#define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17)
185
186/* 34xx GENERAL_WKUP regist offsets */
187#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
188 0x008 + (i))
189#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
190#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
191#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
192#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
193#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
151 194
152/* 34xx D2D idle-related pins, handled by PM core */ 195/* 34xx D2D idle-related pins, handled by PM core */
153#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 196#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
@@ -226,6 +269,8 @@ extern void omap3_save_scratchpad_contents(void);
226extern void omap3_clear_scratchpad_contents(void); 269extern void omap3_clear_scratchpad_contents(void);
227extern u32 *get_restore_pointer(void); 270extern u32 *get_restore_pointer(void);
228extern u32 omap3_arm_context[128]; 271extern u32 omap3_arm_context[128];
272extern void omap3_control_save_context(void);
273extern void omap3_control_restore_context(void);
229 274
230#else 275#else
231#define omap_ctrl_base_get() 0 276#define omap_ctrl_base_get() 0