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authorAbhijit Pagare <abhijitpagare@ti.com>2010-01-26 22:12:52 -0500
committerPaul Walmsley <paul@pwsan.com>2010-01-26 22:12:52 -0500
commit38900c27fbbbe97e16f448b8bc9cafc05af03460 (patch)
tree6b2c90dd83235f0ca08ee0f55c82cf7c45dc3a61 /arch/arm/plat-omap
parentf37c6dfac99451b8babdd320d7aed4e03d51b94b (diff)
ARM: OMAP4: PM: Adapt the existing OMAP2/3 and common Power Domain Frameworks.
Taking care of the platform specific and common power domains with proper checks. Also refining some Macros according to the latest OMAP4 requirements. Signed-off-by: Abhijit Pagare <abhijitpagare@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com>
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r--arch/arm/plat-omap/include/plat/powerdomain.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index 2510005e5ef0..bac378eff8df 100644
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -51,16 +51,16 @@
51 */ 51 */
52 52
53/* 53/*
54 * Number of memory banks that are power-controllable. On OMAP3430, the 54 * Number of memory banks that are power-controllable. On OMAP4430, the
55 * maximum is 4. 55 * maximum is 5.
56 */ 56 */
57#define PWRDM_MAX_MEM_BANKS 4 57#define PWRDM_MAX_MEM_BANKS 5
58 58
59/* 59/*
60 * Maximum number of clockdomains that can be associated with a powerdomain. 60 * Maximum number of clockdomains that can be associated with a powerdomain.
61 * CORE powerdomain on OMAP3 is the worst case 61 * CORE powerdomain on OMAP4 is the worst case
62 */ 62 */
63#define PWRDM_MAX_CLKDMS 4 63#define PWRDM_MAX_CLKDMS 9
64 64
65/* XXX A completely arbitrary number. What is reasonable here? */ 65/* XXX A completely arbitrary number. What is reasonable here? */
66#define PWRDM_TRANSITION_BAILOUT 100000 66#define PWRDM_TRANSITION_BAILOUT 100000