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authorDavid Woodhouse <David.Woodhouse@intel.com>2008-07-25 10:40:14 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2008-07-25 10:40:14 -0400
commitff877ea80efa2015b6263766f78ee42c2a1b32f9 (patch)
tree85205005c611ab774702148558321c6fb92f1ccd /arch/arm/plat-omap
parent30821fee4f0cb3e6d241d9f7ddc37742212e3eb7 (diff)
parentd37e6bf68fc1eb34a4ad21d9ae8890ed37ea80e7 (diff)
Merge branch 'linux-next' of git://git.infradead.org/~dedekind/ubi-2.6
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r--arch/arm/plat-omap/Makefile2
-rw-r--r--arch/arm/plat-omap/clock.c128
-rw-r--r--arch/arm/plat-omap/common.c59
-rw-r--r--arch/arm/plat-omap/devices.c48
-rw-r--r--arch/arm/plat-omap/dma.c764
-rw-r--r--arch/arm/plat-omap/dmtimer.c212
-rw-r--r--arch/arm/plat-omap/mailbox.c2
-rw-r--r--arch/arm/plat-omap/mcbsp.c767
-rw-r--r--arch/arm/plat-omap/sram-fn.S57
-rw-r--r--arch/arm/plat-omap/sram.c211
-rw-r--r--arch/arm/plat-omap/usb.c131
11 files changed, 1406 insertions, 975 deletions
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index bc639a30d6d1..2c4051cc79a1 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := common.o sram.o sram-fn.o clock.o devices.o dma.o mux.o gpio.o \ 6obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \
7 usb.o fb.o 7 usb.o fb.o
8obj-m := 8obj-m :=
9obj-n := 9obj-n :=
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 2db5580048d8..c2e741de0203 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/arm/plat-omap/clock.c 2 * linux/arch/arm/plat-omap/clock.c
3 * 3 *
4 * Copyright (C) 2004 - 2005 Nokia corporation 4 * Copyright (C) 2004 - 2008 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * 6 *
7 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com> 7 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
@@ -22,6 +22,7 @@
22#include <linux/mutex.h> 22#include <linux/mutex.h>
23#include <linux/platform_device.h> 23#include <linux/platform_device.h>
24#include <linux/cpufreq.h> 24#include <linux/cpufreq.h>
25#include <linux/debugfs.h>
25 26
26#include <asm/io.h> 27#include <asm/io.h>
27 28
@@ -33,41 +34,6 @@ static DEFINE_SPINLOCK(clockfw_lock);
33 34
34static struct clk_functions *arch_clock; 35static struct clk_functions *arch_clock;
35 36
36#ifdef CONFIG_PM_DEBUG
37
38static void print_parents(struct clk *clk)
39{
40 struct clk *p;
41 int printed = 0;
42
43 list_for_each_entry(p, &clocks, node) {
44 if (p->parent == clk && p->usecount) {
45 if (!clk->usecount && !printed) {
46 printk("MISMATCH: %s\n", clk->name);
47 printed = 1;
48 }
49 printk("\t%-15s\n", p->name);
50 }
51 }
52}
53
54void clk_print_usecounts(void)
55{
56 unsigned long flags;
57 struct clk *p;
58
59 spin_lock_irqsave(&clockfw_lock, flags);
60 list_for_each_entry(p, &clocks, node) {
61 if (p->usecount)
62 printk("%-15s: %d\n", p->name, p->usecount);
63 print_parents(p);
64
65 }
66 spin_unlock_irqrestore(&clockfw_lock, flags);
67}
68
69#endif
70
71/*------------------------------------------------------------------------- 37/*-------------------------------------------------------------------------
72 * Standard clock functions defined in include/linux/clk.h 38 * Standard clock functions defined in include/linux/clk.h
73 *-------------------------------------------------------------------------*/ 39 *-------------------------------------------------------------------------*/
@@ -446,3 +412,93 @@ int __init clk_init(struct clk_functions * custom_clocks)
446 return 0; 412 return 0;
447} 413}
448 414
415#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
416/*
417 * debugfs support to trace clock tree hierarchy and attributes
418 */
419static struct dentry *clk_debugfs_root;
420
421static int clk_debugfs_register_one(struct clk *c)
422{
423 int err;
424 struct dentry *d, *child;
425 struct clk *pa = c->parent;
426 char s[255];
427 char *p = s;
428
429 p += sprintf(p, "%s", c->name);
430 if (c->id != 0)
431 sprintf(p, ":%d", c->id);
432 d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
433 if (IS_ERR(d))
434 return PTR_ERR(d);
435 c->dent = d;
436
437 d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount);
438 if (IS_ERR(d)) {
439 err = PTR_ERR(d);
440 goto err_out;
441 }
442 d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
443 if (IS_ERR(d)) {
444 err = PTR_ERR(d);
445 goto err_out;
446 }
447 d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
448 if (IS_ERR(d)) {
449 err = PTR_ERR(d);
450 goto err_out;
451 }
452 return 0;
453
454err_out:
455 d = c->dent;
456 list_for_each_entry(child, &d->d_subdirs, d_u.d_child)
457 debugfs_remove(child);
458 debugfs_remove(c->dent);
459 return err;
460}
461
462static int clk_debugfs_register(struct clk *c)
463{
464 int err;
465 struct clk *pa = c->parent;
466
467 if (pa && !pa->dent) {
468 err = clk_debugfs_register(pa);
469 if (err)
470 return err;
471 }
472
473 if (!c->dent) {
474 err = clk_debugfs_register_one(c);
475 if (err)
476 return err;
477 }
478 return 0;
479}
480
481static int __init clk_debugfs_init(void)
482{
483 struct clk *c;
484 struct dentry *d;
485 int err;
486
487 d = debugfs_create_dir("clock", NULL);
488 if (IS_ERR(d))
489 return PTR_ERR(d);
490 clk_debugfs_root = d;
491
492 list_for_each_entry(c, &clocks, node) {
493 err = clk_debugfs_register(c);
494 if (err)
495 goto err_out;
496 }
497 return 0;
498err_out:
499 debugfs_remove(clk_debugfs_root); /* REVISIT: Cleanup correctly */
500 return err;
501}
502late_initcall(clk_debugfs_init);
503
504#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index bd1cef2c3c14..8d04929a3c75 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -26,6 +26,7 @@
26#include <asm/io.h> 26#include <asm/io.h>
27#include <asm/setup.h> 27#include <asm/setup.h>
28 28
29#include <asm/arch/common.h>
29#include <asm/arch/board.h> 30#include <asm/arch/board.h>
30#include <asm/arch/control.h> 31#include <asm/arch/control.h>
31#include <asm/arch/mux.h> 32#include <asm/arch/mux.h>
@@ -241,30 +242,70 @@ arch_initcall(omap_init_clocksource_32k);
241 242
242/* Global address base setup code */ 243/* Global address base setup code */
243 244
245#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
246
247static struct omap_globals *omap2_globals;
248
249static void __init __omap2_set_globals(void)
250{
251 omap2_set_globals_memory(omap2_globals);
252 omap2_set_globals_control(omap2_globals);
253 omap2_set_globals_prcm(omap2_globals);
254}
255
256#endif
257
244#if defined(CONFIG_ARCH_OMAP2420) 258#if defined(CONFIG_ARCH_OMAP2420)
259
260static struct omap_globals omap242x_globals = {
261 .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x48014000),
262 .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE),
263 .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE),
264 .ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE),
265 .prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE),
266 .cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_CM_BASE),
267};
268
245void __init omap2_set_globals_242x(void) 269void __init omap2_set_globals_242x(void)
246{ 270{
247 omap2_sdrc_base = OMAP2420_SDRC_BASE; 271 omap2_globals = &omap242x_globals;
248 omap2_sms_base = OMAP2420_SMS_BASE; 272 __omap2_set_globals();
249 omap_ctrl_base_set(OMAP2420_CTRL_BASE);
250} 273}
251#endif 274#endif
252 275
253#if defined(CONFIG_ARCH_OMAP2430) 276#if defined(CONFIG_ARCH_OMAP2430)
277
278static struct omap_globals omap243x_globals = {
279 .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4900a000),
280 .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE),
281 .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE),
282 .ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE),
283 .prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE),
284 .cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2430_CM_BASE),
285};
286
254void __init omap2_set_globals_243x(void) 287void __init omap2_set_globals_243x(void)
255{ 288{
256 omap2_sdrc_base = OMAP243X_SDRC_BASE; 289 omap2_globals = &omap243x_globals;
257 omap2_sms_base = OMAP243X_SMS_BASE; 290 __omap2_set_globals();
258 omap_ctrl_base_set(OMAP243X_CTRL_BASE);
259} 291}
260#endif 292#endif
261 293
262#if defined(CONFIG_ARCH_OMAP3430) 294#if defined(CONFIG_ARCH_OMAP3430)
295
296static struct omap_globals omap343x_globals = {
297 .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4830A000),
298 .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE),
299 .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE),
300 .ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE),
301 .prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE),
302 .cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP3430_CM_BASE),
303};
304
263void __init omap2_set_globals_343x(void) 305void __init omap2_set_globals_343x(void)
264{ 306{
265 omap2_sdrc_base = OMAP343X_SDRC_BASE; 307 omap2_globals = &omap343x_globals;
266 omap2_sms_base = OMAP343X_SMS_BASE; 308 __omap2_set_globals();
267 omap_ctrl_base_set(OMAP343X_CTRL_BASE);
268} 309}
269#endif 310#endif
270 311
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 4a53f9ba6c43..81002b722da1 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -24,6 +24,7 @@
24#include <asm/arch/mux.h> 24#include <asm/arch/mux.h>
25#include <asm/arch/gpio.h> 25#include <asm/arch/gpio.h>
26#include <asm/arch/menelaus.h> 26#include <asm/arch/menelaus.h>
27#include <asm/arch/mcbsp.h>
27 28
28#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) 29#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
29 30
@@ -145,6 +146,53 @@ static inline void omap_init_kp(void) {}
145#endif 146#endif
146 147
147/*-------------------------------------------------------------------------*/ 148/*-------------------------------------------------------------------------*/
149#if defined(CONFIG_OMAP_MCBSP) || defined(CONFIG_OMAP_MCBSP_MODULE)
150
151static struct platform_device **omap_mcbsp_devices;
152
153void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
154 int size)
155{
156 int i;
157
158 if (size > OMAP_MAX_MCBSP_COUNT) {
159 printk(KERN_WARNING "Registered too many McBSPs platform_data."
160 " Using maximum (%d) available.\n",
161 OMAP_MAX_MCBSP_COUNT);
162 size = OMAP_MAX_MCBSP_COUNT;
163 }
164
165 omap_mcbsp_devices = kzalloc(size * sizeof(struct platform_device *),
166 GFP_KERNEL);
167 if (!omap_mcbsp_devices) {
168 printk(KERN_ERR "Could not register McBSP devices\n");
169 return;
170 }
171
172 for (i = 0; i < size; i++) {
173 struct platform_device *new_mcbsp;
174 int ret;
175
176 new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1);
177 if (!new_mcbsp)
178 continue;
179 new_mcbsp->dev.platform_data = &config[i];
180 ret = platform_device_add(new_mcbsp);
181 if (ret) {
182 platform_device_put(new_mcbsp);
183 continue;
184 }
185 omap_mcbsp_devices[i] = new_mcbsp;
186 }
187}
188
189#else
190void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
191 int size)
192{ }
193#endif
194
195/*-------------------------------------------------------------------------*/
148 196
149#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) 197#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
150 198
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 39c637b0ffea..fac8e994f588 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/arm/plat-omap/dma.c 2 * linux/arch/arm/plat-omap/dma.c
3 * 3 *
4 * Copyright (C) 2003 Nokia Corporation 4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com> 5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> 6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations 7 * Graphics DMA and LCD DMA graphics tranformations
@@ -25,11 +25,11 @@
25#include <linux/errno.h> 25#include <linux/errno.h>
26#include <linux/interrupt.h> 26#include <linux/interrupt.h>
27#include <linux/irq.h> 27#include <linux/irq.h>
28#include <linux/io.h>
28 29
29#include <asm/system.h> 30#include <asm/system.h>
30#include <asm/hardware.h> 31#include <asm/hardware.h>
31#include <asm/dma.h> 32#include <asm/dma.h>
32#include <asm/io.h>
33 33
34#include <asm/arch/tc.h> 34#include <asm/arch/tc.h>
35 35
@@ -43,13 +43,13 @@ enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
43enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; 43enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
44#endif 44#endif
45 45
46#define OMAP_DMA_ACTIVE 0x01 46#define OMAP_DMA_ACTIVE 0x01
47#define OMAP_DMA_CCR_EN (1 << 7) 47#define OMAP_DMA_CCR_EN (1 << 7)
48#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe 48#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
49 49
50#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) 50#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
51 51
52static int enable_1510_mode = 0; 52static int enable_1510_mode;
53 53
54struct omap_dma_lch { 54struct omap_dma_lch {
55 int next_lch; 55 int next_lch;
@@ -57,7 +57,7 @@ struct omap_dma_lch {
57 u16 saved_csr; 57 u16 saved_csr;
58 u16 enabled_irqs; 58 u16 enabled_irqs;
59 const char *dev_name; 59 const char *dev_name;
60 void (* callback)(int lch, u16 ch_status, void *data); 60 void (*callback)(int lch, u16 ch_status, void *data);
61 void *data; 61 void *data;
62 62
63#ifndef CONFIG_ARCH_OMAP1 63#ifndef CONFIG_ARCH_OMAP1
@@ -72,7 +72,6 @@ struct omap_dma_lch {
72 long flags; 72 long flags;
73}; 73};
74 74
75#ifndef CONFIG_ARCH_OMAP1
76struct dma_link_info { 75struct dma_link_info {
77 int *linked_dmach_q; 76 int *linked_dmach_q;
78 int no_of_lchs_linked; 77 int no_of_lchs_linked;
@@ -86,7 +85,9 @@ struct dma_link_info {
86 85
87}; 86};
88 87
89static struct dma_link_info dma_linked_lch[OMAP_LOGICAL_DMA_CH_COUNT]; 88static struct dma_link_info *dma_linked_lch;
89
90#ifndef CONFIG_ARCH_OMAP1
90 91
91/* Chain handling macros */ 92/* Chain handling macros */
92#define OMAP_DMA_CHAIN_QINIT(chain_id) \ 93#define OMAP_DMA_CHAIN_QINIT(chain_id) \
@@ -119,12 +120,15 @@ static struct dma_link_info dma_linked_lch[OMAP_LOGICAL_DMA_CH_COUNT];
119 dma_linked_lch[chain_id].q_count++; \ 120 dma_linked_lch[chain_id].q_count++; \
120 } while (0) 121 } while (0)
121#endif 122#endif
123
124static int dma_lch_count;
122static int dma_chan_count; 125static int dma_chan_count;
123 126
124static spinlock_t dma_chan_lock; 127static spinlock_t dma_chan_lock;
125static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT]; 128static struct omap_dma_lch *dma_chan;
129static void __iomem *omap_dma_base;
126 130
127static const u8 omap1_dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = { 131static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
128 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3, 132 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
129 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7, 133 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
130 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10, 134 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
@@ -139,6 +143,24 @@ static inline void omap_enable_channel_irq(int lch);
139#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \ 143#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
140 __func__); 144 __func__);
141 145
146#define dma_read(reg) \
147({ \
148 u32 __val; \
149 if (cpu_class_is_omap1()) \
150 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \
151 else \
152 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \
153 __val; \
154})
155
156#define dma_write(val, reg) \
157({ \
158 if (cpu_class_is_omap1()) \
159 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
160 else \
161 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \
162})
163
142#ifdef CONFIG_ARCH_OMAP15XX 164#ifdef CONFIG_ARCH_OMAP15XX
143/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ 165/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
144int omap_dma_in_1510_mode(void) 166int omap_dma_in_1510_mode(void)
@@ -173,13 +195,14 @@ static inline void set_gdma_dev(int req, int dev)
173#define set_gdma_dev(req, dev) do {} while (0) 195#define set_gdma_dev(req, dev) do {} while (0)
174#endif 196#endif
175 197
198/* Omap1 only */
176static void clear_lch_regs(int lch) 199static void clear_lch_regs(int lch)
177{ 200{
178 int i; 201 int i;
179 u32 lch_base = OMAP_DMA_BASE + lch * 0x40; 202 void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
180 203
181 for (i = 0; i < 0x2c; i += 2) 204 for (i = 0; i < 0x2c; i += 2)
182 omap_writew(0, lch_base + i); 205 __raw_writew(0, lch_base + i);
183} 206}
184 207
185void omap_set_dma_priority(int lch, int dst_port, int priority) 208void omap_set_dma_priority(int lch, int dst_port, int priority)
@@ -212,33 +235,49 @@ void omap_set_dma_priority(int lch, int dst_port, int priority)
212 } 235 }
213 236
214 if (cpu_class_is_omap2()) { 237 if (cpu_class_is_omap2()) {
238 u32 ccr;
239
240 ccr = dma_read(CCR(lch));
215 if (priority) 241 if (priority)
216 OMAP_DMA_CCR_REG(lch) |= (1 << 6); 242 ccr |= (1 << 6);
217 else 243 else
218 OMAP_DMA_CCR_REG(lch) &= ~(1 << 6); 244 ccr &= ~(1 << 6);
245 dma_write(ccr, CCR(lch));
219 } 246 }
220} 247}
248EXPORT_SYMBOL(omap_set_dma_priority);
221 249
222void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, 250void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
223 int frame_count, int sync_mode, 251 int frame_count, int sync_mode,
224 int dma_trigger, int src_or_dst_synch) 252 int dma_trigger, int src_or_dst_synch)
225{ 253{
226 OMAP_DMA_CSDP_REG(lch) &= ~0x03; 254 u32 l;
227 OMAP_DMA_CSDP_REG(lch) |= data_type; 255
256 l = dma_read(CSDP(lch));
257 l &= ~0x03;
258 l |= data_type;
259 dma_write(l, CSDP(lch));
228 260
229 if (cpu_class_is_omap1()) { 261 if (cpu_class_is_omap1()) {
230 OMAP_DMA_CCR_REG(lch) &= ~(1 << 5); 262 u16 ccr;
263
264 ccr = dma_read(CCR(lch));
265 ccr &= ~(1 << 5);
231 if (sync_mode == OMAP_DMA_SYNC_FRAME) 266 if (sync_mode == OMAP_DMA_SYNC_FRAME)
232 OMAP_DMA_CCR_REG(lch) |= 1 << 5; 267 ccr |= 1 << 5;
268 dma_write(ccr, CCR(lch));
233 269
234 OMAP1_DMA_CCR2_REG(lch) &= ~(1 << 2); 270 ccr = dma_read(CCR2(lch));
271 ccr &= ~(1 << 2);
235 if (sync_mode == OMAP_DMA_SYNC_BLOCK) 272 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
236 OMAP1_DMA_CCR2_REG(lch) |= 1 << 2; 273 ccr |= 1 << 2;
274 dma_write(ccr, CCR2(lch));
237 } 275 }
238 276
239 if (cpu_class_is_omap2() && dma_trigger) { 277 if (cpu_class_is_omap2() && dma_trigger) {
240 u32 val = OMAP_DMA_CCR_REG(lch); 278 u32 val;
241 279
280 val = dma_read(CCR(lch));
242 val &= ~(3 << 19); 281 val &= ~(3 << 19);
243 if (dma_trigger > 63) 282 if (dma_trigger > 63)
244 val |= 1 << 20; 283 val |= 1 << 20;
@@ -263,12 +302,13 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
263 else 302 else
264 val &= ~(1 << 24); /* dest synch */ 303 val &= ~(1 << 24); /* dest synch */
265 304
266 OMAP_DMA_CCR_REG(lch) = val; 305 dma_write(val, CCR(lch));
267 } 306 }
268 307
269 OMAP_DMA_CEN_REG(lch) = elem_count; 308 dma_write(elem_count, CEN(lch));
270 OMAP_DMA_CFN_REG(lch) = frame_count; 309 dma_write(frame_count, CFN(lch));
271} 310}
311EXPORT_SYMBOL(omap_set_dma_transfer_params);
272 312
273void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) 313void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
274{ 314{
@@ -281,7 +321,9 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
281 return; 321 return;
282 } 322 }
283 323
284 w = OMAP1_DMA_CCR2_REG(lch) & ~0x03; 324 w = dma_read(CCR2(lch));
325 w &= ~0x03;
326
285 switch (mode) { 327 switch (mode) {
286 case OMAP_DMA_CONSTANT_FILL: 328 case OMAP_DMA_CONSTANT_FILL:
287 w |= 0x01; 329 w |= 0x01;
@@ -294,52 +336,81 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
294 default: 336 default:
295 BUG(); 337 BUG();
296 } 338 }
297 OMAP1_DMA_CCR2_REG(lch) = w; 339 dma_write(w, CCR2(lch));
298 340
299 w = OMAP1_DMA_LCH_CTRL_REG(lch) & ~0x0f; 341 w = dma_read(LCH_CTRL(lch));
342 w &= ~0x0f;
300 /* Default is channel type 2D */ 343 /* Default is channel type 2D */
301 if (mode) { 344 if (mode) {
302 OMAP1_DMA_COLOR_L_REG(lch) = (u16)color; 345 dma_write((u16)color, COLOR_L(lch));
303 OMAP1_DMA_COLOR_U_REG(lch) = (u16)(color >> 16); 346 dma_write((u16)(color >> 16), COLOR_U(lch));
304 w |= 1; /* Channel type G */ 347 w |= 1; /* Channel type G */
305 } 348 }
306 OMAP1_DMA_LCH_CTRL_REG(lch) = w; 349 dma_write(w, LCH_CTRL(lch));
307} 350}
351EXPORT_SYMBOL(omap_set_dma_color_mode);
308 352
309void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) 353void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
310{ 354{
311 if (cpu_class_is_omap2()) { 355 if (cpu_class_is_omap2()) {
312 OMAP_DMA_CSDP_REG(lch) &= ~(0x3 << 16); 356 u32 csdp;
313 OMAP_DMA_CSDP_REG(lch) |= (mode << 16); 357
358 csdp = dma_read(CSDP(lch));
359 csdp &= ~(0x3 << 16);
360 csdp |= (mode << 16);
361 dma_write(csdp, CSDP(lch));
362 }
363}
364EXPORT_SYMBOL(omap_set_dma_write_mode);
365
366void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
367{
368 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
369 u32 l;
370
371 l = dma_read(LCH_CTRL(lch));
372 l &= ~0x7;
373 l |= mode;
374 dma_write(l, LCH_CTRL(lch));
314 } 375 }
315} 376}
377EXPORT_SYMBOL(omap_set_dma_channel_mode);
316 378
317/* Note that src_port is only for omap1 */ 379/* Note that src_port is only for omap1 */
318void omap_set_dma_src_params(int lch, int src_port, int src_amode, 380void omap_set_dma_src_params(int lch, int src_port, int src_amode,
319 unsigned long src_start, 381 unsigned long src_start,
320 int src_ei, int src_fi) 382 int src_ei, int src_fi)
321{ 383{
384 u32 l;
385
322 if (cpu_class_is_omap1()) { 386 if (cpu_class_is_omap1()) {
323 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 2); 387 u16 w;
324 OMAP_DMA_CSDP_REG(lch) |= src_port << 2; 388
389 w = dma_read(CSDP(lch));
390 w &= ~(0x1f << 2);
391 w |= src_port << 2;
392 dma_write(w, CSDP(lch));
325 } 393 }
326 394
327 OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 12); 395 l = dma_read(CCR(lch));
328 OMAP_DMA_CCR_REG(lch) |= src_amode << 12; 396 l &= ~(0x03 << 12);
397 l |= src_amode << 12;
398 dma_write(l, CCR(lch));
329 399
330 if (cpu_class_is_omap1()) { 400 if (cpu_class_is_omap1()) {
331 OMAP1_DMA_CSSA_U_REG(lch) = src_start >> 16; 401 dma_write(src_start >> 16, CSSA_U(lch));
332 OMAP1_DMA_CSSA_L_REG(lch) = src_start; 402 dma_write((u16)src_start, CSSA_L(lch));
333 } 403 }
334 404
335 if (cpu_class_is_omap2()) 405 if (cpu_class_is_omap2())
336 OMAP2_DMA_CSSA_REG(lch) = src_start; 406 dma_write(src_start, CSSA(lch));
337 407
338 OMAP_DMA_CSEI_REG(lch) = src_ei; 408 dma_write(src_ei, CSEI(lch));
339 OMAP_DMA_CSFI_REG(lch) = src_fi; 409 dma_write(src_fi, CSFI(lch));
340} 410}
411EXPORT_SYMBOL(omap_set_dma_src_params);
341 412
342void omap_set_dma_params(int lch, struct omap_dma_channel_params * params) 413void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
343{ 414{
344 omap_set_dma_transfer_params(lch, params->data_type, 415 omap_set_dma_transfer_params(lch, params->data_type,
345 params->elem_count, params->frame_count, 416 params->elem_count, params->frame_count,
@@ -356,28 +427,37 @@ void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
356 omap_dma_set_prio_lch(lch, params->read_prio, 427 omap_dma_set_prio_lch(lch, params->read_prio,
357 params->write_prio); 428 params->write_prio);
358} 429}
430EXPORT_SYMBOL(omap_set_dma_params);
359 431
360void omap_set_dma_src_index(int lch, int eidx, int fidx) 432void omap_set_dma_src_index(int lch, int eidx, int fidx)
361{ 433{
362 if (cpu_class_is_omap2()) { 434 if (cpu_class_is_omap2())
363 REVISIT_24XX();
364 return; 435 return;
365 } 436
366 OMAP_DMA_CSEI_REG(lch) = eidx; 437 dma_write(eidx, CSEI(lch));
367 OMAP_DMA_CSFI_REG(lch) = fidx; 438 dma_write(fidx, CSFI(lch));
368} 439}
440EXPORT_SYMBOL(omap_set_dma_src_index);
369 441
370void omap_set_dma_src_data_pack(int lch, int enable) 442void omap_set_dma_src_data_pack(int lch, int enable)
371{ 443{
372 OMAP_DMA_CSDP_REG(lch) &= ~(1 << 6); 444 u32 l;
445
446 l = dma_read(CSDP(lch));
447 l &= ~(1 << 6);
373 if (enable) 448 if (enable)
374 OMAP_DMA_CSDP_REG(lch) |= (1 << 6); 449 l |= (1 << 6);
450 dma_write(l, CSDP(lch));
375} 451}
452EXPORT_SYMBOL(omap_set_dma_src_data_pack);
376 453
377void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) 454void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
378{ 455{
379 unsigned int burst = 0; 456 unsigned int burst = 0;
380 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7); 457 u32 l;
458
459 l = dma_read(CSDP(lch));
460 l &= ~(0x03 << 7);
381 461
382 switch (burst_mode) { 462 switch (burst_mode) {
383 case OMAP_DMA_DATA_BURST_DIS: 463 case OMAP_DMA_DATA_BURST_DIS:
@@ -408,55 +488,73 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
408 default: 488 default:
409 BUG(); 489 BUG();
410 } 490 }
411 OMAP_DMA_CSDP_REG(lch) |= (burst << 7); 491
492 l |= (burst << 7);
493 dma_write(l, CSDP(lch));
412} 494}
495EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
413 496
414/* Note that dest_port is only for OMAP1 */ 497/* Note that dest_port is only for OMAP1 */
415void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, 498void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
416 unsigned long dest_start, 499 unsigned long dest_start,
417 int dst_ei, int dst_fi) 500 int dst_ei, int dst_fi)
418{ 501{
502 u32 l;
503
419 if (cpu_class_is_omap1()) { 504 if (cpu_class_is_omap1()) {
420 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 9); 505 l = dma_read(CSDP(lch));
421 OMAP_DMA_CSDP_REG(lch) |= dest_port << 9; 506 l &= ~(0x1f << 9);
507 l |= dest_port << 9;
508 dma_write(l, CSDP(lch));
422 } 509 }
423 510
424 OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 14); 511 l = dma_read(CCR(lch));
425 OMAP_DMA_CCR_REG(lch) |= dest_amode << 14; 512 l &= ~(0x03 << 14);
513 l |= dest_amode << 14;
514 dma_write(l, CCR(lch));
426 515
427 if (cpu_class_is_omap1()) { 516 if (cpu_class_is_omap1()) {
428 OMAP1_DMA_CDSA_U_REG(lch) = dest_start >> 16; 517 dma_write(dest_start >> 16, CDSA_U(lch));
429 OMAP1_DMA_CDSA_L_REG(lch) = dest_start; 518 dma_write(dest_start, CDSA_L(lch));
430 } 519 }
431 520
432 if (cpu_class_is_omap2()) 521 if (cpu_class_is_omap2())
433 OMAP2_DMA_CDSA_REG(lch) = dest_start; 522 dma_write(dest_start, CDSA(lch));
434 523
435 OMAP_DMA_CDEI_REG(lch) = dst_ei; 524 dma_write(dst_ei, CDEI(lch));
436 OMAP_DMA_CDFI_REG(lch) = dst_fi; 525 dma_write(dst_fi, CDFI(lch));
437} 526}
527EXPORT_SYMBOL(omap_set_dma_dest_params);
438 528
439void omap_set_dma_dest_index(int lch, int eidx, int fidx) 529void omap_set_dma_dest_index(int lch, int eidx, int fidx)
440{ 530{
441 if (cpu_class_is_omap2()) { 531 if (cpu_class_is_omap2())
442 REVISIT_24XX();
443 return; 532 return;
444 } 533
445 OMAP_DMA_CDEI_REG(lch) = eidx; 534 dma_write(eidx, CDEI(lch));
446 OMAP_DMA_CDFI_REG(lch) = fidx; 535 dma_write(fidx, CDFI(lch));
447} 536}
537EXPORT_SYMBOL(omap_set_dma_dest_index);
448 538
449void omap_set_dma_dest_data_pack(int lch, int enable) 539void omap_set_dma_dest_data_pack(int lch, int enable)
450{ 540{
451 OMAP_DMA_CSDP_REG(lch) &= ~(1 << 13); 541 u32 l;
542
543 l = dma_read(CSDP(lch));
544 l &= ~(1 << 13);
452 if (enable) 545 if (enable)
453 OMAP_DMA_CSDP_REG(lch) |= 1 << 13; 546 l |= 1 << 13;
547 dma_write(l, CSDP(lch));
454} 548}
549EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
455 550
456void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) 551void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
457{ 552{
458 unsigned int burst = 0; 553 unsigned int burst = 0;
459 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14); 554 u32 l;
555
556 l = dma_read(CSDP(lch));
557 l &= ~(0x03 << 14);
460 558
461 switch (burst_mode) { 559 switch (burst_mode) {
462 case OMAP_DMA_DATA_BURST_DIS: 560 case OMAP_DMA_DATA_BURST_DIS:
@@ -486,8 +584,10 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
486 BUG(); 584 BUG();
487 return; 585 return;
488 } 586 }
489 OMAP_DMA_CSDP_REG(lch) |= (burst << 14); 587 l |= (burst << 14);
588 dma_write(l, CSDP(lch));
490} 589}
590EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
491 591
492static inline void omap_enable_channel_irq(int lch) 592static inline void omap_enable_channel_irq(int lch)
493{ 593{
@@ -495,62 +595,74 @@ static inline void omap_enable_channel_irq(int lch)
495 595
496 /* Clear CSR */ 596 /* Clear CSR */
497 if (cpu_class_is_omap1()) 597 if (cpu_class_is_omap1())
498 status = OMAP_DMA_CSR_REG(lch); 598 status = dma_read(CSR(lch));
499 else if (cpu_class_is_omap2()) 599 else if (cpu_class_is_omap2())
500 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK; 600 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
501 601
502 /* Enable some nice interrupts. */ 602 /* Enable some nice interrupts. */
503 OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs; 603 dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
504} 604}
505 605
506static void omap_disable_channel_irq(int lch) 606static void omap_disable_channel_irq(int lch)
507{ 607{
508 if (cpu_class_is_omap2()) 608 if (cpu_class_is_omap2())
509 OMAP_DMA_CICR_REG(lch) = 0; 609 dma_write(0, CICR(lch));
510} 610}
511 611
512void omap_enable_dma_irq(int lch, u16 bits) 612void omap_enable_dma_irq(int lch, u16 bits)
513{ 613{
514 dma_chan[lch].enabled_irqs |= bits; 614 dma_chan[lch].enabled_irqs |= bits;
515} 615}
616EXPORT_SYMBOL(omap_enable_dma_irq);
516 617
517void omap_disable_dma_irq(int lch, u16 bits) 618void omap_disable_dma_irq(int lch, u16 bits)
518{ 619{
519 dma_chan[lch].enabled_irqs &= ~bits; 620 dma_chan[lch].enabled_irqs &= ~bits;
520} 621}
622EXPORT_SYMBOL(omap_disable_dma_irq);
521 623
522static inline void enable_lnk(int lch) 624static inline void enable_lnk(int lch)
523{ 625{
626 u32 l;
627
628 l = dma_read(CLNK_CTRL(lch));
629
524 if (cpu_class_is_omap1()) 630 if (cpu_class_is_omap1())
525 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 14); 631 l &= ~(1 << 14);
526 632
527 /* Set the ENABLE_LNK bits */ 633 /* Set the ENABLE_LNK bits */
528 if (dma_chan[lch].next_lch != -1) 634 if (dma_chan[lch].next_lch != -1)
529 OMAP_DMA_CLNK_CTRL_REG(lch) = 635 l = dma_chan[lch].next_lch | (1 << 15);
530 dma_chan[lch].next_lch | (1 << 15);
531 636
532#ifndef CONFIG_ARCH_OMAP1 637#ifndef CONFIG_ARCH_OMAP1
533 if (dma_chan[lch].next_linked_ch != -1) 638 if (cpu_class_is_omap2())
534 OMAP_DMA_CLNK_CTRL_REG(lch) = 639 if (dma_chan[lch].next_linked_ch != -1)
535 dma_chan[lch].next_linked_ch | (1 << 15); 640 l = dma_chan[lch].next_linked_ch | (1 << 15);
536#endif 641#endif
642
643 dma_write(l, CLNK_CTRL(lch));
537} 644}
538 645
539static inline void disable_lnk(int lch) 646static inline void disable_lnk(int lch)
540{ 647{
648 u32 l;
649
650 l = dma_read(CLNK_CTRL(lch));
651
541 /* Disable interrupts */ 652 /* Disable interrupts */
542 if (cpu_class_is_omap1()) { 653 if (cpu_class_is_omap1()) {
543 OMAP_DMA_CICR_REG(lch) = 0; 654 dma_write(0, CICR(lch));
544 /* Set the STOP_LNK bit */ 655 /* Set the STOP_LNK bit */
545 OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14; 656 l |= 1 << 14;
546 } 657 }
547 658
548 if (cpu_class_is_omap2()) { 659 if (cpu_class_is_omap2()) {
549 omap_disable_channel_irq(lch); 660 omap_disable_channel_irq(lch);
550 /* Clear the ENABLE_LNK bit */ 661 /* Clear the ENABLE_LNK bit */
551 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15); 662 l &= ~(1 << 15);
552 } 663 }
553 664
665 dma_write(l, CLNK_CTRL(lch));
554 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; 666 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
555} 667}
556 668
@@ -561,13 +673,13 @@ static inline void omap2_enable_irq_lch(int lch)
561 if (!cpu_class_is_omap2()) 673 if (!cpu_class_is_omap2())
562 return; 674 return;
563 675
564 val = omap_readl(OMAP_DMA4_IRQENABLE_L0); 676 val = dma_read(IRQENABLE_L0);
565 val |= 1 << lch; 677 val |= 1 << lch;
566 omap_writel(val, OMAP_DMA4_IRQENABLE_L0); 678 dma_write(val, IRQENABLE_L0);
567} 679}
568 680
569int omap_request_dma(int dev_id, const char *dev_name, 681int omap_request_dma(int dev_id, const char *dev_name,
570 void (* callback)(int lch, u16 ch_status, void *data), 682 void (*callback)(int lch, u16 ch_status, void *data),
571 void *data, int *dma_ch_out) 683 void *data, int *dma_ch_out)
572{ 684{
573 int ch, free_ch = -1; 685 int ch, free_ch = -1;
@@ -600,10 +712,14 @@ int omap_request_dma(int dev_id, const char *dev_name,
600 chan->dev_name = dev_name; 712 chan->dev_name = dev_name;
601 chan->callback = callback; 713 chan->callback = callback;
602 chan->data = data; 714 chan->data = data;
715
603#ifndef CONFIG_ARCH_OMAP1 716#ifndef CONFIG_ARCH_OMAP1
604 chan->chain_id = -1; 717 if (cpu_class_is_omap2()) {
605 chan->next_linked_ch = -1; 718 chan->chain_id = -1;
719 chan->next_linked_ch = -1;
720 }
606#endif 721#endif
722
607 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; 723 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
608 724
609 if (cpu_class_is_omap1()) 725 if (cpu_class_is_omap1())
@@ -618,26 +734,28 @@ int omap_request_dma(int dev_id, const char *dev_name,
618 set_gdma_dev(free_ch + 1, dev_id); 734 set_gdma_dev(free_ch + 1, dev_id);
619 dev_id = free_ch + 1; 735 dev_id = free_ch + 1;
620 } 736 }
621 /* Disable the 1510 compatibility mode and set the sync device 737 /*
622 * id. */ 738 * Disable the 1510 compatibility mode and set the sync device
623 OMAP_DMA_CCR_REG(free_ch) = dev_id | (1 << 10); 739 * id.
740 */
741 dma_write(dev_id | (1 << 10), CCR(free_ch));
624 } else if (cpu_is_omap730() || cpu_is_omap15xx()) { 742 } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
625 OMAP_DMA_CCR_REG(free_ch) = dev_id; 743 dma_write(dev_id, CCR(free_ch));
626 } 744 }
627 745
628 if (cpu_class_is_omap2()) { 746 if (cpu_class_is_omap2()) {
629 omap2_enable_irq_lch(free_ch); 747 omap2_enable_irq_lch(free_ch);
630
631 omap_enable_channel_irq(free_ch); 748 omap_enable_channel_irq(free_ch);
632 /* Clear the CSR register and IRQ status register */ 749 /* Clear the CSR register and IRQ status register */
633 OMAP_DMA_CSR_REG(free_ch) = OMAP2_DMA_CSR_CLEAR_MASK; 750 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
634 omap_writel(1 << free_ch, OMAP_DMA4_IRQSTATUS_L0); 751 dma_write(1 << free_ch, IRQSTATUS_L0);
635 } 752 }
636 753
637 *dma_ch_out = free_ch; 754 *dma_ch_out = free_ch;
638 755
639 return 0; 756 return 0;
640} 757}
758EXPORT_SYMBOL(omap_request_dma);
641 759
642void omap_free_dma(int lch) 760void omap_free_dma(int lch)
643{ 761{
@@ -645,11 +763,12 @@ void omap_free_dma(int lch)
645 763
646 spin_lock_irqsave(&dma_chan_lock, flags); 764 spin_lock_irqsave(&dma_chan_lock, flags);
647 if (dma_chan[lch].dev_id == -1) { 765 if (dma_chan[lch].dev_id == -1) {
648 printk("omap_dma: trying to free nonallocated DMA channel %d\n", 766 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
649 lch); 767 lch);
650 spin_unlock_irqrestore(&dma_chan_lock, flags); 768 spin_unlock_irqrestore(&dma_chan_lock, flags);
651 return; 769 return;
652 } 770 }
771
653 dma_chan[lch].dev_id = -1; 772 dma_chan[lch].dev_id = -1;
654 dma_chan[lch].next_lch = -1; 773 dma_chan[lch].next_lch = -1;
655 dma_chan[lch].callback = NULL; 774 dma_chan[lch].callback = NULL;
@@ -657,30 +776,31 @@ void omap_free_dma(int lch)
657 776
658 if (cpu_class_is_omap1()) { 777 if (cpu_class_is_omap1()) {
659 /* Disable all DMA interrupts for the channel. */ 778 /* Disable all DMA interrupts for the channel. */
660 OMAP_DMA_CICR_REG(lch) = 0; 779 dma_write(0, CICR(lch));
661 /* Make sure the DMA transfer is stopped. */ 780 /* Make sure the DMA transfer is stopped. */
662 OMAP_DMA_CCR_REG(lch) = 0; 781 dma_write(0, CCR(lch));
663 } 782 }
664 783
665 if (cpu_class_is_omap2()) { 784 if (cpu_class_is_omap2()) {
666 u32 val; 785 u32 val;
667 /* Disable interrupts */ 786 /* Disable interrupts */
668 val = omap_readl(OMAP_DMA4_IRQENABLE_L0); 787 val = dma_read(IRQENABLE_L0);
669 val &= ~(1 << lch); 788 val &= ~(1 << lch);
670 omap_writel(val, OMAP_DMA4_IRQENABLE_L0); 789 dma_write(val, IRQENABLE_L0);
671 790
672 /* Clear the CSR register and IRQ status register */ 791 /* Clear the CSR register and IRQ status register */
673 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK; 792 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
674 omap_writel(1 << lch, OMAP_DMA4_IRQSTATUS_L0); 793 dma_write(1 << lch, IRQSTATUS_L0);
675 794
676 /* Disable all DMA interrupts for the channel. */ 795 /* Disable all DMA interrupts for the channel. */
677 OMAP_DMA_CICR_REG(lch) = 0; 796 dma_write(0, CICR(lch));
678 797
679 /* Make sure the DMA transfer is stopped. */ 798 /* Make sure the DMA transfer is stopped. */
680 OMAP_DMA_CCR_REG(lch) = 0; 799 dma_write(0, CCR(lch));
681 omap_clear_dma(lch); 800 omap_clear_dma(lch);
682 } 801 }
683} 802}
803EXPORT_SYMBOL(omap_free_dma);
684 804
685/** 805/**
686 * @brief omap_dma_set_global_params : Set global priority settings for dma 806 * @brief omap_dma_set_global_params : Set global priority settings for dma
@@ -708,7 +828,7 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
708 reg = (arb_rate & 0xff) << 16; 828 reg = (arb_rate & 0xff) << 16;
709 reg |= (0xff & max_fifo_depth); 829 reg |= (0xff & max_fifo_depth);
710 830
711 omap_writel(reg, OMAP_DMA4_GCR_REG); 831 dma_write(reg, GCR);
712} 832}
713EXPORT_SYMBOL(omap_dma_set_global_params); 833EXPORT_SYMBOL(omap_dma_set_global_params);
714 834
@@ -725,20 +845,21 @@ int
725omap_dma_set_prio_lch(int lch, unsigned char read_prio, 845omap_dma_set_prio_lch(int lch, unsigned char read_prio,
726 unsigned char write_prio) 846 unsigned char write_prio)
727{ 847{
728 u32 w; 848 u32 l;
729 849
730 if (unlikely((lch < 0 || lch >= OMAP_LOGICAL_DMA_CH_COUNT))) { 850 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
731 printk(KERN_ERR "Invalid channel id\n"); 851 printk(KERN_ERR "Invalid channel id\n");
732 return -EINVAL; 852 return -EINVAL;
733 } 853 }
734 w = OMAP_DMA_CCR_REG(lch); 854 l = dma_read(CCR(lch));
735 w &= ~((1 << 6) | (1 << 26)); 855 l &= ~((1 << 6) | (1 << 26));
736 if (cpu_is_omap2430() || cpu_is_omap34xx()) 856 if (cpu_is_omap2430() || cpu_is_omap34xx())
737 w |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); 857 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
738 else 858 else
739 w |= ((read_prio & 0x1) << 6); 859 l |= ((read_prio & 0x1) << 6);
860
861 dma_write(l, CCR(lch));
740 862
741 OMAP_DMA_CCR_REG(lch) = w;
742 return 0; 863 return 0;
743} 864}
744EXPORT_SYMBOL(omap_dma_set_prio_lch); 865EXPORT_SYMBOL(omap_dma_set_prio_lch);
@@ -754,28 +875,34 @@ void omap_clear_dma(int lch)
754 local_irq_save(flags); 875 local_irq_save(flags);
755 876
756 if (cpu_class_is_omap1()) { 877 if (cpu_class_is_omap1()) {
757 int status; 878 u32 l;
758 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN; 879
880 l = dma_read(CCR(lch));
881 l &= ~OMAP_DMA_CCR_EN;
882 dma_write(l, CCR(lch));
759 883
760 /* Clear pending interrupts */ 884 /* Clear pending interrupts */
761 status = OMAP_DMA_CSR_REG(lch); 885 l = dma_read(CSR(lch));
762 } 886 }
763 887
764 if (cpu_class_is_omap2()) { 888 if (cpu_class_is_omap2()) {
765 int i; 889 int i;
766 u32 lch_base = OMAP_DMA4_BASE + lch * 0x60 + 0x80; 890 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
767 for (i = 0; i < 0x44; i += 4) 891 for (i = 0; i < 0x44; i += 4)
768 omap_writel(0, lch_base + i); 892 __raw_writel(0, lch_base + i);
769 } 893 }
770 894
771 local_irq_restore(flags); 895 local_irq_restore(flags);
772} 896}
897EXPORT_SYMBOL(omap_clear_dma);
773 898
774void omap_start_dma(int lch) 899void omap_start_dma(int lch)
775{ 900{
901 u32 l;
902
776 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { 903 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
777 int next_lch, cur_lch; 904 int next_lch, cur_lch;
778 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT]; 905 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
779 906
780 dma_chan_link_map[lch] = 1; 907 dma_chan_link_map[lch] = 1;
781 /* Set the link register of the first channel */ 908 /* Set the link register of the first channel */
@@ -799,27 +926,34 @@ void omap_start_dma(int lch)
799 } while (next_lch != -1); 926 } while (next_lch != -1);
800 } else if (cpu_class_is_omap2()) { 927 } else if (cpu_class_is_omap2()) {
801 /* Errata: Need to write lch even if not using chaining */ 928 /* Errata: Need to write lch even if not using chaining */
802 OMAP_DMA_CLNK_CTRL_REG(lch) = lch; 929 dma_write(lch, CLNK_CTRL(lch));
803 } 930 }
804 931
805 omap_enable_channel_irq(lch); 932 omap_enable_channel_irq(lch);
806 933
807 /* Errata: On ES2.0 BUFFERING disable must be set. 934 l = dma_read(CCR(lch));
808 * This will always fail on ES1.0 */ 935
809 if (cpu_is_omap24xx()) { 936 /*
810 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN; 937 * Errata: On ES2.0 BUFFERING disable must be set.
811 } 938 * This will always fail on ES1.0
939 */
940 if (cpu_is_omap24xx())
941 l |= OMAP_DMA_CCR_EN;
812 942
813 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN; 943 l |= OMAP_DMA_CCR_EN;
944 dma_write(l, CCR(lch));
814 945
815 dma_chan[lch].flags |= OMAP_DMA_ACTIVE; 946 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
816} 947}
948EXPORT_SYMBOL(omap_start_dma);
817 949
818void omap_stop_dma(int lch) 950void omap_stop_dma(int lch)
819{ 951{
952 u32 l;
953
820 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { 954 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
821 int next_lch, cur_lch = lch; 955 int next_lch, cur_lch = lch;
822 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT]; 956 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
823 957
824 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); 958 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
825 do { 959 do {
@@ -840,18 +974,22 @@ void omap_stop_dma(int lch)
840 974
841 /* Disable all interrupts on the channel */ 975 /* Disable all interrupts on the channel */
842 if (cpu_class_is_omap1()) 976 if (cpu_class_is_omap1())
843 OMAP_DMA_CICR_REG(lch) = 0; 977 dma_write(0, CICR(lch));
978
979 l = dma_read(CCR(lch));
980 l &= ~OMAP_DMA_CCR_EN;
981 dma_write(l, CCR(lch));
844 982
845 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
846 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; 983 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
847} 984}
985EXPORT_SYMBOL(omap_stop_dma);
848 986
849/* 987/*
850 * Allows changing the DMA callback function or data. This may be needed if 988 * Allows changing the DMA callback function or data. This may be needed if
851 * the driver shares a single DMA channel for multiple dma triggers. 989 * the driver shares a single DMA channel for multiple dma triggers.
852 */ 990 */
853int omap_set_dma_callback(int lch, 991int omap_set_dma_callback(int lch,
854 void (* callback)(int lch, u16 ch_status, void *data), 992 void (*callback)(int lch, u16 ch_status, void *data),
855 void *data) 993 void *data)
856{ 994{
857 unsigned long flags; 995 unsigned long flags;
@@ -871,6 +1009,7 @@ int omap_set_dma_callback(int lch,
871 1009
872 return 0; 1010 return 0;
873} 1011}
1012EXPORT_SYMBOL(omap_set_dma_callback);
874 1013
875/* 1014/*
876 * Returns current physical source address for the given DMA channel. 1015 * Returns current physical source address for the given DMA channel.
@@ -884,15 +1023,24 @@ dma_addr_t omap_get_dma_src_pos(int lch)
884{ 1023{
885 dma_addr_t offset = 0; 1024 dma_addr_t offset = 0;
886 1025
887 if (cpu_class_is_omap1()) 1026 if (cpu_is_omap15xx())
888 offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) | 1027 offset = dma_read(CPC(lch));
889 (OMAP1_DMA_CSSA_U_REG(lch) << 16)); 1028 else
1029 offset = dma_read(CSAC(lch));
890 1030
891 if (cpu_class_is_omap2()) 1031 /*
892 offset = OMAP_DMA_CSAC_REG(lch); 1032 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1033 * read before the DMA controller finished disabling the channel.
1034 */
1035 if (!cpu_is_omap15xx() && offset == 0)
1036 offset = dma_read(CSAC(lch));
1037
1038 if (cpu_class_is_omap1())
1039 offset |= (dma_read(CSSA_U(lch)) << 16);
893 1040
894 return offset; 1041 return offset;
895} 1042}
1043EXPORT_SYMBOL(omap_get_dma_src_pos);
896 1044
897/* 1045/*
898 * Returns current physical destination address for the given DMA channel. 1046 * Returns current physical destination address for the given DMA channel.
@@ -906,25 +1054,30 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
906{ 1054{
907 dma_addr_t offset = 0; 1055 dma_addr_t offset = 0;
908 1056
909 if (cpu_class_is_omap1()) 1057 if (cpu_is_omap15xx())
910 offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) | 1058 offset = dma_read(CPC(lch));
911 (OMAP1_DMA_CDSA_U_REG(lch) << 16)); 1059 else
1060 offset = dma_read(CDAC(lch));
912 1061
913 if (cpu_class_is_omap2()) 1062 /*
914 offset = OMAP_DMA_CDAC_REG(lch); 1063 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1064 * read before the DMA controller finished disabling the channel.
1065 */
1066 if (!cpu_is_omap15xx() && offset == 0)
1067 offset = dma_read(CDAC(lch));
1068
1069 if (cpu_class_is_omap1())
1070 offset |= (dma_read(CDSA_U(lch)) << 16);
915 1071
916 return offset; 1072 return offset;
917} 1073}
1074EXPORT_SYMBOL(omap_get_dma_dst_pos);
918 1075
919/* 1076int omap_get_dma_active_status(int lch)
920 * Returns current source transfer counting for the given DMA channel.
921 * Can be used to monitor the progress of a transfer inside a block.
922 * It must be called with disabled interrupts.
923 */
924int omap_get_dma_src_addr_counter(int lch)
925{ 1077{
926 return (dma_addr_t) OMAP_DMA_CSAC_REG(lch); 1078 return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
927} 1079}
1080EXPORT_SYMBOL(omap_get_dma_active_status);
928 1081
929int omap_dma_running(void) 1082int omap_dma_running(void)
930{ 1083{
@@ -936,7 +1089,7 @@ int omap_dma_running(void)
936 return 1; 1089 return 1;
937 1090
938 for (lch = 0; lch < dma_chan_count; lch++) 1091 for (lch = 0; lch < dma_chan_count; lch++)
939 if (OMAP_DMA_CCR_REG(lch) & OMAP_DMA_CCR_EN) 1092 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
940 return 1; 1093 return 1;
941 1094
942 return 0; 1095 return 0;
@@ -947,7 +1100,7 @@ int omap_dma_running(void)
947 * For this DMA link to start, you still need to start (see omap_start_dma) 1100 * For this DMA link to start, you still need to start (see omap_start_dma)
948 * the first one. That will fire up the entire queue. 1101 * the first one. That will fire up the entire queue.
949 */ 1102 */
950void omap_dma_link_lch (int lch_head, int lch_queue) 1103void omap_dma_link_lch(int lch_head, int lch_queue)
951{ 1104{
952 if (omap_dma_in_1510_mode()) { 1105 if (omap_dma_in_1510_mode()) {
953 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); 1106 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
@@ -964,11 +1117,12 @@ void omap_dma_link_lch (int lch_head, int lch_queue)
964 1117
965 dma_chan[lch_head].next_lch = lch_queue; 1118 dma_chan[lch_head].next_lch = lch_queue;
966} 1119}
1120EXPORT_SYMBOL(omap_dma_link_lch);
967 1121
968/* 1122/*
969 * Once the DMA queue is stopped, we can destroy it. 1123 * Once the DMA queue is stopped, we can destroy it.
970 */ 1124 */
971void omap_dma_unlink_lch (int lch_head, int lch_queue) 1125void omap_dma_unlink_lch(int lch_head, int lch_queue)
972{ 1126{
973 if (omap_dma_in_1510_mode()) { 1127 if (omap_dma_in_1510_mode()) {
974 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); 1128 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
@@ -983,7 +1137,6 @@ void omap_dma_unlink_lch (int lch_head, int lch_queue)
983 dump_stack(); 1137 dump_stack();
984 } 1138 }
985 1139
986
987 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) || 1140 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
988 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) { 1141 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
989 printk(KERN_ERR "omap_dma: You need to stop the DMA channels " 1142 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
@@ -993,12 +1146,15 @@ void omap_dma_unlink_lch (int lch_head, int lch_queue)
993 1146
994 dma_chan[lch_head].next_lch = -1; 1147 dma_chan[lch_head].next_lch = -1;
995} 1148}
1149EXPORT_SYMBOL(omap_dma_unlink_lch);
1150
1151/*----------------------------------------------------------------------------*/
996 1152
997#ifndef CONFIG_ARCH_OMAP1 1153#ifndef CONFIG_ARCH_OMAP1
998/* Create chain of DMA channesls */ 1154/* Create chain of DMA channesls */
999static void create_dma_lch_chain(int lch_head, int lch_queue) 1155static void create_dma_lch_chain(int lch_head, int lch_queue)
1000{ 1156{
1001 u32 w; 1157 u32 l;
1002 1158
1003 /* Check if this is the first link in chain */ 1159 /* Check if this is the first link in chain */
1004 if (dma_chan[lch_head].next_linked_ch == -1) { 1160 if (dma_chan[lch_head].next_linked_ch == -1) {
@@ -1018,15 +1174,15 @@ static void create_dma_lch_chain(int lch_head, int lch_queue)
1018 lch_queue; 1174 lch_queue;
1019 } 1175 }
1020 1176
1021 w = OMAP_DMA_CLNK_CTRL_REG(lch_head); 1177 l = dma_read(CLNK_CTRL(lch_head));
1022 w &= ~(0x1f); 1178 l &= ~(0x1f);
1023 w |= lch_queue; 1179 l |= lch_queue;
1024 OMAP_DMA_CLNK_CTRL_REG(lch_head) = w; 1180 dma_write(l, CLNK_CTRL(lch_head));
1025 1181
1026 w = OMAP_DMA_CLNK_CTRL_REG(lch_queue); 1182 l = dma_read(CLNK_CTRL(lch_queue));
1027 w &= ~(0x1f); 1183 l &= ~(0x1f);
1028 w |= (dma_chan[lch_queue].next_linked_ch); 1184 l |= (dma_chan[lch_queue].next_linked_ch);
1029 OMAP_DMA_CLNK_CTRL_REG(lch_queue) = w; 1185 dma_write(l, CLNK_CTRL(lch_queue));
1030} 1186}
1031 1187
1032/** 1188/**
@@ -1061,7 +1217,7 @@ int omap_request_dma_chain(int dev_id, const char *dev_name,
1061 } 1217 }
1062 1218
1063 if (unlikely((no_of_chans < 1 1219 if (unlikely((no_of_chans < 1
1064 || no_of_chans > OMAP_LOGICAL_DMA_CH_COUNT))) { 1220 || no_of_chans > dma_lch_count))) {
1065 printk(KERN_ERR "Invalid Number of channels requested\n"); 1221 printk(KERN_ERR "Invalid Number of channels requested\n");
1066 return -EINVAL; 1222 return -EINVAL;
1067 } 1223 }
@@ -1116,6 +1272,7 @@ int omap_request_dma_chain(int dev_id, const char *dev_name,
1116 for (i = 0; i < (no_of_chans - 1); i++) 1272 for (i = 0; i < (no_of_chans - 1); i++)
1117 create_dma_lch_chain(channels[i], channels[i + 1]); 1273 create_dma_lch_chain(channels[i], channels[i + 1]);
1118 } 1274 }
1275
1119 return 0; 1276 return 0;
1120} 1277}
1121EXPORT_SYMBOL(omap_request_dma_chain); 1278EXPORT_SYMBOL(omap_request_dma_chain);
@@ -1138,7 +1295,7 @@ int omap_modify_dma_chain_params(int chain_id,
1138 1295
1139 /* Check for input params */ 1296 /* Check for input params */
1140 if (unlikely((chain_id < 0 1297 if (unlikely((chain_id < 0
1141 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1298 || chain_id >= dma_lch_count))) {
1142 printk(KERN_ERR "Invalid chain id\n"); 1299 printk(KERN_ERR "Invalid chain id\n");
1143 return -EINVAL; 1300 return -EINVAL;
1144 } 1301 }
@@ -1158,6 +1315,7 @@ int omap_modify_dma_chain_params(int chain_id,
1158 */ 1315 */
1159 omap_set_dma_params(channels[i], &params); 1316 omap_set_dma_params(channels[i], &params);
1160 } 1317 }
1318
1161 return 0; 1319 return 0;
1162} 1320}
1163EXPORT_SYMBOL(omap_modify_dma_chain_params); 1321EXPORT_SYMBOL(omap_modify_dma_chain_params);
@@ -1176,7 +1334,7 @@ int omap_free_dma_chain(int chain_id)
1176 u32 i; 1334 u32 i;
1177 1335
1178 /* Check for input params */ 1336 /* Check for input params */
1179 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1337 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1180 printk(KERN_ERR "Invalid chain id\n"); 1338 printk(KERN_ERR "Invalid chain id\n");
1181 return -EINVAL; 1339 return -EINVAL;
1182 } 1340 }
@@ -1201,6 +1359,7 @@ int omap_free_dma_chain(int chain_id)
1201 dma_linked_lch[chain_id].linked_dmach_q = NULL; 1359 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1202 dma_linked_lch[chain_id].chain_mode = -1; 1360 dma_linked_lch[chain_id].chain_mode = -1;
1203 dma_linked_lch[chain_id].chain_state = -1; 1361 dma_linked_lch[chain_id].chain_state = -1;
1362
1204 return (0); 1363 return (0);
1205} 1364}
1206EXPORT_SYMBOL(omap_free_dma_chain); 1365EXPORT_SYMBOL(omap_free_dma_chain);
@@ -1216,7 +1375,7 @@ EXPORT_SYMBOL(omap_free_dma_chain);
1216int omap_dma_chain_status(int chain_id) 1375int omap_dma_chain_status(int chain_id)
1217{ 1376{
1218 /* Check for input params */ 1377 /* Check for input params */
1219 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1378 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1220 printk(KERN_ERR "Invalid chain id\n"); 1379 printk(KERN_ERR "Invalid chain id\n");
1221 return -EINVAL; 1380 return -EINVAL;
1222 } 1381 }
@@ -1231,6 +1390,7 @@ int omap_dma_chain_status(int chain_id)
1231 1390
1232 if (OMAP_DMA_CHAIN_QEMPTY(chain_id)) 1391 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1233 return OMAP_DMA_CHAIN_INACTIVE; 1392 return OMAP_DMA_CHAIN_INACTIVE;
1393
1234 return OMAP_DMA_CHAIN_ACTIVE; 1394 return OMAP_DMA_CHAIN_ACTIVE;
1235} 1395}
1236EXPORT_SYMBOL(omap_dma_chain_status); 1396EXPORT_SYMBOL(omap_dma_chain_status);
@@ -1253,11 +1413,13 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1253 int elem_count, int frame_count, void *callbk_data) 1413 int elem_count, int frame_count, void *callbk_data)
1254{ 1414{
1255 int *channels; 1415 int *channels;
1256 u32 w, lch; 1416 u32 l, lch;
1257 int start_dma = 0; 1417 int start_dma = 0;
1258 1418
1259 /* if buffer size is less than 1 then there is 1419 /*
1260 * no use of starting the chain */ 1420 * if buffer size is less than 1 then there is
1421 * no use of starting the chain
1422 */
1261 if (elem_count < 1) { 1423 if (elem_count < 1) {
1262 printk(KERN_ERR "Invalid buffer size\n"); 1424 printk(KERN_ERR "Invalid buffer size\n");
1263 return -EINVAL; 1425 return -EINVAL;
@@ -1265,7 +1427,7 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1265 1427
1266 /* Check for input params */ 1428 /* Check for input params */
1267 if (unlikely((chain_id < 0 1429 if (unlikely((chain_id < 0
1268 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1430 || chain_id >= dma_lch_count))) {
1269 printk(KERN_ERR "Invalid chain id\n"); 1431 printk(KERN_ERR "Invalid chain id\n");
1270 return -EINVAL; 1432 return -EINVAL;
1271 } 1433 }
@@ -1294,20 +1456,24 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1294 1456
1295 /* Set the params to the free channel */ 1457 /* Set the params to the free channel */
1296 if (src_start != 0) 1458 if (src_start != 0)
1297 OMAP2_DMA_CSSA_REG(lch) = src_start; 1459 dma_write(src_start, CSSA(lch));
1298 if (dest_start != 0) 1460 if (dest_start != 0)
1299 OMAP2_DMA_CDSA_REG(lch) = dest_start; 1461 dma_write(dest_start, CDSA(lch));
1300 1462
1301 /* Write the buffer size */ 1463 /* Write the buffer size */
1302 OMAP_DMA_CEN_REG(lch) = elem_count; 1464 dma_write(elem_count, CEN(lch));
1303 OMAP_DMA_CFN_REG(lch) = frame_count; 1465 dma_write(frame_count, CFN(lch));
1304 1466
1305 /* If the chain is dynamically linked, 1467 /*
1306 * then we may have to start the chain if its not active */ 1468 * If the chain is dynamically linked,
1469 * then we may have to start the chain if its not active
1470 */
1307 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) { 1471 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1308 1472
1309 /* In Dynamic chain, if the chain is not started, 1473 /*
1310 * queue the channel */ 1474 * In Dynamic chain, if the chain is not started,
1475 * queue the channel
1476 */
1311 if (dma_linked_lch[chain_id].chain_state == 1477 if (dma_linked_lch[chain_id].chain_state ==
1312 DMA_CHAIN_NOTSTARTED) { 1478 DMA_CHAIN_NOTSTARTED) {
1313 /* Enable the link in previous channel */ 1479 /* Enable the link in previous channel */
@@ -1317,8 +1483,10 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1317 dma_chan[lch].state = DMA_CH_QUEUED; 1483 dma_chan[lch].state = DMA_CH_QUEUED;
1318 } 1484 }
1319 1485
1320 /* Chain is already started, make sure its active, 1486 /*
1321 * if not then start the chain */ 1487 * Chain is already started, make sure its active,
1488 * if not then start the chain
1489 */
1322 else { 1490 else {
1323 start_dma = 1; 1491 start_dma = 1;
1324 1492
@@ -1327,8 +1495,8 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1327 enable_lnk(dma_chan[lch].prev_linked_ch); 1495 enable_lnk(dma_chan[lch].prev_linked_ch);
1328 dma_chan[lch].state = DMA_CH_QUEUED; 1496 dma_chan[lch].state = DMA_CH_QUEUED;
1329 start_dma = 0; 1497 start_dma = 0;
1330 if (0 == ((1 << 7) & (OMAP_DMA_CCR_REG 1498 if (0 == ((1 << 7) & dma_read(
1331 (dma_chan[lch].prev_linked_ch)))) { 1499 CCR(dma_chan[lch].prev_linked_ch)))) {
1332 disable_lnk(dma_chan[lch]. 1500 disable_lnk(dma_chan[lch].
1333 prev_linked_ch); 1501 prev_linked_ch);
1334 pr_debug("\n prev ch is stopped\n"); 1502 pr_debug("\n prev ch is stopped\n");
@@ -1344,27 +1512,28 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1344 } 1512 }
1345 omap_enable_channel_irq(lch); 1513 omap_enable_channel_irq(lch);
1346 1514
1347 w = OMAP_DMA_CCR_REG(lch); 1515 l = dma_read(CCR(lch));
1348 1516
1349 if ((0 == (w & (1 << 24)))) 1517 if ((0 == (l & (1 << 24))))
1350 w &= ~(1 << 25); 1518 l &= ~(1 << 25);
1351 else 1519 else
1352 w |= (1 << 25); 1520 l |= (1 << 25);
1353 if (start_dma == 1) { 1521 if (start_dma == 1) {
1354 if (0 == (w & (1 << 7))) { 1522 if (0 == (l & (1 << 7))) {
1355 w |= (1 << 7); 1523 l |= (1 << 7);
1356 dma_chan[lch].state = DMA_CH_STARTED; 1524 dma_chan[lch].state = DMA_CH_STARTED;
1357 pr_debug("starting %d\n", lch); 1525 pr_debug("starting %d\n", lch);
1358 OMAP_DMA_CCR_REG(lch) = w; 1526 dma_write(l, CCR(lch));
1359 } else 1527 } else
1360 start_dma = 0; 1528 start_dma = 0;
1361 } else { 1529 } else {
1362 if (0 == (w & (1 << 7))) 1530 if (0 == (l & (1 << 7)))
1363 OMAP_DMA_CCR_REG(lch) = w; 1531 dma_write(l, CCR(lch));
1364 } 1532 }
1365 dma_chan[lch].flags |= OMAP_DMA_ACTIVE; 1533 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1366 } 1534 }
1367 } 1535 }
1536
1368 return 0; 1537 return 0;
1369} 1538}
1370EXPORT_SYMBOL(omap_dma_chain_a_transfer); 1539EXPORT_SYMBOL(omap_dma_chain_a_transfer);
@@ -1380,9 +1549,9 @@ EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1380int omap_start_dma_chain_transfers(int chain_id) 1549int omap_start_dma_chain_transfers(int chain_id)
1381{ 1550{
1382 int *channels; 1551 int *channels;
1383 u32 w, i; 1552 u32 l, i;
1384 1553
1385 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1554 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1386 printk(KERN_ERR "Invalid chain id\n"); 1555 printk(KERN_ERR "Invalid chain id\n");
1387 return -EINVAL; 1556 return -EINVAL;
1388 } 1557 }
@@ -1404,18 +1573,19 @@ int omap_start_dma_chain_transfers(int chain_id)
1404 omap_enable_channel_irq(channels[0]); 1573 omap_enable_channel_irq(channels[0]);
1405 } 1574 }
1406 1575
1407 w = OMAP_DMA_CCR_REG(channels[0]); 1576 l = dma_read(CCR(channels[0]));
1408 w |= (1 << 7); 1577 l |= (1 << 7);
1409 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED; 1578 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1410 dma_chan[channels[0]].state = DMA_CH_STARTED; 1579 dma_chan[channels[0]].state = DMA_CH_STARTED;
1411 1580
1412 if ((0 == (w & (1 << 24)))) 1581 if ((0 == (l & (1 << 24))))
1413 w &= ~(1 << 25); 1582 l &= ~(1 << 25);
1414 else 1583 else
1415 w |= (1 << 25); 1584 l |= (1 << 25);
1416 OMAP_DMA_CCR_REG(channels[0]) = w; 1585 dma_write(l, CCR(channels[0]));
1417 1586
1418 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE; 1587 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1588
1419 return 0; 1589 return 0;
1420} 1590}
1421EXPORT_SYMBOL(omap_start_dma_chain_transfers); 1591EXPORT_SYMBOL(omap_start_dma_chain_transfers);
@@ -1431,11 +1601,11 @@ EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1431int omap_stop_dma_chain_transfers(int chain_id) 1601int omap_stop_dma_chain_transfers(int chain_id)
1432{ 1602{
1433 int *channels; 1603 int *channels;
1434 u32 w, i; 1604 u32 l, i;
1435 u32 sys_cf; 1605 u32 sys_cf;
1436 1606
1437 /* Check for input params */ 1607 /* Check for input params */
1438 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1608 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1439 printk(KERN_ERR "Invalid chain id\n"); 1609 printk(KERN_ERR "Invalid chain id\n");
1440 return -EINVAL; 1610 return -EINVAL;
1441 } 1611 }
@@ -1447,21 +1617,22 @@ int omap_stop_dma_chain_transfers(int chain_id)
1447 } 1617 }
1448 channels = dma_linked_lch[chain_id].linked_dmach_q; 1618 channels = dma_linked_lch[chain_id].linked_dmach_q;
1449 1619
1450 /* DMA Errata: 1620 /*
1621 * DMA Errata:
1451 * Special programming model needed to disable DMA before end of block 1622 * Special programming model needed to disable DMA before end of block
1452 */ 1623 */
1453 sys_cf = omap_readl(OMAP_DMA4_OCP_SYSCONFIG); 1624 sys_cf = dma_read(OCP_SYSCONFIG);
1454 w = sys_cf; 1625 l = sys_cf;
1455 /* Middle mode reg set no Standby */ 1626 /* Middle mode reg set no Standby */
1456 w &= ~((1 << 12)|(1 << 13)); 1627 l &= ~((1 << 12)|(1 << 13));
1457 omap_writel(w, OMAP_DMA4_OCP_SYSCONFIG); 1628 dma_write(l, OCP_SYSCONFIG);
1458 1629
1459 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { 1630 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1460 1631
1461 /* Stop the Channel transmission */ 1632 /* Stop the Channel transmission */
1462 w = OMAP_DMA_CCR_REG(channels[i]); 1633 l = dma_read(CCR(channels[i]));
1463 w &= ~(1 << 7); 1634 l &= ~(1 << 7);
1464 OMAP_DMA_CCR_REG(channels[i]) = w; 1635 dma_write(l, CCR(channels[i]));
1465 1636
1466 /* Disable the link in all the channels */ 1637 /* Disable the link in all the channels */
1467 disable_lnk(channels[i]); 1638 disable_lnk(channels[i]);
@@ -1474,7 +1645,8 @@ int omap_stop_dma_chain_transfers(int chain_id)
1474 OMAP_DMA_CHAIN_QINIT(chain_id); 1645 OMAP_DMA_CHAIN_QINIT(chain_id);
1475 1646
1476 /* Errata - put in the old value */ 1647 /* Errata - put in the old value */
1477 omap_writel(sys_cf, OMAP_DMA4_OCP_SYSCONFIG); 1648 dma_write(sys_cf, OCP_SYSCONFIG);
1649
1478 return 0; 1650 return 0;
1479} 1651}
1480EXPORT_SYMBOL(omap_stop_dma_chain_transfers); 1652EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
@@ -1497,7 +1669,7 @@ int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1497 int *channels; 1669 int *channels;
1498 1670
1499 /* Check for input params */ 1671 /* Check for input params */
1500 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1672 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1501 printk(KERN_ERR "Invalid chain id\n"); 1673 printk(KERN_ERR "Invalid chain id\n");
1502 return -EINVAL; 1674 return -EINVAL;
1503 } 1675 }
@@ -1515,8 +1687,8 @@ int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1515 /* Get the current channel */ 1687 /* Get the current channel */
1516 lch = channels[dma_linked_lch[chain_id].q_head]; 1688 lch = channels[dma_linked_lch[chain_id].q_head];
1517 1689
1518 *ei = OMAP2_DMA_CCEN_REG(lch); 1690 *ei = dma_read(CCEN(lch));
1519 *fi = OMAP2_DMA_CCFN_REG(lch); 1691 *fi = dma_read(CCFN(lch));
1520 1692
1521 return 0; 1693 return 0;
1522} 1694}
@@ -1537,7 +1709,7 @@ int omap_get_dma_chain_dst_pos(int chain_id)
1537 int *channels; 1709 int *channels;
1538 1710
1539 /* Check for input params */ 1711 /* Check for input params */
1540 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1712 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1541 printk(KERN_ERR "Invalid chain id\n"); 1713 printk(KERN_ERR "Invalid chain id\n");
1542 return -EINVAL; 1714 return -EINVAL;
1543 } 1715 }
@@ -1553,7 +1725,7 @@ int omap_get_dma_chain_dst_pos(int chain_id)
1553 /* Get the current channel */ 1725 /* Get the current channel */
1554 lch = channels[dma_linked_lch[chain_id].q_head]; 1726 lch = channels[dma_linked_lch[chain_id].q_head];
1555 1727
1556 return (OMAP_DMA_CDAC_REG(lch)); 1728 return dma_read(CDAC(lch));
1557} 1729}
1558EXPORT_SYMBOL(omap_get_dma_chain_dst_pos); 1730EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1559 1731
@@ -1571,7 +1743,7 @@ int omap_get_dma_chain_src_pos(int chain_id)
1571 int *channels; 1743 int *channels;
1572 1744
1573 /* Check for input params */ 1745 /* Check for input params */
1574 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1746 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1575 printk(KERN_ERR "Invalid chain id\n"); 1747 printk(KERN_ERR "Invalid chain id\n");
1576 return -EINVAL; 1748 return -EINVAL;
1577 } 1749 }
@@ -1587,10 +1759,10 @@ int omap_get_dma_chain_src_pos(int chain_id)
1587 /* Get the current channel */ 1759 /* Get the current channel */
1588 lch = channels[dma_linked_lch[chain_id].q_head]; 1760 lch = channels[dma_linked_lch[chain_id].q_head];
1589 1761
1590 return (OMAP_DMA_CSAC_REG(lch)); 1762 return dma_read(CSAC(lch));
1591} 1763}
1592EXPORT_SYMBOL(omap_get_dma_chain_src_pos); 1764EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1593#endif 1765#endif /* ifndef CONFIG_ARCH_OMAP1 */
1594 1766
1595/*----------------------------------------------------------------------------*/ 1767/*----------------------------------------------------------------------------*/
1596 1768
@@ -1598,13 +1770,13 @@ EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1598 1770
1599static int omap1_dma_handle_ch(int ch) 1771static int omap1_dma_handle_ch(int ch)
1600{ 1772{
1601 u16 csr; 1773 u32 csr;
1602 1774
1603 if (enable_1510_mode && ch >= 6) { 1775 if (enable_1510_mode && ch >= 6) {
1604 csr = dma_chan[ch].saved_csr; 1776 csr = dma_chan[ch].saved_csr;
1605 dma_chan[ch].saved_csr = 0; 1777 dma_chan[ch].saved_csr = 0;
1606 } else 1778 } else
1607 csr = OMAP_DMA_CSR_REG(ch); 1779 csr = dma_read(CSR(ch));
1608 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) { 1780 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1609 dma_chan[ch + 6].saved_csr = csr >> 7; 1781 dma_chan[ch + 6].saved_csr = csr >> 7;
1610 csr &= 0x7f; 1782 csr &= 0x7f;
@@ -1626,6 +1798,7 @@ static int omap1_dma_handle_ch(int ch)
1626 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; 1798 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1627 if (likely(dma_chan[ch].callback != NULL)) 1799 if (likely(dma_chan[ch].callback != NULL))
1628 dma_chan[ch].callback(ch, csr, dma_chan[ch].data); 1800 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1801
1629 return 1; 1802 return 1;
1630} 1803}
1631 1804
@@ -1656,12 +1829,13 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1656 1829
1657static int omap2_dma_handle_ch(int ch) 1830static int omap2_dma_handle_ch(int ch)
1658{ 1831{
1659 u32 status = OMAP_DMA_CSR_REG(ch); 1832 u32 status = dma_read(CSR(ch));
1660 1833
1661 if (!status) { 1834 if (!status) {
1662 if (printk_ratelimit()) 1835 if (printk_ratelimit())
1663 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", ch); 1836 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1664 omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0); 1837 ch);
1838 dma_write(1 << ch, IRQSTATUS_L0);
1665 return 0; 1839 return 0;
1666 } 1840 }
1667 if (unlikely(dma_chan[ch].dev_id == -1)) { 1841 if (unlikely(dma_chan[ch].dev_id == -1)) {
@@ -1684,14 +1858,14 @@ static int omap2_dma_handle_ch(int ch)
1684 printk(KERN_INFO "DMA misaligned error with device %d\n", 1858 printk(KERN_INFO "DMA misaligned error with device %d\n",
1685 dma_chan[ch].dev_id); 1859 dma_chan[ch].dev_id);
1686 1860
1687 OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK; 1861 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1688 omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0); 1862 dma_write(1 << ch, IRQSTATUS_L0);
1689 1863
1690 /* If the ch is not chained then chain_id will be -1 */ 1864 /* If the ch is not chained then chain_id will be -1 */
1691 if (dma_chan[ch].chain_id != -1) { 1865 if (dma_chan[ch].chain_id != -1) {
1692 int chain_id = dma_chan[ch].chain_id; 1866 int chain_id = dma_chan[ch].chain_id;
1693 dma_chan[ch].state = DMA_CH_NOTSTARTED; 1867 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1694 if (OMAP_DMA_CLNK_CTRL_REG(ch) & (1 << 15)) 1868 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1695 dma_chan[dma_chan[ch].next_linked_ch].state = 1869 dma_chan[dma_chan[ch].next_linked_ch].state =
1696 DMA_CH_STARTED; 1870 DMA_CH_STARTED;
1697 if (dma_linked_lch[chain_id].chain_mode == 1871 if (dma_linked_lch[chain_id].chain_mode ==
@@ -1701,13 +1875,13 @@ static int omap2_dma_handle_ch(int ch)
1701 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id)) 1875 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1702 OMAP_DMA_CHAIN_INCQHEAD(chain_id); 1876 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1703 1877
1704 status = OMAP_DMA_CSR_REG(ch); 1878 status = dma_read(CSR(ch));
1705 } 1879 }
1706 1880
1707 if (likely(dma_chan[ch].callback != NULL)) 1881 if (likely(dma_chan[ch].callback != NULL))
1708 dma_chan[ch].callback(ch, status, dma_chan[ch].data); 1882 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1709 1883
1710 OMAP_DMA_CSR_REG(ch) = status; 1884 dma_write(status, CSR(ch));
1711 1885
1712 return 0; 1886 return 0;
1713} 1887}
@@ -1718,13 +1892,13 @@ static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1718 u32 val; 1892 u32 val;
1719 int i; 1893 int i;
1720 1894
1721 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0); 1895 val = dma_read(IRQSTATUS_L0);
1722 if (val == 0) { 1896 if (val == 0) {
1723 if (printk_ratelimit()) 1897 if (printk_ratelimit())
1724 printk(KERN_WARNING "Spurious DMA IRQ\n"); 1898 printk(KERN_WARNING "Spurious DMA IRQ\n");
1725 return IRQ_HANDLED; 1899 return IRQ_HANDLED;
1726 } 1900 }
1727 for (i = 0; i < OMAP_LOGICAL_DMA_CH_COUNT && val != 0; i++) { 1901 for (i = 0; i < dma_lch_count && val != 0; i++) {
1728 if (val & 1) 1902 if (val & 1)
1729 omap2_dma_handle_ch(i); 1903 omap2_dma_handle_ch(i);
1730 val >>= 1; 1904 val >>= 1;
@@ -1748,7 +1922,7 @@ static struct irqaction omap24xx_dma_irq;
1748static struct lcd_dma_info { 1922static struct lcd_dma_info {
1749 spinlock_t lock; 1923 spinlock_t lock;
1750 int reserved; 1924 int reserved;
1751 void (* callback)(u16 status, void *data); 1925 void (*callback)(u16 status, void *data);
1752 void *cb_data; 1926 void *cb_data;
1753 1927
1754 int active; 1928 int active;
@@ -1770,6 +1944,7 @@ void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1770 lcd_dma.xres = fb_xres; 1944 lcd_dma.xres = fb_xres;
1771 lcd_dma.yres = fb_yres; 1945 lcd_dma.yres = fb_yres;
1772} 1946}
1947EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1773 1948
1774void omap_set_lcd_dma_src_port(int port) 1949void omap_set_lcd_dma_src_port(int port)
1775{ 1950{
@@ -1780,12 +1955,13 @@ void omap_set_lcd_dma_ext_controller(int external)
1780{ 1955{
1781 lcd_dma.ext_ctrl = external; 1956 lcd_dma.ext_ctrl = external;
1782} 1957}
1958EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
1783 1959
1784void omap_set_lcd_dma_single_transfer(int single) 1960void omap_set_lcd_dma_single_transfer(int single)
1785{ 1961{
1786 lcd_dma.single_transfer = single; 1962 lcd_dma.single_transfer = single;
1787} 1963}
1788 1964EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
1789 1965
1790void omap_set_lcd_dma_b1_rotation(int rotate) 1966void omap_set_lcd_dma_b1_rotation(int rotate)
1791{ 1967{
@@ -1796,6 +1972,7 @@ void omap_set_lcd_dma_b1_rotation(int rotate)
1796 } 1972 }
1797 lcd_dma.rotate = rotate; 1973 lcd_dma.rotate = rotate;
1798} 1974}
1975EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
1799 1976
1800void omap_set_lcd_dma_b1_mirror(int mirror) 1977void omap_set_lcd_dma_b1_mirror(int mirror)
1801{ 1978{
@@ -1805,6 +1982,7 @@ void omap_set_lcd_dma_b1_mirror(int mirror)
1805 } 1982 }
1806 lcd_dma.mirror = mirror; 1983 lcd_dma.mirror = mirror;
1807} 1984}
1985EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
1808 1986
1809void omap_set_lcd_dma_b1_vxres(unsigned long vxres) 1987void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
1810{ 1988{
@@ -1815,6 +1993,7 @@ void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
1815 } 1993 }
1816 lcd_dma.vxres = vxres; 1994 lcd_dma.vxres = vxres;
1817} 1995}
1996EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
1818 1997
1819void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale) 1998void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
1820{ 1999{
@@ -1825,6 +2004,7 @@ void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
1825 lcd_dma.xscale = xscale; 2004 lcd_dma.xscale = xscale;
1826 lcd_dma.yscale = yscale; 2005 lcd_dma.yscale = yscale;
1827} 2006}
2007EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
1828 2008
1829static void set_b1_regs(void) 2009static void set_b1_regs(void)
1830{ 2010{
@@ -1855,8 +2035,11 @@ static void set_b1_regs(void)
1855 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1; 2035 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
1856 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1; 2036 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
1857 BUG_ON(vxres < lcd_dma.xres); 2037 BUG_ON(vxres < lcd_dma.xres);
1858#define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * es) 2038
2039#define PIXADDR(x, y) (lcd_dma.addr + \
2040 ((y) * vxres * yscale + (x) * xscale) * es)
1859#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1) 2041#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2042
1860 switch (lcd_dma.rotate) { 2043 switch (lcd_dma.rotate) {
1861 case 0: 2044 case 0:
1862 if (!lcd_dma.mirror) { 2045 if (!lcd_dma.mirror) {
@@ -1865,8 +2048,8 @@ static void set_b1_regs(void)
1865 /* 1510 DMA requires the bottom address to be 2 more 2048 /* 1510 DMA requires the bottom address to be 2 more
1866 * than the actual last memory access location. */ 2049 * than the actual last memory access location. */
1867 if (omap_dma_in_1510_mode() && 2050 if (omap_dma_in_1510_mode() &&
1868 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32) 2051 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
1869 bottom += 2; 2052 bottom += 2;
1870 ei = PIXSTEP(0, 0, 1, 0); 2053 ei = PIXSTEP(0, 0, 1, 0);
1871 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1); 2054 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
1872 } else { 2055 } else {
@@ -1993,7 +2176,7 @@ static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
1993 return IRQ_HANDLED; 2176 return IRQ_HANDLED;
1994} 2177}
1995 2178
1996int omap_request_lcd_dma(void (* callback)(u16 status, void *data), 2179int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
1997 void *data) 2180 void *data)
1998{ 2181{
1999 spin_lock_irq(&lcd_dma.lock); 2182 spin_lock_irq(&lcd_dma.lock);
@@ -2019,6 +2202,7 @@ int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
2019 2202
2020 return 0; 2203 return 0;
2021} 2204}
2205EXPORT_SYMBOL(omap_request_lcd_dma);
2022 2206
2023void omap_free_lcd_dma(void) 2207void omap_free_lcd_dma(void)
2024{ 2208{
@@ -2035,12 +2219,14 @@ void omap_free_lcd_dma(void)
2035 lcd_dma.reserved = 0; 2219 lcd_dma.reserved = 0;
2036 spin_unlock(&lcd_dma.lock); 2220 spin_unlock(&lcd_dma.lock);
2037} 2221}
2222EXPORT_SYMBOL(omap_free_lcd_dma);
2038 2223
2039void omap_enable_lcd_dma(void) 2224void omap_enable_lcd_dma(void)
2040{ 2225{
2041 u16 w; 2226 u16 w;
2042 2227
2043 /* Set the Enable bit only if an external controller is 2228 /*
2229 * Set the Enable bit only if an external controller is
2044 * connected. Otherwise the OMAP internal controller will 2230 * connected. Otherwise the OMAP internal controller will
2045 * start the transfer when it gets enabled. 2231 * start the transfer when it gets enabled.
2046 */ 2232 */
@@ -2057,6 +2243,7 @@ void omap_enable_lcd_dma(void)
2057 w |= 1 << 7; 2243 w |= 1 << 7;
2058 omap_writew(w, OMAP1610_DMA_LCD_CCR); 2244 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2059} 2245}
2246EXPORT_SYMBOL(omap_enable_lcd_dma);
2060 2247
2061void omap_setup_lcd_dma(void) 2248void omap_setup_lcd_dma(void)
2062{ 2249{
@@ -2072,16 +2259,18 @@ void omap_setup_lcd_dma(void)
2072 u16 w; 2259 u16 w;
2073 2260
2074 w = omap_readw(OMAP1610_DMA_LCD_CCR); 2261 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2075 /* If DMA was already active set the end_prog bit to have 2262 /*
2263 * If DMA was already active set the end_prog bit to have
2076 * the programmed register set loaded into the active 2264 * the programmed register set loaded into the active
2077 * register set. 2265 * register set.
2078 */ 2266 */
2079 w |= 1 << 11; /* End_prog */ 2267 w |= 1 << 11; /* End_prog */
2080 if (!lcd_dma.single_transfer) 2268 if (!lcd_dma.single_transfer)
2081 w |= (3 << 8); /* Auto_init, repeat */ 2269 w |= (3 << 8); /* Auto_init, repeat */
2082 omap_writew(w, OMAP1610_DMA_LCD_CCR); 2270 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2083 } 2271 }
2084} 2272}
2273EXPORT_SYMBOL(omap_setup_lcd_dma);
2085 2274
2086void omap_stop_lcd_dma(void) 2275void omap_stop_lcd_dma(void)
2087{ 2276{
@@ -2099,6 +2288,7 @@ void omap_stop_lcd_dma(void)
2099 w &= ~(1 << 8); 2288 w &= ~(1 << 8);
2100 omap_writew(w, OMAP1610_DMA_LCD_CTRL); 2289 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2101} 2290}
2291EXPORT_SYMBOL(omap_stop_lcd_dma);
2102 2292
2103/*----------------------------------------------------------------------------*/ 2293/*----------------------------------------------------------------------------*/
2104 2294
@@ -2106,27 +2296,55 @@ static int __init omap_init_dma(void)
2106{ 2296{
2107 int ch, r; 2297 int ch, r;
2108 2298
2299 if (cpu_class_is_omap1()) {
2300 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP1_DMA_BASE);
2301 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2302 } else if (cpu_is_omap24xx()) {
2303 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP24XX_DMA4_BASE);
2304 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2305 } else if (cpu_is_omap34xx()) {
2306 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP34XX_DMA4_BASE);
2307 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2308 } else {
2309 pr_err("DMA init failed for unsupported omap\n");
2310 return -ENODEV;
2311 }
2312
2313 dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2314 GFP_KERNEL);
2315 if (!dma_chan)
2316 return -ENOMEM;
2317
2318 if (cpu_class_is_omap2()) {
2319 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2320 dma_lch_count, GFP_KERNEL);
2321 if (!dma_linked_lch) {
2322 kfree(dma_chan);
2323 return -ENOMEM;
2324 }
2325 }
2326
2109 if (cpu_is_omap15xx()) { 2327 if (cpu_is_omap15xx()) {
2110 printk(KERN_INFO "DMA support for OMAP15xx initialized\n"); 2328 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2111 dma_chan_count = 9; 2329 dma_chan_count = 9;
2112 enable_1510_mode = 1; 2330 enable_1510_mode = 1;
2113 } else if (cpu_is_omap16xx() || cpu_is_omap730()) { 2331 } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
2114 printk(KERN_INFO "OMAP DMA hardware version %d\n", 2332 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2115 omap_readw(OMAP_DMA_HW_ID)); 2333 dma_read(HW_ID));
2116 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n", 2334 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2117 (omap_readw(OMAP_DMA_CAPS_0_U) << 16) | 2335 (dma_read(CAPS_0_U) << 16) |
2118 omap_readw(OMAP_DMA_CAPS_0_L), 2336 dma_read(CAPS_0_L),
2119 (omap_readw(OMAP_DMA_CAPS_1_U) << 16) | 2337 (dma_read(CAPS_1_U) << 16) |
2120 omap_readw(OMAP_DMA_CAPS_1_L), 2338 dma_read(CAPS_1_L),
2121 omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3), 2339 dma_read(CAPS_2), dma_read(CAPS_3),
2122 omap_readw(OMAP_DMA_CAPS_4)); 2340 dma_read(CAPS_4));
2123 if (!enable_1510_mode) { 2341 if (!enable_1510_mode) {
2124 u16 w; 2342 u16 w;
2125 2343
2126 /* Disable OMAP 3.0/3.1 compatibility mode. */ 2344 /* Disable OMAP 3.0/3.1 compatibility mode. */
2127 w = omap_readw(OMAP_DMA_GSCR); 2345 w = dma_read(GSCR);
2128 w |= 1 << 3; 2346 w |= 1 << 3;
2129 omap_writew(w, OMAP_DMA_GSCR); 2347 dma_write(w, GSCR);
2130 dma_chan_count = 16; 2348 dma_chan_count = 16;
2131 } else 2349 } else
2132 dma_chan_count = 9; 2350 dma_chan_count = 9;
@@ -2139,19 +2357,17 @@ static int __init omap_init_dma(void)
2139 omap_writew(w, OMAP1610_DMA_LCD_CTRL); 2357 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2140 } 2358 }
2141 } else if (cpu_class_is_omap2()) { 2359 } else if (cpu_class_is_omap2()) {
2142 u8 revision = omap_readb(OMAP_DMA4_REVISION); 2360 u8 revision = dma_read(REVISION) & 0xff;
2143 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", 2361 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2144 revision >> 4, revision & 0xf); 2362 revision >> 4, revision & 0xf);
2145 dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT; 2363 dma_chan_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2146 } else { 2364 } else {
2147 dma_chan_count = 0; 2365 dma_chan_count = 0;
2148 return 0; 2366 return 0;
2149 } 2367 }
2150 2368
2151 memset(&lcd_dma, 0, sizeof(lcd_dma));
2152 spin_lock_init(&lcd_dma.lock); 2369 spin_lock_init(&lcd_dma.lock);
2153 spin_lock_init(&dma_chan_lock); 2370 spin_lock_init(&dma_chan_lock);
2154 memset(&dma_chan, 0, sizeof(dma_chan));
2155 2371
2156 for (ch = 0; ch < dma_chan_count; ch++) { 2372 for (ch = 0; ch < dma_chan_count; ch++) {
2157 omap_clear_dma(ch); 2373 omap_clear_dma(ch);
@@ -2162,8 +2378,10 @@ static int __init omap_init_dma(void)
2162 continue; 2378 continue;
2163 2379
2164 if (cpu_class_is_omap1()) { 2380 if (cpu_class_is_omap1()) {
2165 /* request_irq() doesn't like dev_id (ie. ch) being 2381 /*
2166 * zero, so we have to kludge around this. */ 2382 * request_irq() doesn't like dev_id (ie. ch) being
2383 * zero, so we have to kludge around this.
2384 */
2167 r = request_irq(omap1_dma_irq[ch], 2385 r = request_irq(omap1_dma_irq[ch],
2168 omap1_dma_irq_handler, 0, "DMA", 2386 omap1_dma_irq_handler, 0, "DMA",
2169 (void *) (ch + 1)); 2387 (void *) (ch + 1));
@@ -2208,48 +2426,4 @@ static int __init omap_init_dma(void)
2208 2426
2209arch_initcall(omap_init_dma); 2427arch_initcall(omap_init_dma);
2210 2428
2211EXPORT_SYMBOL(omap_get_dma_src_pos);
2212EXPORT_SYMBOL(omap_get_dma_dst_pos);
2213EXPORT_SYMBOL(omap_get_dma_src_addr_counter);
2214EXPORT_SYMBOL(omap_clear_dma);
2215EXPORT_SYMBOL(omap_set_dma_priority);
2216EXPORT_SYMBOL(omap_request_dma);
2217EXPORT_SYMBOL(omap_free_dma);
2218EXPORT_SYMBOL(omap_start_dma);
2219EXPORT_SYMBOL(omap_stop_dma);
2220EXPORT_SYMBOL(omap_set_dma_callback);
2221EXPORT_SYMBOL(omap_enable_dma_irq);
2222EXPORT_SYMBOL(omap_disable_dma_irq);
2223
2224EXPORT_SYMBOL(omap_set_dma_transfer_params);
2225EXPORT_SYMBOL(omap_set_dma_color_mode);
2226EXPORT_SYMBOL(omap_set_dma_write_mode);
2227
2228EXPORT_SYMBOL(omap_set_dma_src_params);
2229EXPORT_SYMBOL(omap_set_dma_src_index);
2230EXPORT_SYMBOL(omap_set_dma_src_data_pack);
2231EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
2232
2233EXPORT_SYMBOL(omap_set_dma_dest_params);
2234EXPORT_SYMBOL(omap_set_dma_dest_index);
2235EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
2236EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
2237
2238EXPORT_SYMBOL(omap_set_dma_params);
2239
2240EXPORT_SYMBOL(omap_dma_link_lch);
2241EXPORT_SYMBOL(omap_dma_unlink_lch);
2242
2243EXPORT_SYMBOL(omap_request_lcd_dma);
2244EXPORT_SYMBOL(omap_free_lcd_dma);
2245EXPORT_SYMBOL(omap_enable_lcd_dma);
2246EXPORT_SYMBOL(omap_setup_lcd_dma);
2247EXPORT_SYMBOL(omap_stop_lcd_dma);
2248EXPORT_SYMBOL(omap_set_lcd_dma_b1);
2249EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
2250EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
2251EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
2252EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2253EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2254EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
2255 2429
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 302ad8dff2cb..f22506af0e67 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -38,34 +38,113 @@
38#include <asm/arch/irqs.h> 38#include <asm/arch/irqs.h>
39 39
40/* register offsets */ 40/* register offsets */
41#define OMAP_TIMER_ID_REG 0x00 41#define _OMAP_TIMER_ID_OFFSET 0x00
42#define OMAP_TIMER_OCP_CFG_REG 0x10 42#define _OMAP_TIMER_OCP_CFG_OFFSET 0x10
43#define OMAP_TIMER_SYS_STAT_REG 0x14 43#define _OMAP_TIMER_SYS_STAT_OFFSET 0x14
44#define OMAP_TIMER_STAT_REG 0x18 44#define _OMAP_TIMER_STAT_OFFSET 0x18
45#define OMAP_TIMER_INT_EN_REG 0x1c 45#define _OMAP_TIMER_INT_EN_OFFSET 0x1c
46#define OMAP_TIMER_WAKEUP_EN_REG 0x20 46#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
47#define OMAP_TIMER_CTRL_REG 0x24 47#define _OMAP_TIMER_CTRL_OFFSET 0x24
48#define OMAP_TIMER_COUNTER_REG 0x28 48#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
49#define OMAP_TIMER_LOAD_REG 0x2c 49#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
50#define OMAP_TIMER_TRIGGER_REG 0x30 50#define OMAP_TIMER_CTRL_PT (1 << 12)
51#define OMAP_TIMER_WRITE_PEND_REG 0x34 51#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
52#define OMAP_TIMER_MATCH_REG 0x38 52#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
53#define OMAP_TIMER_CAPTURE_REG 0x3c 53#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
54#define OMAP_TIMER_IF_CTRL_REG 0x40 54#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
55 55#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
56/* timer control reg bits */ 56#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
57#define OMAP_TIMER_CTRL_GPOCFG (1 << 14) 57#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
58#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13) 58#define OMAP_TIMER_CTRL_POSTED (1 << 2)
59#define OMAP_TIMER_CTRL_PT (1 << 12) 59#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
60#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8) 60#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
61#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8) 61#define _OMAP_TIMER_COUNTER_OFFSET 0x28
62#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8) 62#define _OMAP_TIMER_LOAD_OFFSET 0x2c
63#define OMAP_TIMER_CTRL_SCPWM (1 << 7) 63#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
64#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */ 64#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
65#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */ 65#define WP_NONE 0 /* no write pending bit */
66#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* how much to shift the prescaler value */ 66#define WP_TCLR (1 << 0)
67#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */ 67#define WP_TCRR (1 << 1)
68#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */ 68#define WP_TLDR (1 << 2)
69#define WP_TTGR (1 << 3)
70#define WP_TMAR (1 << 4)
71#define WP_TPIR (1 << 5)
72#define WP_TNIR (1 << 6)
73#define WP_TCVR (1 << 7)
74#define WP_TOCR (1 << 8)
75#define WP_TOWR (1 << 9)
76#define _OMAP_TIMER_MATCH_OFFSET 0x38
77#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
78#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
79#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
80#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
81#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
82#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
83#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
84#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
85
86/* register offsets with the write pending bit encoded */
87#define WPSHIFT 16
88
89#define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
90 | (WP_NONE << WPSHIFT))
91
92#define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
93 | (WP_NONE << WPSHIFT))
94
95#define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
96 | (WP_NONE << WPSHIFT))
97
98#define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
99 | (WP_NONE << WPSHIFT))
100
101#define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
102 | (WP_NONE << WPSHIFT))
103
104#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
105 | (WP_NONE << WPSHIFT))
106
107#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
108 | (WP_TCLR << WPSHIFT))
109
110#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
111 | (WP_TCRR << WPSHIFT))
112
113#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
114 | (WP_TLDR << WPSHIFT))
115
116#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
117 | (WP_TTGR << WPSHIFT))
118
119#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
120 | (WP_NONE << WPSHIFT))
121
122#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
123 | (WP_TMAR << WPSHIFT))
124
125#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
126 | (WP_NONE << WPSHIFT))
127
128#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
129 | (WP_NONE << WPSHIFT))
130
131#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
132 | (WP_NONE << WPSHIFT))
133
134#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
135 | (WP_TPIR << WPSHIFT))
136
137#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
138 | (WP_TNIR << WPSHIFT))
139
140#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
141 | (WP_TCVR << WPSHIFT))
142
143#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
144 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
145
146#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
147 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
69 148
70struct omap_dm_timer { 149struct omap_dm_timer {
71 unsigned long phys_base; 150 unsigned long phys_base;
@@ -76,6 +155,7 @@ struct omap_dm_timer {
76 void __iomem *io_base; 155 void __iomem *io_base;
77 unsigned reserved:1; 156 unsigned reserved:1;
78 unsigned enabled:1; 157 unsigned enabled:1;
158 unsigned posted:1;
79}; 159};
80 160
81#ifdef CONFIG_ARCH_OMAP1 161#ifdef CONFIG_ARCH_OMAP1
@@ -181,16 +261,34 @@ static struct clk **dm_source_clocks;
181 261
182static spinlock_t dm_timer_lock; 262static spinlock_t dm_timer_lock;
183 263
184static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg) 264/*
265 * Reads timer registers in posted and non-posted mode. The posted mode bit
266 * is encoded in reg. Note that in posted mode write pending bit must be
267 * checked. Otherwise a read of a non completed write will produce an error.
268 */
269static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
185{ 270{
186 return readl(timer->io_base + reg); 271 if (timer->posted)
272 while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
273 & (reg >> WPSHIFT))
274 cpu_relax();
275 return readl(timer->io_base + (reg & 0xff));
187} 276}
188 277
189static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value) 278/*
279 * Writes timer registers in posted and non-posted mode. The posted mode bit
280 * is encoded in reg. Note that in posted mode the write pending bit must be
281 * checked. Otherwise a write on a register which has a pending write will be
282 * lost.
283 */
284static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
285 u32 value)
190{ 286{
191 writel(value, timer->io_base + reg); 287 if (timer->posted)
192 while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG)) 288 while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
193 ; 289 & (reg >> WPSHIFT))
290 cpu_relax();
291 writel(value, timer->io_base + (reg & 0xff));
194} 292}
195 293
196static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer) 294static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
@@ -217,17 +315,23 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
217 } 315 }
218 omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); 316 omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
219 317
220 /* Set to smart-idle mode */
221 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG); 318 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
222 l |= 0x02 << 3; 319 l |= 0x02 << 3; /* Set to smart-idle mode */
223 320 l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
224 if (cpu_class_is_omap2() && timer == &dm_timers[0]) { 321
225 /* Enable wake-up only for GPT1 on OMAP2 CPUs*/ 322 /*
323 * Enable wake-up only for GPT1 on OMAP2 CPUs.
324 * FIXME: All timers should have wake-up enabled and clear
325 * PRCM status.
326 */
327 if (cpu_class_is_omap2() && (timer == &dm_timers[0]))
226 l |= 1 << 2; 328 l |= 1 << 2;
227 /* Non-posted mode */
228 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0);
229 }
230 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l); 329 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
330
331 /* Match hardware reset default of posted mode */
332 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
333 OMAP_TIMER_CTRL_POSTED);
334 timer->posted = 1;
231} 335}
232 336
233static void omap_dm_timer_prepare(struct omap_dm_timer *timer) 337static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
@@ -434,9 +538,32 @@ void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
434 l &= ~OMAP_TIMER_CTRL_AR; 538 l &= ~OMAP_TIMER_CTRL_AR;
435 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 539 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
436 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); 540 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
541
542 /* REVISIT: hw feature, ttgr overtaking tldr? */
543 while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff)))
544 cpu_relax();
545
437 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); 546 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
438} 547}
439 548
549/* Optimized set_load which removes costly spin wait in timer_start */
550void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
551 unsigned int load)
552{
553 u32 l;
554
555 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
556 if (autoreload)
557 l |= OMAP_TIMER_CTRL_AR;
558 else
559 l &= ~OMAP_TIMER_CTRL_AR;
560 l |= OMAP_TIMER_CTRL_ST;
561
562 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load);
563 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
564 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
565}
566
440void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, 567void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
441 unsigned int match) 568 unsigned int match)
442{ 569{
@@ -451,7 +578,6 @@ void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
451 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); 578 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
452} 579}
453 580
454
455void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, 581void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
456 int toggle, int trigger) 582 int toggle, int trigger)
457{ 583{
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 6f33f58bca45..ff1413eae0b8 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -334,7 +334,7 @@ static int omap_mbox_init(struct omap_mbox *mbox)
334 } 334 }
335 335
336 mbox->dev.class = &omap_mbox_class; 336 mbox->dev.class = &omap_mbox_class;
337 strlcpy(mbox->dev.bus_id, mbox->name, KOBJ_NAME_LEN); 337 dev_set_name(&mbox->dev, "%s", mbox->name);
338 dev_set_drvdata(&mbox->dev, mbox); 338 dev_set_drvdata(&mbox->dev, mbox);
339 339
340 ret = device_register(&mbox->dev); 340 ret = device_register(&mbox->dev);
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 9cf83c4da9fa..c7f74064696c 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -15,95 +15,66 @@
15#include <linux/module.h> 15#include <linux/module.h>
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/device.h> 17#include <linux/device.h>
18#include <linux/platform_device.h>
18#include <linux/wait.h> 19#include <linux/wait.h>
19#include <linux/completion.h> 20#include <linux/completion.h>
20#include <linux/interrupt.h> 21#include <linux/interrupt.h>
21#include <linux/err.h> 22#include <linux/err.h>
22#include <linux/clk.h> 23#include <linux/clk.h>
23#include <linux/delay.h> 24#include <linux/delay.h>
24 25#include <linux/io.h>
25#include <asm/io.h>
26#include <asm/irq.h>
27 26
28#include <asm/arch/dma.h> 27#include <asm/arch/dma.h>
29#include <asm/arch/mux.h>
30#include <asm/arch/irqs.h>
31#include <asm/arch/dsp_common.h>
32#include <asm/arch/mcbsp.h> 28#include <asm/arch/mcbsp.h>
33 29
34#ifdef CONFIG_MCBSP_DEBUG
35#define DBG(x...) printk(x)
36#else
37#define DBG(x...) do { } while (0)
38#endif
39
40struct omap_mcbsp {
41 u32 io_base;
42 u8 id;
43 u8 free;
44 omap_mcbsp_word_length rx_word_length;
45 omap_mcbsp_word_length tx_word_length;
46
47 omap_mcbsp_io_type_t io_type; /* IRQ or poll */
48 /* IRQ based TX/RX */
49 int rx_irq;
50 int tx_irq;
51
52 /* DMA stuff */
53 u8 dma_rx_sync;
54 short dma_rx_lch;
55 u8 dma_tx_sync;
56 short dma_tx_lch;
57
58 /* Completion queues */
59 struct completion tx_irq_completion;
60 struct completion rx_irq_completion;
61 struct completion tx_dma_completion;
62 struct completion rx_dma_completion;
63
64 spinlock_t lock;
65};
66
67static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT]; 30static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
68#ifdef CONFIG_ARCH_OMAP1 31
69static struct clk *mcbsp_dsp_ck = 0; 32#define omap_mcbsp_check_valid_id(id) (mcbsp[id].pdata && \
70static struct clk *mcbsp_api_ck = 0; 33 mcbsp[id].pdata->ops && \
71static struct clk *mcbsp_dspxor_ck = 0; 34 mcbsp[id].pdata->ops->check && \
72#endif 35 (mcbsp[id].pdata->ops->check(id) == 0))
73#ifdef CONFIG_ARCH_OMAP2
74static struct clk *mcbsp1_ick = 0;
75static struct clk *mcbsp1_fck = 0;
76static struct clk *mcbsp2_ick = 0;
77static struct clk *mcbsp2_fck = 0;
78#endif
79 36
80static void omap_mcbsp_dump_reg(u8 id) 37static void omap_mcbsp_dump_reg(u8 id)
81{ 38{
82 DBG("**** MCBSP%d regs ****\n", mcbsp[id].id); 39 dev_dbg(mcbsp[id].dev, "**** McBSP%d regs ****\n", mcbsp[id].id);
83 DBG("DRR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2)); 40 dev_dbg(mcbsp[id].dev, "DRR2: 0x%04x\n",
84 DBG("DRR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1)); 41 OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
85 DBG("DXR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2)); 42 dev_dbg(mcbsp[id].dev, "DRR1: 0x%04x\n",
86 DBG("DXR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1)); 43 OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
87 DBG("SPCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2)); 44 dev_dbg(mcbsp[id].dev, "DXR2: 0x%04x\n",
88 DBG("SPCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1)); 45 OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
89 DBG("RCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2)); 46 dev_dbg(mcbsp[id].dev, "DXR1: 0x%04x\n",
90 DBG("RCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1)); 47 OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
91 DBG("XCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2)); 48 dev_dbg(mcbsp[id].dev, "SPCR2: 0x%04x\n",
92 DBG("XCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1)); 49 OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
93 DBG("SRGR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2)); 50 dev_dbg(mcbsp[id].dev, "SPCR1: 0x%04x\n",
94 DBG("SRGR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1)); 51 OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
95 DBG("PCR0: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0)); 52 dev_dbg(mcbsp[id].dev, "RCR2: 0x%04x\n",
96 DBG("***********************\n"); 53 OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
54 dev_dbg(mcbsp[id].dev, "RCR1: 0x%04x\n",
55 OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
56 dev_dbg(mcbsp[id].dev, "XCR2: 0x%04x\n",
57 OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
58 dev_dbg(mcbsp[id].dev, "XCR1: 0x%04x\n",
59 OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
60 dev_dbg(mcbsp[id].dev, "SRGR2: 0x%04x\n",
61 OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
62 dev_dbg(mcbsp[id].dev, "SRGR1: 0x%04x\n",
63 OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
64 dev_dbg(mcbsp[id].dev, "PCR0: 0x%04x\n",
65 OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
66 dev_dbg(mcbsp[id].dev, "***********************\n");
97} 67}
98 68
99static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id) 69static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
100{ 70{
101 struct omap_mcbsp *mcbsp_tx = dev_id; 71 struct omap_mcbsp *mcbsp_tx = dev_id;
102 72
103 DBG("TX IRQ callback : 0x%x\n", 73 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n",
104 OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2)); 74 OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
105 75
106 complete(&mcbsp_tx->tx_irq_completion); 76 complete(&mcbsp_tx->tx_irq_completion);
77
107 return IRQ_HANDLED; 78 return IRQ_HANDLED;
108} 79}
109 80
@@ -111,10 +82,11 @@ static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
111{ 82{
112 struct omap_mcbsp *mcbsp_rx = dev_id; 83 struct omap_mcbsp *mcbsp_rx = dev_id;
113 84
114 DBG("RX IRQ callback : 0x%x\n", 85 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n",
115 OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2)); 86 OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
116 87
117 complete(&mcbsp_rx->rx_irq_completion); 88 complete(&mcbsp_rx->rx_irq_completion);
89
118 return IRQ_HANDLED; 90 return IRQ_HANDLED;
119} 91}
120 92
@@ -122,8 +94,8 @@ static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
122{ 94{
123 struct omap_mcbsp *mcbsp_dma_tx = data; 95 struct omap_mcbsp *mcbsp_dma_tx = data;
124 96
125 DBG("TX DMA callback : 0x%x\n", 97 dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
126 OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2)); 98 OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
127 99
128 /* We can free the channels */ 100 /* We can free the channels */
129 omap_free_dma(mcbsp_dma_tx->dma_tx_lch); 101 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
@@ -136,8 +108,8 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
136{ 108{
137 struct omap_mcbsp *mcbsp_dma_rx = data; 109 struct omap_mcbsp *mcbsp_dma_rx = data;
138 110
139 DBG("RX DMA callback : 0x%x\n", 111 dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
140 OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2)); 112 OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
141 113
142 /* We can free the channels */ 114 /* We can free the channels */
143 omap_free_dma(mcbsp_dma_rx->dma_rx_lch); 115 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
@@ -146,19 +118,24 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
146 complete(&mcbsp_dma_rx->rx_dma_completion); 118 complete(&mcbsp_dma_rx->rx_dma_completion);
147} 119}
148 120
149
150/* 121/*
151 * omap_mcbsp_config simply write a config to the 122 * omap_mcbsp_config simply write a config to the
152 * appropriate McBSP. 123 * appropriate McBSP.
153 * You either call this function or set the McBSP registers 124 * You either call this function or set the McBSP registers
154 * by yourself before calling omap_mcbsp_start(). 125 * by yourself before calling omap_mcbsp_start().
155 */ 126 */
156 127void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
157void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config)
158{ 128{
159 u32 io_base = mcbsp[id].io_base; 129 u32 io_base;
130
131 if (!omap_mcbsp_check_valid_id(id)) {
132 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
133 return;
134 }
160 135
161 DBG("OMAP-McBSP: McBSP%d io_base: 0x%8x\n", id+1, io_base); 136 io_base = mcbsp[id].io_base;
137 dev_dbg(mcbsp[id].dev, "Configuring McBSP%d io_base: 0x%8x\n",
138 mcbsp[id].id, io_base);
162 139
163 /* We write the given config */ 140 /* We write the given config */
164 OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2); 141 OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
@@ -173,83 +150,7 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config
173 OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1); 150 OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
174 OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0); 151 OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
175} 152}
176 153EXPORT_SYMBOL(omap_mcbsp_config);
177
178
179static int omap_mcbsp_check(unsigned int id)
180{
181 if (cpu_is_omap730()) {
182 if (id > OMAP_MAX_MCBSP_COUNT - 1) {
183 printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
184 return -1;
185 }
186 return 0;
187 }
188
189 if (cpu_is_omap15xx() || cpu_is_omap16xx() || cpu_is_omap24xx()) {
190 if (id > OMAP_MAX_MCBSP_COUNT) {
191 printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
192 return -1;
193 }
194 return 0;
195 }
196
197 return -1;
198}
199
200#ifdef CONFIG_ARCH_OMAP1
201static void omap_mcbsp_dsp_request(void)
202{
203 if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
204 int ret;
205
206 ret = omap_dsp_request_mem();
207 if (ret < 0) {
208 printk(KERN_ERR "Could not get dsp memory: %i\n", ret);
209 return;
210 }
211
212 clk_enable(mcbsp_dsp_ck);
213 clk_enable(mcbsp_api_ck);
214
215 /* enable 12MHz clock to mcbsp 1 & 3 */
216 clk_enable(mcbsp_dspxor_ck);
217
218 /*
219 * DSP external peripheral reset
220 * FIXME: This should be moved to dsp code
221 */
222 __raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1,
223 DSP_RSTCT2);
224 }
225}
226
227static void omap_mcbsp_dsp_free(void)
228{
229 if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
230 omap_dsp_release_mem();
231 clk_disable(mcbsp_dspxor_ck);
232 clk_disable(mcbsp_dsp_ck);
233 clk_disable(mcbsp_api_ck);
234 }
235}
236#endif
237
238#ifdef CONFIG_ARCH_OMAP2
239static void omap2_mcbsp2_mux_setup(void)
240{
241 if (cpu_is_omap2420()) {
242 omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
243 omap_cfg_reg(R14_24XX_MCBSP2_FSX);
244 omap_cfg_reg(W15_24XX_MCBSP2_DR);
245 omap_cfg_reg(V15_24XX_MCBSP2_DX);
246 omap_cfg_reg(V14_24XX_GPIO117);
247 }
248 /*
249 * Need to add MUX settings for OMAP 2430 SDP
250 */
251}
252#endif
253 154
254/* 155/*
255 * We can choose between IRQ based or polled IO. 156 * We can choose between IRQ based or polled IO.
@@ -257,13 +158,16 @@ static void omap2_mcbsp2_mux_setup(void)
257 */ 158 */
258int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type) 159int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
259{ 160{
260 if (omap_mcbsp_check(id) < 0) 161 if (!omap_mcbsp_check_valid_id(id)) {
261 return -EINVAL; 162 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
163 return -ENODEV;
164 }
262 165
263 spin_lock(&mcbsp[id].lock); 166 spin_lock(&mcbsp[id].lock);
264 167
265 if (!mcbsp[id].free) { 168 if (!mcbsp[id].free) {
266 printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1); 169 dev_err(mcbsp[id].dev, "McBSP%d is currently in use\n",
170 mcbsp[id].id);
267 spin_unlock(&mcbsp[id].lock); 171 spin_unlock(&mcbsp[id].lock);
268 return -EINVAL; 172 return -EINVAL;
269 } 173 }
@@ -274,38 +178,26 @@ int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
274 178
275 return 0; 179 return 0;
276} 180}
181EXPORT_SYMBOL(omap_mcbsp_set_io_type);
277 182
278int omap_mcbsp_request(unsigned int id) 183int omap_mcbsp_request(unsigned int id)
279{ 184{
280 int err; 185 int err;
281 186
282 if (omap_mcbsp_check(id) < 0) 187 if (!omap_mcbsp_check_valid_id(id)) {
283 return -EINVAL; 188 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
284 189 return -ENODEV;
285#ifdef CONFIG_ARCH_OMAP1
286 /*
287 * On 1510, 1610 and 1710, McBSP1 and McBSP3
288 * are DSP public peripherals.
289 */
290 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
291 omap_mcbsp_dsp_request();
292#endif
293
294#ifdef CONFIG_ARCH_OMAP2
295 if (cpu_is_omap24xx()) {
296 if (id == OMAP_MCBSP1) {
297 clk_enable(mcbsp1_ick);
298 clk_enable(mcbsp1_fck);
299 } else {
300 clk_enable(mcbsp2_ick);
301 clk_enable(mcbsp2_fck);
302 }
303 } 190 }
304#endif 191
192 if (mcbsp[id].pdata->ops->request)
193 mcbsp[id].pdata->ops->request(id);
194
195 clk_enable(mcbsp[id].clk);
305 196
306 spin_lock(&mcbsp[id].lock); 197 spin_lock(&mcbsp[id].lock);
307 if (!mcbsp[id].free) { 198 if (!mcbsp[id].free) {
308 printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1); 199 dev_err(mcbsp[id].dev, "McBSP%d is currently in use\n",
200 mcbsp[id].id);
309 spin_unlock(&mcbsp[id].lock); 201 spin_unlock(&mcbsp[id].lock);
310 return -1; 202 return -1;
311 } 203 }
@@ -315,24 +207,23 @@ int omap_mcbsp_request(unsigned int id)
315 207
316 if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) { 208 if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
317 /* We need to get IRQs here */ 209 /* We need to get IRQs here */
318 err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler, 0, 210 err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler,
319 "McBSP", 211 0, "McBSP", (void *) (&mcbsp[id]));
320 (void *) (&mcbsp[id]));
321 if (err != 0) { 212 if (err != 0) {
322 printk(KERN_ERR "OMAP-McBSP: Unable to request TX IRQ %d for McBSP%d\n", 213 dev_err(mcbsp[id].dev, "Unable to request TX IRQ %d "
323 mcbsp[id].tx_irq, mcbsp[id].id); 214 "for McBSP%d\n", mcbsp[id].tx_irq,
215 mcbsp[id].id);
324 return err; 216 return err;
325 } 217 }
326 218
327 init_completion(&(mcbsp[id].tx_irq_completion)); 219 init_completion(&(mcbsp[id].tx_irq_completion));
328 220
329 221 err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler,
330 err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler, 0, 222 0, "McBSP", (void *) (&mcbsp[id]));
331 "McBSP",
332 (void *) (&mcbsp[id]));
333 if (err != 0) { 223 if (err != 0) {
334 printk(KERN_ERR "OMAP-McBSP: Unable to request RX IRQ %d for McBSP%d\n", 224 dev_err(mcbsp[id].dev, "Unable to request RX IRQ %d "
335 mcbsp[id].rx_irq, mcbsp[id].id); 225 "for McBSP%d\n", mcbsp[id].rx_irq,
226 mcbsp[id].id);
336 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id])); 227 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
337 return err; 228 return err;
338 } 229 }
@@ -341,36 +232,25 @@ int omap_mcbsp_request(unsigned int id)
341 } 232 }
342 233
343 return 0; 234 return 0;
344
345} 235}
236EXPORT_SYMBOL(omap_mcbsp_request);
346 237
347void omap_mcbsp_free(unsigned int id) 238void omap_mcbsp_free(unsigned int id)
348{ 239{
349 if (omap_mcbsp_check(id) < 0) 240 if (!omap_mcbsp_check_valid_id(id)) {
241 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
350 return; 242 return;
351
352#ifdef CONFIG_ARCH_OMAP1
353 if (cpu_class_is_omap1()) {
354 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
355 omap_mcbsp_dsp_free();
356 } 243 }
357#endif 244
358 245 if (mcbsp[id].pdata->ops->free)
359#ifdef CONFIG_ARCH_OMAP2 246 mcbsp[id].pdata->ops->free(id);
360 if (cpu_is_omap24xx()) { 247
361 if (id == OMAP_MCBSP1) { 248 clk_disable(mcbsp[id].clk);
362 clk_disable(mcbsp1_ick);
363 clk_disable(mcbsp1_fck);
364 } else {
365 clk_disable(mcbsp2_ick);
366 clk_disable(mcbsp2_fck);
367 }
368 }
369#endif
370 249
371 spin_lock(&mcbsp[id].lock); 250 spin_lock(&mcbsp[id].lock);
372 if (mcbsp[id].free) { 251 if (mcbsp[id].free) {
373 printk (KERN_ERR "OMAP-McBSP: McBSP%d was not reserved\n", id + 1); 252 dev_err(mcbsp[id].dev, "McBSP%d was not reserved\n",
253 mcbsp[id].id);
374 spin_unlock(&mcbsp[id].lock); 254 spin_unlock(&mcbsp[id].lock);
375 return; 255 return;
376 } 256 }
@@ -384,6 +264,7 @@ void omap_mcbsp_free(unsigned int id)
384 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id])); 264 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
385 } 265 }
386} 266}
267EXPORT_SYMBOL(omap_mcbsp_free);
387 268
388/* 269/*
389 * Here we start the McBSP, by enabling the sample 270 * Here we start the McBSP, by enabling the sample
@@ -395,13 +276,15 @@ void omap_mcbsp_start(unsigned int id)
395 u32 io_base; 276 u32 io_base;
396 u16 w; 277 u16 w;
397 278
398 if (omap_mcbsp_check(id) < 0) 279 if (!omap_mcbsp_check_valid_id(id)) {
280 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
399 return; 281 return;
282 }
400 283
401 io_base = mcbsp[id].io_base; 284 io_base = mcbsp[id].io_base;
402 285
403 mcbsp[id].rx_word_length = ((OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7); 286 mcbsp[id].rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
404 mcbsp[id].tx_word_length = ((OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7); 287 mcbsp[id].tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
405 288
406 /* Start the sample generator */ 289 /* Start the sample generator */
407 w = OMAP_MCBSP_READ(io_base, SPCR2); 290 w = OMAP_MCBSP_READ(io_base, SPCR2);
@@ -422,20 +305,22 @@ void omap_mcbsp_start(unsigned int id)
422 305
423 /* Dump McBSP Regs */ 306 /* Dump McBSP Regs */
424 omap_mcbsp_dump_reg(id); 307 omap_mcbsp_dump_reg(id);
425
426} 308}
309EXPORT_SYMBOL(omap_mcbsp_start);
427 310
428void omap_mcbsp_stop(unsigned int id) 311void omap_mcbsp_stop(unsigned int id)
429{ 312{
430 u32 io_base; 313 u32 io_base;
431 u16 w; 314 u16 w;
432 315
433 if (omap_mcbsp_check(id) < 0) 316 if (!omap_mcbsp_check_valid_id(id)) {
317 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
434 return; 318 return;
319 }
435 320
436 io_base = mcbsp[id].io_base; 321 io_base = mcbsp[id].io_base;
437 322
438 /* Reset transmitter */ 323 /* Reset transmitter */
439 w = OMAP_MCBSP_READ(io_base, SPCR2); 324 w = OMAP_MCBSP_READ(io_base, SPCR2);
440 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1)); 325 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1));
441 326
@@ -447,12 +332,19 @@ void omap_mcbsp_stop(unsigned int id)
447 w = OMAP_MCBSP_READ(io_base, SPCR2); 332 w = OMAP_MCBSP_READ(io_base, SPCR2);
448 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6)); 333 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
449} 334}
450 335EXPORT_SYMBOL(omap_mcbsp_stop);
451 336
452/* polled mcbsp i/o operations */ 337/* polled mcbsp i/o operations */
453int omap_mcbsp_pollwrite(unsigned int id, u16 buf) 338int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
454{ 339{
455 u32 base = mcbsp[id].io_base; 340 u32 base;
341
342 if (!omap_mcbsp_check_valid_id(id)) {
343 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
344 return -ENODEV;
345 }
346
347 base = mcbsp[id].io_base;
456 writew(buf, base + OMAP_MCBSP_REG_DXR1); 348 writew(buf, base + OMAP_MCBSP_REG_DXR1);
457 /* if frame sync error - clear the error */ 349 /* if frame sync error - clear the error */
458 if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) { 350 if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
@@ -474,18 +366,27 @@ int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
474 (XRST), 366 (XRST),
475 base + OMAP_MCBSP_REG_SPCR2); 367 base + OMAP_MCBSP_REG_SPCR2);
476 udelay(10); 368 udelay(10);
477 printk(KERN_ERR 369 dev_err(mcbsp[id].dev, "Could not write to"
478 " Could not write to McBSP Register\n"); 370 " McBSP%d Register\n", mcbsp[id].id);
479 return -2; 371 return -2;
480 } 372 }
481 } 373 }
482 } 374 }
375
483 return 0; 376 return 0;
484} 377}
378EXPORT_SYMBOL(omap_mcbsp_pollwrite);
485 379
486int omap_mcbsp_pollread(unsigned int id, u16 * buf) 380int omap_mcbsp_pollread(unsigned int id, u16 *buf)
487{ 381{
488 u32 base = mcbsp[id].io_base; 382 u32 base;
383
384 if (!omap_mcbsp_check_valid_id(id)) {
385 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
386 return -ENODEV;
387 }
388
389 base = mcbsp[id].io_base;
489 /* if frame sync error - clear the error */ 390 /* if frame sync error - clear the error */
490 if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) { 391 if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
491 /* clear error */ 392 /* clear error */
@@ -506,15 +407,17 @@ int omap_mcbsp_pollread(unsigned int id, u16 * buf)
506 (RRST), 407 (RRST),
507 base + OMAP_MCBSP_REG_SPCR1); 408 base + OMAP_MCBSP_REG_SPCR1);
508 udelay(10); 409 udelay(10);
509 printk(KERN_ERR 410 dev_err(mcbsp[id].dev, "Could not read from"
510 " Could not read from McBSP Register\n"); 411 " McBSP%d Register\n", mcbsp[id].id);
511 return -2; 412 return -2;
512 } 413 }
513 } 414 }
514 } 415 }
515 *buf = readw(base + OMAP_MCBSP_REG_DRR1); 416 *buf = readw(base + OMAP_MCBSP_REG_DRR1);
417
516 return 0; 418 return 0;
517} 419}
420EXPORT_SYMBOL(omap_mcbsp_pollread);
518 421
519/* 422/*
520 * IRQ based word transmission. 423 * IRQ based word transmission.
@@ -522,12 +425,15 @@ int omap_mcbsp_pollread(unsigned int id, u16 * buf)
522void omap_mcbsp_xmit_word(unsigned int id, u32 word) 425void omap_mcbsp_xmit_word(unsigned int id, u32 word)
523{ 426{
524 u32 io_base; 427 u32 io_base;
525 omap_mcbsp_word_length word_length = mcbsp[id].tx_word_length; 428 omap_mcbsp_word_length word_length;
526 429
527 if (omap_mcbsp_check(id) < 0) 430 if (!omap_mcbsp_check_valid_id(id)) {
431 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
528 return; 432 return;
433 }
529 434
530 io_base = mcbsp[id].io_base; 435 io_base = mcbsp[id].io_base;
436 word_length = mcbsp[id].tx_word_length;
531 437
532 wait_for_completion(&(mcbsp[id].tx_irq_completion)); 438 wait_for_completion(&(mcbsp[id].tx_irq_completion));
533 439
@@ -535,16 +441,20 @@ void omap_mcbsp_xmit_word(unsigned int id, u32 word)
535 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16); 441 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
536 OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff); 442 OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
537} 443}
444EXPORT_SYMBOL(omap_mcbsp_xmit_word);
538 445
539u32 omap_mcbsp_recv_word(unsigned int id) 446u32 omap_mcbsp_recv_word(unsigned int id)
540{ 447{
541 u32 io_base; 448 u32 io_base;
542 u16 word_lsb, word_msb = 0; 449 u16 word_lsb, word_msb = 0;
543 omap_mcbsp_word_length word_length = mcbsp[id].rx_word_length; 450 omap_mcbsp_word_length word_length;
544 451
545 if (omap_mcbsp_check(id) < 0) 452 if (!omap_mcbsp_check_valid_id(id)) {
546 return -EINVAL; 453 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
454 return -ENODEV;
455 }
547 456
457 word_length = mcbsp[id].rx_word_length;
548 io_base = mcbsp[id].io_base; 458 io_base = mcbsp[id].io_base;
549 459
550 wait_for_completion(&(mcbsp[id].rx_irq_completion)); 460 wait_for_completion(&(mcbsp[id].rx_irq_completion));
@@ -555,15 +465,24 @@ u32 omap_mcbsp_recv_word(unsigned int id)
555 465
556 return (word_lsb | (word_msb << 16)); 466 return (word_lsb | (word_msb << 16));
557} 467}
558 468EXPORT_SYMBOL(omap_mcbsp_recv_word);
559 469
560int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word) 470int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
561{ 471{
562 u32 io_base = mcbsp[id].io_base; 472 u32 io_base;
563 omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length; 473 omap_mcbsp_word_length tx_word_length;
564 omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length; 474 omap_mcbsp_word_length rx_word_length;
565 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0; 475 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
566 476
477 if (!omap_mcbsp_check_valid_id(id)) {
478 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
479 return -ENODEV;
480 }
481
482 io_base = mcbsp[id].io_base;
483 tx_word_length = mcbsp[id].tx_word_length;
484 rx_word_length = mcbsp[id].rx_word_length;
485
567 if (tx_word_length != rx_word_length) 486 if (tx_word_length != rx_word_length)
568 return -EINVAL; 487 return -EINVAL;
569 488
@@ -577,7 +496,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
577 udelay(10); 496 udelay(10);
578 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST); 497 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
579 udelay(10); 498 udelay(10);
580 printk("McBSP transmitter not ready\n"); 499 dev_err(mcbsp[id].dev, "McBSP%d transmitter not "
500 "ready\n", mcbsp[id].id);
581 return -EAGAIN; 501 return -EAGAIN;
582 } 502 }
583 } 503 }
@@ -597,7 +517,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
597 udelay(10); 517 udelay(10);
598 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST); 518 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
599 udelay(10); 519 udelay(10);
600 printk("McBSP receiver not ready\n"); 520 dev_err(mcbsp[id].dev, "McBSP%d receiver not "
521 "ready\n", mcbsp[id].id);
601 return -EAGAIN; 522 return -EAGAIN;
602 } 523 }
603 } 524 }
@@ -609,14 +530,24 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
609 530
610 return 0; 531 return 0;
611} 532}
533EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
612 534
613int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word) 535int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
614{ 536{
615 u32 io_base = mcbsp[id].io_base, clock_word = 0; 537 u32 io_base, clock_word = 0;
616 omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length; 538 omap_mcbsp_word_length tx_word_length;
617 omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length; 539 omap_mcbsp_word_length rx_word_length;
618 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0; 540 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
619 541
542 if (!omap_mcbsp_check_valid_id(id)) {
543 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
544 return -ENODEV;
545 }
546
547 io_base = mcbsp[id].io_base;
548 tx_word_length = mcbsp[id].tx_word_length;
549 rx_word_length = mcbsp[id].rx_word_length;
550
620 if (tx_word_length != rx_word_length) 551 if (tx_word_length != rx_word_length)
621 return -EINVAL; 552 return -EINVAL;
622 553
@@ -630,7 +561,8 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
630 udelay(10); 561 udelay(10);
631 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST); 562 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
632 udelay(10); 563 udelay(10);
633 printk("McBSP transmitter not ready\n"); 564 dev_err(mcbsp[id].dev, "McBSP%d transmitter not "
565 "ready\n", mcbsp[id].id);
634 return -EAGAIN; 566 return -EAGAIN;
635 } 567 }
636 } 568 }
@@ -650,7 +582,8 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
650 udelay(10); 582 udelay(10);
651 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST); 583 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
652 udelay(10); 584 udelay(10);
653 printk("McBSP receiver not ready\n"); 585 dev_err(mcbsp[id].dev, "McBSP%d receiver not "
586 "ready\n", mcbsp[id].id);
654 return -EAGAIN; 587 return -EAGAIN;
655 } 588 }
656 } 589 }
@@ -664,7 +597,7 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
664 597
665 return 0; 598 return 0;
666} 599}
667 600EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
668 601
669/* 602/*
670 * Simple DMA based buffer rx/tx routines. 603 * Simple DMA based buffer rx/tx routines.
@@ -673,25 +606,32 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
673 * For anything fancier, you should use your own customized DMA 606 * For anything fancier, you should use your own customized DMA
674 * routines and callbacks. 607 * routines and callbacks.
675 */ 608 */
676int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length) 609int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
610 unsigned int length)
677{ 611{
678 int dma_tx_ch; 612 int dma_tx_ch;
679 int src_port = 0; 613 int src_port = 0;
680 int dest_port = 0; 614 int dest_port = 0;
681 int sync_dev = 0; 615 int sync_dev = 0;
682 616
683 if (omap_mcbsp_check(id) < 0) 617 if (!omap_mcbsp_check_valid_id(id)) {
684 return -EINVAL; 618 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
619 return -ENODEV;
620 }
685 621
686 if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX", omap_mcbsp_tx_dma_callback, 622 if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX",
687 &mcbsp[id], 623 omap_mcbsp_tx_dma_callback,
688 &dma_tx_ch)) { 624 &mcbsp[id],
689 printk("OMAP-McBSP: Unable to request DMA channel for McBSP%d TX. Trying IRQ based TX\n", id+1); 625 &dma_tx_ch)) {
626 dev_err(mcbsp[id].dev, " Unable to request DMA channel for "
627 "McBSP%d TX. Trying IRQ based TX\n",
628 mcbsp[id].id);
690 return -EAGAIN; 629 return -EAGAIN;
691 } 630 }
692 mcbsp[id].dma_tx_lch = dma_tx_ch; 631 mcbsp[id].dma_tx_lch = dma_tx_ch;
693 632
694 DBG("TX DMA on channel %d\n", dma_tx_ch); 633 dev_err(mcbsp[id].dev, "McBSP%d TX DMA on channel %d\n", mcbsp[id].id,
634 dma_tx_ch);
695 635
696 init_completion(&(mcbsp[id].tx_dma_completion)); 636 init_completion(&(mcbsp[id].tx_dma_completion));
697 637
@@ -699,7 +639,7 @@ int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
699 src_port = OMAP_DMA_PORT_TIPB; 639 src_port = OMAP_DMA_PORT_TIPB;
700 dest_port = OMAP_DMA_PORT_EMIFF; 640 dest_port = OMAP_DMA_PORT_EMIFF;
701 } 641 }
702 if (cpu_is_omap24xx()) 642 if (cpu_class_is_omap2())
703 sync_dev = mcbsp[id].dma_tx_sync; 643 sync_dev = mcbsp[id].dma_tx_sync;
704 644
705 omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch, 645 omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
@@ -722,29 +662,37 @@ int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
722 662
723 omap_start_dma(mcbsp[id].dma_tx_lch); 663 omap_start_dma(mcbsp[id].dma_tx_lch);
724 wait_for_completion(&(mcbsp[id].tx_dma_completion)); 664 wait_for_completion(&(mcbsp[id].tx_dma_completion));
665
725 return 0; 666 return 0;
726} 667}
668EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
727 669
728 670int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
729int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length) 671 unsigned int length)
730{ 672{
731 int dma_rx_ch; 673 int dma_rx_ch;
732 int src_port = 0; 674 int src_port = 0;
733 int dest_port = 0; 675 int dest_port = 0;
734 int sync_dev = 0; 676 int sync_dev = 0;
735 677
736 if (omap_mcbsp_check(id) < 0) 678 if (!omap_mcbsp_check_valid_id(id)) {
737 return -EINVAL; 679 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
680 return -ENODEV;
681 }
738 682
739 if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX", omap_mcbsp_rx_dma_callback, 683 if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX",
740 &mcbsp[id], 684 omap_mcbsp_rx_dma_callback,
741 &dma_rx_ch)) { 685 &mcbsp[id],
742 printk("Unable to request DMA channel for McBSP%d RX. Trying IRQ based RX\n", id+1); 686 &dma_rx_ch)) {
687 dev_err(mcbsp[id].dev, "Unable to request DMA channel for "
688 "McBSP%d RX. Trying IRQ based RX\n",
689 mcbsp[id].id);
743 return -EAGAIN; 690 return -EAGAIN;
744 } 691 }
745 mcbsp[id].dma_rx_lch = dma_rx_ch; 692 mcbsp[id].dma_rx_lch = dma_rx_ch;
746 693
747 DBG("RX DMA on channel %d\n", dma_rx_ch); 694 dev_err(mcbsp[id].dev, "McBSP%d RX DMA on channel %d\n", mcbsp[id].id,
695 dma_rx_ch);
748 696
749 init_completion(&(mcbsp[id].rx_dma_completion)); 697 init_completion(&(mcbsp[id].rx_dma_completion));
750 698
@@ -752,14 +700,14 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
752 src_port = OMAP_DMA_PORT_TIPB; 700 src_port = OMAP_DMA_PORT_TIPB;
753 dest_port = OMAP_DMA_PORT_EMIFF; 701 dest_port = OMAP_DMA_PORT_EMIFF;
754 } 702 }
755 if (cpu_is_omap24xx()) 703 if (cpu_class_is_omap2())
756 sync_dev = mcbsp[id].dma_rx_sync; 704 sync_dev = mcbsp[id].dma_rx_sync;
757 705
758 omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch, 706 omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
759 OMAP_DMA_DATA_TYPE_S16, 707 OMAP_DMA_DATA_TYPE_S16,
760 length >> 1, 1, 708 length >> 1, 1,
761 OMAP_DMA_SYNC_ELEMENT, 709 OMAP_DMA_SYNC_ELEMENT,
762 sync_dev, 0); 710 sync_dev, 0);
763 711
764 omap_set_dma_src_params(mcbsp[id].dma_rx_lch, 712 omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
765 src_port, 713 src_port,
@@ -768,16 +716,17 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
768 0, 0); 716 0, 0);
769 717
770 omap_set_dma_dest_params(mcbsp[id].dma_rx_lch, 718 omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
771 dest_port, 719 dest_port,
772 OMAP_DMA_AMODE_POST_INC, 720 OMAP_DMA_AMODE_POST_INC,
773 buffer, 721 buffer,
774 0, 0); 722 0, 0);
775 723
776 omap_start_dma(mcbsp[id].dma_rx_lch); 724 omap_start_dma(mcbsp[id].dma_rx_lch);
777 wait_for_completion(&(mcbsp[id].rx_dma_completion)); 725 wait_for_completion(&(mcbsp[id].rx_dma_completion));
726
778 return 0; 727 return 0;
779} 728}
780 729EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
781 730
782/* 731/*
783 * SPI wrapper. 732 * SPI wrapper.
@@ -785,12 +734,15 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
785 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input. 734 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
786 * Once this is done, you can call omap_mcbsp_start(). 735 * Once this is done, you can call omap_mcbsp_start().
787 */ 736 */
788void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg) 737void omap_mcbsp_set_spi_mode(unsigned int id,
738 const struct omap_mcbsp_spi_cfg *spi_cfg)
789{ 739{
790 struct omap_mcbsp_reg_cfg mcbsp_cfg; 740 struct omap_mcbsp_reg_cfg mcbsp_cfg;
791 741
792 if (omap_mcbsp_check(id) < 0) 742 if (!omap_mcbsp_check_valid_id(id)) {
743 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
793 return; 744 return;
745 }
794 746
795 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg)); 747 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
796 748
@@ -798,7 +750,7 @@ void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg *
798 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0)); 750 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
799 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0)); 751 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
800 752
801 /* Clock stop mode */ 753 /* Clock stop mode */
802 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY) 754 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
803 mcbsp_cfg.spcr1 |= (1 << 12); 755 mcbsp_cfg.spcr1 |= (1 << 12);
804 else 756 else
@@ -827,13 +779,12 @@ void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg *
827 779
828 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) { 780 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
829 mcbsp_cfg.pcr0 |= CLKXM; 781 mcbsp_cfg.pcr0 |= CLKXM;
830 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div -1); 782 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
831 mcbsp_cfg.pcr0 |= FSXM; 783 mcbsp_cfg.pcr0 |= FSXM;
832 mcbsp_cfg.srgr2 &= ~FSGM; 784 mcbsp_cfg.srgr2 &= ~FSGM;
833 mcbsp_cfg.xcr2 |= XDATDLY(1); 785 mcbsp_cfg.xcr2 |= XDATDLY(1);
834 mcbsp_cfg.rcr2 |= RDATDLY(1); 786 mcbsp_cfg.rcr2 |= RDATDLY(1);
835 } 787 } else {
836 else {
837 mcbsp_cfg.pcr0 &= ~CLKXM; 788 mcbsp_cfg.pcr0 &= ~CLKXM;
838 mcbsp_cfg.srgr1 |= CLKGDV(1); 789 mcbsp_cfg.srgr1 |= CLKGDV(1);
839 mcbsp_cfg.pcr0 &= ~FSXM; 790 mcbsp_cfg.pcr0 &= ~FSXM;
@@ -846,199 +797,99 @@ void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg *
846 797
847 omap_mcbsp_config(id, &mcbsp_cfg); 798 omap_mcbsp_config(id, &mcbsp_cfg);
848} 799}
849 800EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
850 801
851/* 802/*
852 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510. 803 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
853 * 730 has only 2 McBSP, and both of them are MPU peripherals. 804 * 730 has only 2 McBSP, and both of them are MPU peripherals.
854 */ 805 */
855struct omap_mcbsp_info { 806static int __init omap_mcbsp_probe(struct platform_device *pdev)
856 u32 virt_base; 807{
857 u8 dma_rx_sync, dma_tx_sync; 808 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
858 u16 rx_irq, tx_irq; 809 int id = pdev->id - 1;
859}; 810 int ret = 0;
860 811
861#ifdef CONFIG_ARCH_OMAP730 812 if (!pdata) {
862static const struct omap_mcbsp_info mcbsp_730[] = { 813 dev_err(&pdev->dev, "McBSP device initialized without"
863 [0] = { .virt_base = io_p2v(OMAP730_MCBSP1_BASE), 814 "platform data\n");
864 .dma_rx_sync = OMAP_DMA_MCBSP1_RX, 815 ret = -EINVAL;
865 .dma_tx_sync = OMAP_DMA_MCBSP1_TX, 816 goto exit;
866 .rx_irq = INT_730_McBSP1RX, 817 }
867 .tx_irq = INT_730_McBSP1TX }, 818
868 [1] = { .virt_base = io_p2v(OMAP730_MCBSP2_BASE), 819 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
869 .dma_rx_sync = OMAP_DMA_MCBSP3_RX, 820
870 .dma_tx_sync = OMAP_DMA_MCBSP3_TX, 821 if (id >= OMAP_MAX_MCBSP_COUNT) {
871 .rx_irq = INT_730_McBSP2RX, 822 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
872 .tx_irq = INT_730_McBSP2TX }, 823 ret = -EINVAL;
873}; 824 goto exit;
874#endif 825 }
875 826
876#ifdef CONFIG_ARCH_OMAP15XX 827 spin_lock_init(&mcbsp[id].lock);
877static const struct omap_mcbsp_info mcbsp_1510[] = { 828 mcbsp[id].id = id + 1;
878 [0] = { .virt_base = OMAP1510_MCBSP1_BASE, 829 mcbsp[id].free = 1;
879 .dma_rx_sync = OMAP_DMA_MCBSP1_RX, 830 mcbsp[id].dma_tx_lch = -1;
880 .dma_tx_sync = OMAP_DMA_MCBSP1_TX, 831 mcbsp[id].dma_rx_lch = -1;
881 .rx_irq = INT_McBSP1RX, 832
882 .tx_irq = INT_McBSP1TX }, 833 mcbsp[id].io_base = pdata->virt_base;
883 [1] = { .virt_base = io_p2v(OMAP1510_MCBSP2_BASE), 834 /* Default I/O is IRQ based */
884 .dma_rx_sync = OMAP_DMA_MCBSP2_RX, 835 mcbsp[id].io_type = OMAP_MCBSP_IRQ_IO;
885 .dma_tx_sync = OMAP_DMA_MCBSP2_TX, 836 mcbsp[id].tx_irq = pdata->tx_irq;
886 .rx_irq = INT_1510_SPI_RX, 837 mcbsp[id].rx_irq = pdata->rx_irq;
887 .tx_irq = INT_1510_SPI_TX }, 838 mcbsp[id].dma_rx_sync = pdata->dma_rx_sync;
888 [2] = { .virt_base = OMAP1510_MCBSP3_BASE, 839 mcbsp[id].dma_tx_sync = pdata->dma_tx_sync;
889 .dma_rx_sync = OMAP_DMA_MCBSP3_RX, 840
890 .dma_tx_sync = OMAP_DMA_MCBSP3_TX, 841 if (pdata->clk_name)
891 .rx_irq = INT_McBSP3RX, 842 mcbsp[id].clk = clk_get(&pdev->dev, pdata->clk_name);
892 .tx_irq = INT_McBSP3TX }, 843 if (IS_ERR(mcbsp[id].clk)) {
893}; 844 mcbsp[id].free = 0;
894#endif 845 dev_err(&pdev->dev,
895 846 "Invalid clock configuration for McBSP%d.\n",
896#if defined(CONFIG_ARCH_OMAP16XX) 847 mcbsp[id].id);
897static const struct omap_mcbsp_info mcbsp_1610[] = { 848 ret = -EINVAL;
898 [0] = { .virt_base = OMAP1610_MCBSP1_BASE, 849 goto exit;
899 .dma_rx_sync = OMAP_DMA_MCBSP1_RX, 850 }
900 .dma_tx_sync = OMAP_DMA_MCBSP1_TX, 851
901 .rx_irq = INT_McBSP1RX, 852 mcbsp[id].pdata = pdata;
902 .tx_irq = INT_McBSP1TX }, 853 mcbsp[id].dev = &pdev->dev;
903 [1] = { .virt_base = io_p2v(OMAP1610_MCBSP2_BASE), 854 platform_set_drvdata(pdev, &mcbsp[id]);
904 .dma_rx_sync = OMAP_DMA_MCBSP2_RX, 855
905 .dma_tx_sync = OMAP_DMA_MCBSP2_TX, 856exit:
906 .rx_irq = INT_1610_McBSP2_RX, 857 return ret;
907 .tx_irq = INT_1610_McBSP2_TX }, 858}
908 [2] = { .virt_base = OMAP1610_MCBSP3_BASE,
909 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
910 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
911 .rx_irq = INT_McBSP3RX,
912 .tx_irq = INT_McBSP3TX },
913};
914#endif
915
916#if defined(CONFIG_ARCH_OMAP24XX)
917static const struct omap_mcbsp_info mcbsp_24xx[] = {
918 [0] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP1_BASE),
919 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
920 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
921 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
922 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
923 },
924 [1] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP2_BASE),
925 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
926 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
927 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
928 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
929 },
930};
931#endif
932 859
933static int __init omap_mcbsp_init(void) 860static int omap_mcbsp_remove(struct platform_device *pdev)
934{ 861{
935 int mcbsp_count = 0, i; 862 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
936 static const struct omap_mcbsp_info *mcbsp_info;
937 863
938 printk("Initializing OMAP McBSP system\n"); 864 platform_set_drvdata(pdev, NULL);
865 if (mcbsp) {
939 866
940#ifdef CONFIG_ARCH_OMAP1 867 if (mcbsp->pdata && mcbsp->pdata->ops &&
941 mcbsp_dsp_ck = clk_get(0, "dsp_ck"); 868 mcbsp->pdata->ops->free)
942 if (IS_ERR(mcbsp_dsp_ck)) { 869 mcbsp->pdata->ops->free(mcbsp->id);
943 printk(KERN_ERR "mcbsp: could not acquire dsp_ck handle.\n");
944 return PTR_ERR(mcbsp_dsp_ck);
945 }
946 mcbsp_api_ck = clk_get(0, "api_ck");
947 if (IS_ERR(mcbsp_api_ck)) {
948 printk(KERN_ERR "mcbsp: could not acquire api_ck handle.\n");
949 return PTR_ERR(mcbsp_api_ck);
950 }
951 mcbsp_dspxor_ck = clk_get(0, "dspxor_ck");
952 if (IS_ERR(mcbsp_dspxor_ck)) {
953 printk(KERN_ERR "mcbsp: could not acquire dspxor_ck handle.\n");
954 return PTR_ERR(mcbsp_dspxor_ck);
955 }
956#endif
957#ifdef CONFIG_ARCH_OMAP2
958 mcbsp1_ick = clk_get(0, "mcbsp1_ick");
959 if (IS_ERR(mcbsp1_ick)) {
960 printk(KERN_ERR "mcbsp: could not acquire mcbsp1_ick handle.\n");
961 return PTR_ERR(mcbsp1_ick);
962 }
963 mcbsp1_fck = clk_get(0, "mcbsp1_fck");
964 if (IS_ERR(mcbsp1_fck)) {
965 printk(KERN_ERR "mcbsp: could not acquire mcbsp1_fck handle.\n");
966 return PTR_ERR(mcbsp1_fck);
967 }
968 mcbsp2_ick = clk_get(0, "mcbsp2_ick");
969 if (IS_ERR(mcbsp2_ick)) {
970 printk(KERN_ERR "mcbsp: could not acquire mcbsp2_ick handle.\n");
971 return PTR_ERR(mcbsp2_ick);
972 }
973 mcbsp2_fck = clk_get(0, "mcbsp2_fck");
974 if (IS_ERR(mcbsp2_fck)) {
975 printk(KERN_ERR "mcbsp: could not acquire mcbsp2_fck handle.\n");
976 return PTR_ERR(mcbsp2_fck);
977 }
978#endif
979 870
980#ifdef CONFIG_ARCH_OMAP730 871 clk_disable(mcbsp->clk);
981 if (cpu_is_omap730()) { 872 clk_put(mcbsp->clk);
982 mcbsp_info = mcbsp_730; 873
983 mcbsp_count = ARRAY_SIZE(mcbsp_730); 874 mcbsp->clk = NULL;
984 } 875 mcbsp->free = 0;
985#endif 876 mcbsp->dev = NULL;
986#ifdef CONFIG_ARCH_OMAP15XX
987 if (cpu_is_omap15xx()) {
988 mcbsp_info = mcbsp_1510;
989 mcbsp_count = ARRAY_SIZE(mcbsp_1510);
990 }
991#endif
992#if defined(CONFIG_ARCH_OMAP16XX)
993 if (cpu_is_omap16xx()) {
994 mcbsp_info = mcbsp_1610;
995 mcbsp_count = ARRAY_SIZE(mcbsp_1610);
996 }
997#endif
998#if defined(CONFIG_ARCH_OMAP24XX)
999 if (cpu_is_omap24xx()) {
1000 mcbsp_info = mcbsp_24xx;
1001 mcbsp_count = ARRAY_SIZE(mcbsp_24xx);
1002 omap2_mcbsp2_mux_setup();
1003 }
1004#endif
1005 for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) {
1006 if (i >= mcbsp_count) {
1007 mcbsp[i].io_base = 0;
1008 mcbsp[i].free = 0;
1009 continue;
1010 }
1011 mcbsp[i].id = i + 1;
1012 mcbsp[i].free = 1;
1013 mcbsp[i].dma_tx_lch = -1;
1014 mcbsp[i].dma_rx_lch = -1;
1015
1016 mcbsp[i].io_base = mcbsp_info[i].virt_base;
1017 mcbsp[i].io_type = OMAP_MCBSP_IRQ_IO; /* Default I/O is IRQ based */
1018 mcbsp[i].tx_irq = mcbsp_info[i].tx_irq;
1019 mcbsp[i].rx_irq = mcbsp_info[i].rx_irq;
1020 mcbsp[i].dma_rx_sync = mcbsp_info[i].dma_rx_sync;
1021 mcbsp[i].dma_tx_sync = mcbsp_info[i].dma_tx_sync;
1022 spin_lock_init(&mcbsp[i].lock);
1023 } 877 }
1024 878
1025 return 0; 879 return 0;
1026} 880}
1027 881
1028arch_initcall(omap_mcbsp_init); 882static struct platform_driver omap_mcbsp_driver = {
883 .probe = omap_mcbsp_probe,
884 .remove = omap_mcbsp_remove,
885 .driver = {
886 .name = "omap-mcbsp",
887 },
888};
889
890int __init omap_mcbsp_init(void)
891{
892 /* Register the McBSP driver */
893 return platform_driver_register(&omap_mcbsp_driver);
894}
1029 895
1030EXPORT_SYMBOL(omap_mcbsp_config);
1031EXPORT_SYMBOL(omap_mcbsp_request);
1032EXPORT_SYMBOL(omap_mcbsp_set_io_type);
1033EXPORT_SYMBOL(omap_mcbsp_free);
1034EXPORT_SYMBOL(omap_mcbsp_start);
1035EXPORT_SYMBOL(omap_mcbsp_stop);
1036EXPORT_SYMBOL(omap_mcbsp_pollread);
1037EXPORT_SYMBOL(omap_mcbsp_pollwrite);
1038EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1039EXPORT_SYMBOL(omap_mcbsp_recv_word);
1040EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1041EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1042EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1043EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1044EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
diff --git a/arch/arm/plat-omap/sram-fn.S b/arch/arm/plat-omap/sram-fn.S
deleted file mode 100644
index 9e1813c77e05..000000000000
--- a/arch/arm/plat-omap/sram-fn.S
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * linux/arch/arm/plat-omap/sram-fn.S
3 *
4 * Functions that need to be run in internal SRAM
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/linkage.h>
12#include <asm/assembler.h>
13#include <asm/arch/io.h>
14#include <asm/hardware.h>
15
16 .text
17
18/*
19 * Reprograms ULPD and CKCTL.
20 */
21ENTRY(sram_reprogram_clock)
22 stmfd sp!, {r0 - r12, lr} @ save registers on stack
23
24 mov r2, #IO_ADDRESS(DPLL_CTL) & 0xff000000
25 orr r2, r2, #IO_ADDRESS(DPLL_CTL) & 0x00ff0000
26 orr r2, r2, #IO_ADDRESS(DPLL_CTL) & 0x0000ff00
27
28 mov r3, #IO_ADDRESS(ARM_CKCTL) & 0xff000000
29 orr r3, r3, #IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
30 orr r3, r3, #IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
31
32 tst r0, #1 << 4 @ want lock mode?
33 beq newck @ nope
34 bic r0, r0, #1 << 4 @ else clear lock bit
35 strh r0, [r2] @ set dpll into bypass mode
36 orr r0, r0, #1 << 4 @ set lock bit again
37
38newck:
39 strh r1, [r3] @ write new ckctl value
40 strh r0, [r2] @ write new dpll value
41
42 mov r4, #0x0700 @ let the clocks settle
43 orr r4, r4, #0x00ff
44delay: sub r4, r4, #1
45 cmp r4, #0
46 bne delay
47
48lock: ldrh r4, [r2], #0 @ read back dpll value
49 tst r0, #1 << 4 @ want lock mode?
50 beq out @ nope
51 tst r4, #1 << 0 @ dpll rate locked?
52 beq lock @ try again
53
54out:
55 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
56ENTRY(sram_reprogram_clock_sz)
57 .word . - sram_reprogram_clock
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 1f23f0459e5f..554ee58e1294 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -10,6 +10,7 @@
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13#undef DEBUG
13 14
14#include <linux/module.h> 15#include <linux/module.h>
15#include <linux/kernel.h> 16#include <linux/kernel.h>
@@ -24,25 +25,43 @@
24#include <asm/arch/sram.h> 25#include <asm/arch/sram.h>
25#include <asm/arch/board.h> 26#include <asm/arch/board.h>
26 27
28#include <asm/arch/control.h>
29
30#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
31# include "../mach-omap2/prm.h"
32# include "../mach-omap2/cm.h"
33# include "../mach-omap2/sdrc.h"
34#endif
35
27#define OMAP1_SRAM_PA 0x20000000 36#define OMAP1_SRAM_PA 0x20000000
28#define OMAP1_SRAM_VA 0xd0000000 37#define OMAP1_SRAM_VA VMALLOC_END
29#define OMAP2_SRAM_PA 0x40200000 38#define OMAP2_SRAM_PA 0x40200000
30#define OMAP2_SRAM_PUB_PA 0x4020f800 39#define OMAP2_SRAM_PUB_PA 0x4020f800
31#define OMAP2_SRAM_VA 0xd0000000 40#define OMAP2_SRAM_VA VMALLOC_END
32#define OMAP2_SRAM_PUB_VA 0xd0000800 41#define OMAP2_SRAM_PUB_VA (VMALLOC_END + 0x800)
33 42#define OMAP3_SRAM_PA 0x40200000
34#if defined(CONFIG_ARCH_OMAP24XX) 43#define OMAP3_SRAM_VA 0xd7000000
44#define OMAP3_SRAM_PUB_PA 0x40208000
45#define OMAP3_SRAM_PUB_VA 0xd7008000
46
47#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
35#define SRAM_BOOTLOADER_SZ 0x00 48#define SRAM_BOOTLOADER_SZ 0x00
36#else 49#else
37#define SRAM_BOOTLOADER_SZ 0x80 50#define SRAM_BOOTLOADER_SZ 0x80
38#endif 51#endif
39 52
40#define VA_REQINFOPERM0 IO_ADDRESS(0x68005048) 53#define OMAP24XX_VA_REQINFOPERM0 IO_ADDRESS(0x68005048)
41#define VA_READPERM0 IO_ADDRESS(0x68005050) 54#define OMAP24XX_VA_READPERM0 IO_ADDRESS(0x68005050)
42#define VA_WRITEPERM0 IO_ADDRESS(0x68005058) 55#define OMAP24XX_VA_WRITEPERM0 IO_ADDRESS(0x68005058)
43#define VA_CONTROL_STAT IO_ADDRESS(0x480002F8) 56
57#define OMAP34XX_VA_REQINFOPERM0 IO_ADDRESS(0x68012848)
58#define OMAP34XX_VA_READPERM0 IO_ADDRESS(0x68012850)
59#define OMAP34XX_VA_WRITEPERM0 IO_ADDRESS(0x68012858)
60#define OMAP34XX_VA_ADDR_MATCH2 IO_ADDRESS(0x68012880)
61#define OMAP34XX_VA_SMS_RG_ATT0 IO_ADDRESS(0x6C000048)
62#define OMAP34XX_VA_CONTROL_STAT IO_ADDRESS(0x480022F0)
63
44#define GP_DEVICE 0x300 64#define GP_DEVICE 0x300
45#define TYPE_MASK 0x700
46 65
47#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) 66#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
48 67
@@ -68,14 +87,21 @@ static int is_sram_locked(void)
68 int type = 0; 87 int type = 0;
69 88
70 if (cpu_is_omap242x()) 89 if (cpu_is_omap242x())
71 type = __raw_readl(VA_CONTROL_STAT) & TYPE_MASK; 90 type = system_rev & OMAP2_DEVICETYPE_MASK;
72 91
73 if (type == GP_DEVICE) { 92 if (type == GP_DEVICE) {
74 /* RAMFW: R/W access to all initiators for all qualifier sets */ 93 /* RAMFW: R/W access to all initiators for all qualifier sets */
75 if (cpu_is_omap242x()) { 94 if (cpu_is_omap242x()) {
76 __raw_writel(0xFF, VA_REQINFOPERM0); /* all q-vects */ 95 __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
77 __raw_writel(0xCFDE, VA_READPERM0); /* all i-read */ 96 __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
78 __raw_writel(0xCFDE, VA_WRITEPERM0); /* all i-write */ 97 __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
98 }
99 if (cpu_is_omap34xx()) {
100 __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
101 __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
102 __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
103 __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
104 __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
79 } 105 }
80 return 0; 106 return 0;
81 } else 107 } else
@@ -92,18 +118,30 @@ void __init omap_detect_sram(void)
92{ 118{
93 unsigned long reserved; 119 unsigned long reserved;
94 120
95 if (cpu_is_omap24xx()) { 121 if (cpu_class_is_omap2()) {
96 if (is_sram_locked()) { 122 if (is_sram_locked()) {
97 omap_sram_base = OMAP2_SRAM_PUB_VA; 123 if (cpu_is_omap34xx()) {
98 omap_sram_start = OMAP2_SRAM_PUB_PA; 124 omap_sram_base = OMAP3_SRAM_PUB_VA;
99 omap_sram_size = 0x800; /* 2K */ 125 omap_sram_start = OMAP3_SRAM_PUB_PA;
126 omap_sram_size = 0x8000; /* 32K */
127 } else {
128 omap_sram_base = OMAP2_SRAM_PUB_VA;
129 omap_sram_start = OMAP2_SRAM_PUB_PA;
130 omap_sram_size = 0x800; /* 2K */
131 }
100 } else { 132 } else {
101 omap_sram_base = OMAP2_SRAM_VA; 133 if (cpu_is_omap34xx()) {
102 omap_sram_start = OMAP2_SRAM_PA; 134 omap_sram_base = OMAP3_SRAM_VA;
103 if (cpu_is_omap242x()) 135 omap_sram_start = OMAP3_SRAM_PA;
104 omap_sram_size = 0xa0000; /* 640K */
105 else if (cpu_is_omap243x())
106 omap_sram_size = 0x10000; /* 64K */ 136 omap_sram_size = 0x10000; /* 64K */
137 } else {
138 omap_sram_base = OMAP2_SRAM_VA;
139 omap_sram_start = OMAP2_SRAM_PA;
140 if (cpu_is_omap242x())
141 omap_sram_size = 0xa0000; /* 640K */
142 else if (cpu_is_omap243x())
143 omap_sram_size = 0x10000; /* 64K */
144 }
107 } 145 }
108 } else { 146 } else {
109 omap_sram_base = OMAP1_SRAM_VA; 147 omap_sram_base = OMAP1_SRAM_VA;
@@ -157,6 +195,13 @@ void __init omap_map_sram(void)
157 omap_sram_io_desc[0].pfn = __phys_to_pfn(base); 195 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
158 } 196 }
159 197
198 if (cpu_is_omap34xx()) {
199 omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
200 base = OMAP3_SRAM_PA;
201 base = ROUND_DOWN(base, PAGE_SIZE);
202 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
203 }
204
160 omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */ 205 omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */
161 iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc)); 206 iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
162 207
@@ -191,6 +236,7 @@ void * omap_sram_push(void * start, unsigned long size)
191 omap_sram_ceil -= size; 236 omap_sram_ceil -= size;
192 omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *)); 237 omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
193 memcpy((void *)omap_sram_ceil, start, size); 238 memcpy((void *)omap_sram_ceil, start, size);
239 flush_icache_range((unsigned long)start, (unsigned long)(start + size));
194 240
195 return (void *)omap_sram_ceil; 241 return (void *)omap_sram_ceil;
196} 242}
@@ -214,8 +260,9 @@ void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
214 260
215int __init omap1_sram_init(void) 261int __init omap1_sram_init(void)
216{ 262{
217 _omap_sram_reprogram_clock = omap_sram_push(sram_reprogram_clock, 263 _omap_sram_reprogram_clock =
218 sram_reprogram_clock_sz); 264 omap_sram_push(omap1_sram_reprogram_clock,
265 omap1_sram_reprogram_clock_sz);
219 266
220 return 0; 267 return 0;
221} 268}
@@ -224,7 +271,7 @@ int __init omap1_sram_init(void)
224#define omap1_sram_init() do {} while (0) 271#define omap1_sram_init() do {} while (0)
225#endif 272#endif
226 273
227#ifdef CONFIG_ARCH_OMAP2 274#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
228 275
229static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 276static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
230 u32 base_cs, u32 force_unlock); 277 u32 base_cs, u32 force_unlock);
@@ -259,19 +306,109 @@ u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
259 306
260 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass); 307 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
261} 308}
309#endif
310
311#ifdef CONFIG_ARCH_OMAP2420
312int __init omap242x_sram_init(void)
313{
314 _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
315 omap242x_sram_ddr_init_sz);
316
317 _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
318 omap242x_sram_reprogram_sdrc_sz);
319
320 _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
321 omap242x_sram_set_prcm_sz);
322
323 return 0;
324}
325#else
326static inline int omap242x_sram_init(void)
327{
328 return 0;
329}
330#endif
331
332#ifdef CONFIG_ARCH_OMAP2430
333int __init omap243x_sram_init(void)
334{
335 _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
336 omap243x_sram_ddr_init_sz);
337
338 _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
339 omap243x_sram_reprogram_sdrc_sz);
340
341 _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
342 omap243x_sram_set_prcm_sz);
343
344 return 0;
345}
346#else
347static inline int omap243x_sram_init(void)
348{
349 return 0;
350}
351#endif
352
353#ifdef CONFIG_ARCH_OMAP3
354
355static u32 (*_omap2_sram_reprogram_gpmc)(u32 perf_level);
356u32 omap2_sram_reprogram_gpmc(u32 perf_level)
357{
358 if (!_omap2_sram_reprogram_gpmc)
359 omap_sram_error();
360
361 return _omap2_sram_reprogram_gpmc(perf_level);
362}
363
364static u32 (*_omap2_sram_configure_core_dpll)(u32 m, u32 n,
365 u32 freqsel, u32 m2);
366u32 omap2_sram_configure_core_dpll(u32 m, u32 n, u32 freqsel, u32 m2)
367{
368 if (!_omap2_sram_configure_core_dpll)
369 omap_sram_error();
370
371 return _omap2_sram_configure_core_dpll(m, n, freqsel, m2);
372}
262 373
263int __init omap2_sram_init(void) 374/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
375void restore_sram_functions(void)
264{ 376{
265 _omap2_sram_ddr_init = omap_sram_push(sram_ddr_init, sram_ddr_init_sz); 377 omap_sram_ceil = omap_sram_base + omap_sram_size;
266 378
267 _omap2_sram_reprogram_sdrc = omap_sram_push(sram_reprogram_sdrc, 379 _omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
268 sram_reprogram_sdrc_sz); 380 omap34xx_sram_reprogram_gpmc_sz);
269 _omap2_set_prcm = omap_sram_push(sram_set_prcm, sram_set_prcm_sz); 381
382 _omap2_sram_configure_core_dpll =
383 omap_sram_push(omap34xx_sram_configure_core_dpll,
384 omap34xx_sram_configure_core_dpll_sz);
385}
386
387int __init omap34xx_sram_init(void)
388{
389 _omap2_sram_ddr_init = omap_sram_push(omap34xx_sram_ddr_init,
390 omap34xx_sram_ddr_init_sz);
391
392 _omap2_sram_reprogram_sdrc = omap_sram_push(omap34xx_sram_reprogram_sdrc,
393 omap34xx_sram_reprogram_sdrc_sz);
394
395 _omap2_set_prcm = omap_sram_push(omap34xx_sram_set_prcm,
396 omap34xx_sram_set_prcm_sz);
397
398 _omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
399 omap34xx_sram_reprogram_gpmc_sz);
400
401 _omap2_sram_configure_core_dpll =
402 omap_sram_push(omap34xx_sram_configure_core_dpll,
403 omap34xx_sram_configure_core_dpll_sz);
270 404
271 return 0; 405 return 0;
272} 406}
273#else 407#else
274#define omap2_sram_init() do {} while (0) 408static inline int omap34xx_sram_init(void)
409{
410 return 0;
411}
275#endif 412#endif
276 413
277int __init omap_sram_init(void) 414int __init omap_sram_init(void)
@@ -279,10 +416,14 @@ int __init omap_sram_init(void)
279 omap_detect_sram(); 416 omap_detect_sram();
280 omap_map_sram(); 417 omap_map_sram();
281 418
282 if (!cpu_is_omap24xx()) 419 if (!(cpu_class_is_omap2()))
283 omap1_sram_init(); 420 omap1_sram_init();
284 else 421 else if (cpu_is_omap242x())
285 omap2_sram_init(); 422 omap242x_sram_init();
423 else if (cpu_is_omap2430())
424 omap243x_sram_init();
425 else if (cpu_is_omap34xx())
426 omap34xx_sram_init();
286 427
287 return 0; 428 return 0;
288} 429}
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index a619475c4b76..2699c16d4da0 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -1,4 +1,4 @@
1/* 1 /*
2 * arch/arm/plat-omap/usb.c -- platform level USB initialization 2 * arch/arm/plat-omap/usb.c -- platform level USB initialization
3 * 3 *
4 * Copyright (C) 2004 Texas Instruments, Inc. 4 * Copyright (C) 2004 Texas Instruments, Inc.
@@ -156,8 +156,12 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
156 156
157 if (nwires == 0) { 157 if (nwires == 0) {
158 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) { 158 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
159 u32 l;
160
159 /* pulldown D+/D- */ 161 /* pulldown D+/D- */
160 USB_TRANSCEIVER_CTRL_REG &= ~(3 << 1); 162 l = omap_readl(USB_TRANSCEIVER_CTRL);
163 l &= ~(3 << 1);
164 omap_writel(l, USB_TRANSCEIVER_CTRL);
161 } 165 }
162 return 0; 166 return 0;
163 } 167 }
@@ -171,6 +175,8 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
171 175
172 /* internal transceiver (unavailable on 17xx, 24xx) */ 176 /* internal transceiver (unavailable on 17xx, 24xx) */
173 if (!cpu_class_is_omap2() && nwires == 2) { 177 if (!cpu_class_is_omap2() && nwires == 2) {
178 u32 l;
179
174 // omap_cfg_reg(P9_USB_DP); 180 // omap_cfg_reg(P9_USB_DP);
175 // omap_cfg_reg(R8_USB_DM); 181 // omap_cfg_reg(R8_USB_DM);
176 182
@@ -185,9 +191,11 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
185 * - OTG support on this port not yet written 191 * - OTG support on this port not yet written
186 */ 192 */
187 193
188 USB_TRANSCEIVER_CTRL_REG &= ~(7 << 4); 194 l = omap_readl(USB_TRANSCEIVER_CTRL);
195 l &= ~(7 << 4);
189 if (!is_device) 196 if (!is_device)
190 USB_TRANSCEIVER_CTRL_REG |= (3 << 1); 197 l |= (3 << 1);
198 omap_writel(l, USB_TRANSCEIVER_CTRL);
191 199
192 return 3 << 16; 200 return 3 << 16;
193 } 201 }
@@ -217,8 +225,13 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
217 * with VBUS switching and overcurrent detection. 225 * with VBUS switching and overcurrent detection.
218 */ 226 */
219 227
220 if (cpu_class_is_omap1() && nwires != 6) 228 if (cpu_class_is_omap1() && nwires != 6) {
221 USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB2_UNI_R; 229 u32 l;
230
231 l = omap_readl(USB_TRANSCEIVER_CTRL);
232 l &= ~CONF_USB2_UNI_R;
233 omap_writel(l, USB_TRANSCEIVER_CTRL);
234 }
222 235
223 switch (nwires) { 236 switch (nwires) {
224 case 3: 237 case 3:
@@ -238,9 +251,13 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
238 omap_cfg_reg(K20_24XX_USB0_VM); 251 omap_cfg_reg(K20_24XX_USB0_VM);
239 omap2_usb_devconf_set(0, USB_UNIDIR); 252 omap2_usb_devconf_set(0, USB_UNIDIR);
240 } else { 253 } else {
254 u32 l;
255
241 omap_cfg_reg(AA9_USB0_VP); 256 omap_cfg_reg(AA9_USB0_VP);
242 omap_cfg_reg(R9_USB0_VM); 257 omap_cfg_reg(R9_USB0_VM);
243 USB_TRANSCEIVER_CTRL_REG |= CONF_USB2_UNI_R; 258 l = omap_readl(USB_TRANSCEIVER_CTRL);
259 l |= CONF_USB2_UNI_R;
260 omap_writel(l, USB_TRANSCEIVER_CTRL);
244 } 261 }
245 break; 262 break;
246 default: 263 default:
@@ -254,8 +271,13 @@ static u32 __init omap_usb1_init(unsigned nwires)
254{ 271{
255 u32 syscon1 = 0; 272 u32 syscon1 = 0;
256 273
257 if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) 274 if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) {
258 USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB1_UNI_R; 275 u32 l;
276
277 l = omap_readl(USB_TRANSCEIVER_CTRL);
278 l &= ~CONF_USB1_UNI_R;
279 omap_writel(l, USB_TRANSCEIVER_CTRL);
280 }
259 if (cpu_is_omap24xx()) 281 if (cpu_is_omap24xx())
260 omap2_usb_devconf_clear(1, USB_BIDIR_TLL); 282 omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
261 283
@@ -316,8 +338,13 @@ static u32 __init omap_usb1_init(unsigned nwires)
316 syscon1 = 3; 338 syscon1 = 3;
317 omap_cfg_reg(USB1_VP); 339 omap_cfg_reg(USB1_VP);
318 omap_cfg_reg(USB1_VM); 340 omap_cfg_reg(USB1_VM);
319 if (!cpu_is_omap15xx()) 341 if (!cpu_is_omap15xx()) {
320 USB_TRANSCEIVER_CTRL_REG |= CONF_USB1_UNI_R; 342 u32 l;
343
344 l = omap_readl(USB_TRANSCEIVER_CTRL);
345 l |= CONF_USB1_UNI_R;
346 omap_writel(l, USB_TRANSCEIVER_CTRL);
347 }
321 break; 348 break;
322 default: 349 default:
323bad: 350bad:
@@ -340,8 +367,13 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
340 if (alt_pingroup || nwires == 0) 367 if (alt_pingroup || nwires == 0)
341 return 0; 368 return 0;
342 369
343 if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) 370 if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) {
344 USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB2_UNI_R; 371 u32 l;
372
373 l = omap_readl(USB_TRANSCEIVER_CTRL);
374 l &= ~CONF_USB2_UNI_R;
375 omap_writel(l, USB_TRANSCEIVER_CTRL);
376 }
345 377
346 /* external transceiver */ 378 /* external transceiver */
347 if (cpu_is_omap15xx()) { 379 if (cpu_is_omap15xx()) {
@@ -410,9 +442,13 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
410 omap_cfg_reg(USB2_VP); 442 omap_cfg_reg(USB2_VP);
411 omap_cfg_reg(USB2_VM); 443 omap_cfg_reg(USB2_VM);
412 } else { 444 } else {
445 u32 l;
446
413 omap_cfg_reg(AA9_USB2_VP); 447 omap_cfg_reg(AA9_USB2_VP);
414 omap_cfg_reg(R9_USB2_VM); 448 omap_cfg_reg(R9_USB2_VM);
415 USB_TRANSCEIVER_CTRL_REG |= CONF_USB2_UNI_R; 449 l = omap_readl(USB_TRANSCEIVER_CTRL);
450 l |= CONF_USB2_UNI_R;
451 omap_writel(l, USB_TRANSCEIVER_CTRL);
416 } 452 }
417 break; 453 break;
418 default: 454 default:
@@ -531,10 +567,6 @@ static struct platform_device otg_device = {
531 567
532/*-------------------------------------------------------------------------*/ 568/*-------------------------------------------------------------------------*/
533 569
534#define ULPD_CLOCK_CTRL_REG __REG16(ULPD_CLOCK_CTRL)
535#define ULPD_SOFT_REQ_REG __REG16(ULPD_SOFT_REQ)
536
537
538// FIXME correct answer depends on hmc_mode, 570// FIXME correct answer depends on hmc_mode,
539// as does (on omap1) any nonzero value for config->otg port number 571// as does (on omap1) any nonzero value for config->otg port number
540#ifdef CONFIG_USB_GADGET_OMAP 572#ifdef CONFIG_USB_GADGET_OMAP
@@ -550,17 +582,17 @@ static struct platform_device otg_device = {
550void __init 582void __init
551omap_otg_init(struct omap_usb_config *config) 583omap_otg_init(struct omap_usb_config *config)
552{ 584{
553 u32 syscon = OTG_SYSCON_1_REG & 0xffff; 585 u32 syscon;
554 int status; 586 int status;
555 int alt_pingroup = 0; 587 int alt_pingroup = 0;
556 588
557 /* NOTE: no bus or clock setup (yet?) */ 589 /* NOTE: no bus or clock setup (yet?) */
558 590
559 syscon = OTG_SYSCON_1_REG & 0xffff; 591 syscon = omap_readl(OTG_SYSCON_1) & 0xffff;
560 if (!(syscon & OTG_RESET_DONE)) 592 if (!(syscon & OTG_RESET_DONE))
561 pr_debug("USB resets not complete?\n"); 593 pr_debug("USB resets not complete?\n");
562 594
563 // OTG_IRQ_EN_REG = 0; 595 //omap_writew(0, OTG_IRQ_EN);
564 596
565 /* pin muxing and transceiver pinouts */ 597 /* pin muxing and transceiver pinouts */
566 if (config->pins[0] > 2) /* alt pingroup 2 */ 598 if (config->pins[0] > 2) /* alt pingroup 2 */
@@ -568,8 +600,8 @@ omap_otg_init(struct omap_usb_config *config)
568 syscon |= omap_usb0_init(config->pins[0], is_usb0_device(config)); 600 syscon |= omap_usb0_init(config->pins[0], is_usb0_device(config));
569 syscon |= omap_usb1_init(config->pins[1]); 601 syscon |= omap_usb1_init(config->pins[1]);
570 syscon |= omap_usb2_init(config->pins[2], alt_pingroup); 602 syscon |= omap_usb2_init(config->pins[2], alt_pingroup);
571 pr_debug("OTG_SYSCON_1_REG = %08x\n", syscon); 603 pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
572 OTG_SYSCON_1_REG = syscon; 604 omap_writel(syscon, OTG_SYSCON_1);
573 605
574 syscon = config->hmc_mode; 606 syscon = config->hmc_mode;
575 syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */; 607 syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */;
@@ -578,9 +610,10 @@ omap_otg_init(struct omap_usb_config *config)
578 syscon |= OTG_EN; 610 syscon |= OTG_EN;
579#endif 611#endif
580 if (cpu_class_is_omap1()) 612 if (cpu_class_is_omap1())
581 pr_debug("USB_TRANSCEIVER_CTRL_REG = %03x\n", USB_TRANSCEIVER_CTRL_REG); 613 pr_debug("USB_TRANSCEIVER_CTRL = %03x\n",
582 pr_debug("OTG_SYSCON_2_REG = %08x\n", syscon); 614 omap_readl(USB_TRANSCEIVER_CTRL));
583 OTG_SYSCON_2_REG = syscon; 615 pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2));
616 omap_writel(syscon, OTG_SYSCON_2);
584 617
585 printk("USB: hmc %d", config->hmc_mode); 618 printk("USB: hmc %d", config->hmc_mode);
586 if (!alt_pingroup) 619 if (!alt_pingroup)
@@ -597,12 +630,19 @@ omap_otg_init(struct omap_usb_config *config)
597 printk("\n"); 630 printk("\n");
598 631
599 if (cpu_class_is_omap1()) { 632 if (cpu_class_is_omap1()) {
633 u16 w;
634
600 /* leave USB clocks/controllers off until needed */ 635 /* leave USB clocks/controllers off until needed */
601 ULPD_SOFT_REQ_REG &= ~SOFT_USB_CLK_REQ; 636 w = omap_readw(ULPD_SOFT_REQ);
602 ULPD_CLOCK_CTRL_REG &= ~USB_MCLK_EN; 637 w &= ~SOFT_USB_CLK_REQ;
603 ULPD_CLOCK_CTRL_REG |= DIS_USB_PVCI_CLK; 638 omap_writew(w, ULPD_SOFT_REQ);
639
640 w = omap_readw(ULPD_CLOCK_CTRL);
641 w &= ~USB_MCLK_EN;
642 w |= DIS_USB_PVCI_CLK;
643 omap_writew(w, ULPD_CLOCK_CTRL);
604 } 644 }
605 syscon = OTG_SYSCON_1_REG; 645 syscon = omap_readl(OTG_SYSCON_1);
606 syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN; 646 syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
607 647
608#ifdef CONFIG_USB_GADGET_OMAP 648#ifdef CONFIG_USB_GADGET_OMAP
@@ -639,8 +679,8 @@ omap_otg_init(struct omap_usb_config *config)
639 pr_debug("can't register OTG device, %d\n", status); 679 pr_debug("can't register OTG device, %d\n", status);
640 } 680 }
641#endif 681#endif
642 pr_debug("OTG_SYSCON_1_REG = %08x\n", syscon); 682 pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
643 OTG_SYSCON_1_REG = syscon; 683 omap_writel(syscon, OTG_SYSCON_1);
644 684
645 status = 0; 685 status = 0;
646} 686}
@@ -653,18 +693,19 @@ static inline void omap_otg_init(struct omap_usb_config *config) {}
653 693
654#ifdef CONFIG_ARCH_OMAP15XX 694#ifdef CONFIG_ARCH_OMAP15XX
655 695
656#define ULPD_DPLL_CTRL_REG __REG16(ULPD_DPLL_CTRL) 696/* ULPD_DPLL_CTRL */
657#define DPLL_IOB (1 << 13) 697#define DPLL_IOB (1 << 13)
658#define DPLL_PLL_ENABLE (1 << 4) 698#define DPLL_PLL_ENABLE (1 << 4)
659#define DPLL_LOCK (1 << 0) 699#define DPLL_LOCK (1 << 0)
660 700
661#define ULPD_APLL_CTRL_REG __REG16(ULPD_APLL_CTRL) 701/* ULPD_APLL_CTRL */
662#define APLL_NDPLL_SWITCH (1 << 0) 702#define APLL_NDPLL_SWITCH (1 << 0)
663 703
664 704
665static void __init omap_1510_usb_init(struct omap_usb_config *config) 705static void __init omap_1510_usb_init(struct omap_usb_config *config)
666{ 706{
667 unsigned int val; 707 unsigned int val;
708 u16 w;
668 709
669 omap_usb0_init(config->pins[0], is_usb0_device(config)); 710 omap_usb0_init(config->pins[0], is_usb0_device(config));
670 omap_usb1_init(config->pins[1]); 711 omap_usb1_init(config->pins[1]);
@@ -685,12 +726,22 @@ static void __init omap_1510_usb_init(struct omap_usb_config *config)
685 printk("\n"); 726 printk("\n");
686 727
687 /* use DPLL for 48 MHz function clock */ 728 /* use DPLL for 48 MHz function clock */
688 pr_debug("APLL %04x DPLL %04x REQ %04x\n", ULPD_APLL_CTRL_REG, 729 pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL),
689 ULPD_DPLL_CTRL_REG, ULPD_SOFT_REQ_REG); 730 omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ));
690 ULPD_APLL_CTRL_REG &= ~APLL_NDPLL_SWITCH; 731
691 ULPD_DPLL_CTRL_REG |= DPLL_IOB | DPLL_PLL_ENABLE; 732 w = omap_readw(ULPD_APLL_CTRL);
692 ULPD_SOFT_REQ_REG |= SOFT_UDC_REQ | SOFT_DPLL_REQ; 733 w &= ~APLL_NDPLL_SWITCH;
693 while (!(ULPD_DPLL_CTRL_REG & DPLL_LOCK)) 734 omap_writew(w, ULPD_APLL_CTRL);
735
736 w = omap_readw(ULPD_DPLL_CTRL);
737 w |= DPLL_IOB | DPLL_PLL_ENABLE;
738 omap_writew(w, ULPD_DPLL_CTRL);
739
740 w = omap_readw(ULPD_SOFT_REQ);
741 w |= SOFT_UDC_REQ | SOFT_DPLL_REQ;
742 omap_writew(w, ULPD_SOFT_REQ);
743
744 while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK))
694 cpu_relax(); 745 cpu_relax();
695 746
696#ifdef CONFIG_USB_GADGET_OMAP 747#ifdef CONFIG_USB_GADGET_OMAP
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-20 07:59:57 -0500