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authorTony Lindgren <tony@atomide.com>2010-09-27 16:17:13 -0400
committerTony Lindgren <tony@atomide.com>2010-09-27 16:17:13 -0400
commit91f6c90c8df1818a66d177e105d602c3da820919 (patch)
tree5cb1b01823dd676a07596f6153d2fc124c4691cb /arch/arm/plat-omap
parent6e457bb05c348e196f67005876992ceb5eb0430a (diff)
parenta3fed9bc181666df6ecfe9ce34a29d48803f2310 (diff)
Merge branch 'omap4_and_sdrc_2.6.27' of git://git.pwsan.com/linux-2.6 into omap-for-linus
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r--arch/arm/plat-omap/common.c3
-rw-r--r--arch/arm/plat-omap/include/plat/common.h1
-rw-r--r--arch/arm/plat-omap/include/plat/control.h31
-rw-r--r--arch/arm/plat-omap/include/plat/powerdomain.h1
4 files changed, 12 insertions, 24 deletions
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 3008e7104487..7d668b3b5363 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -336,7 +336,8 @@ void __init omap3_map_io(void)
336static struct omap_globals omap4_globals = { 336static struct omap_globals omap4_globals = {
337 .class = OMAP443X_CLASS, 337 .class = OMAP443X_CLASS,
338 .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), 338 .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
339 .ctrl = OMAP443X_CTRL_BASE, 339 .ctrl = OMAP443X_SCM_BASE,
340 .ctrl_pad = OMAP443X_CTRL_BASE,
340 .prm = OMAP4430_PRM_BASE, 341 .prm = OMAP4430_PRM_BASE,
341 .cm = OMAP4430_CM_BASE, 342 .cm = OMAP4430_CM_BASE,
342 .cm2 = OMAP4430_CM2_BASE, 343 .cm2 = OMAP4430_CM2_BASE,
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index c45dbb975e09..2d8f98d7ae50 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -47,6 +47,7 @@ struct omap_globals {
47 unsigned long sdrc; /* SDRAM Controller */ 47 unsigned long sdrc; /* SDRAM Controller */
48 unsigned long sms; /* SDRAM Memory Scheduler */ 48 unsigned long sms; /* SDRAM Memory Scheduler */
49 unsigned long ctrl; /* System Control Module */ 49 unsigned long ctrl; /* System Control Module */
50 unsigned long ctrl_pad; /* PAD Control Module */
50 unsigned long prm; /* Power and Reset Management */ 51 unsigned long prm; /* Power and Reset Management */
51 unsigned long cm; /* Clock Management */ 52 unsigned long cm; /* Clock Management */
52 unsigned long cm2; 53 unsigned long cm2;
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
index 131bf405c2f6..19c9b2a82046 100644
--- a/arch/arm/plat-omap/include/plat/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -17,6 +17,10 @@
17#define __ASM_ARCH_CONTROL_H 17#define __ASM_ARCH_CONTROL_H
18 18
19#include <mach/io.h> 19#include <mach/io.h>
20#include <mach/ctrl_module_core_44xx.h>
21#include <mach/ctrl_module_wkup_44xx.h>
22#include <mach/ctrl_module_pad_core_44xx.h>
23#include <mach/ctrl_module_pad_wkup_44xx.h>
20 24
21#ifndef __ASSEMBLY__ 25#ifndef __ASSEMBLY__
22#define OMAP242X_CTRL_REGADDR(reg) \ 26#define OMAP242X_CTRL_REGADDR(reg) \
@@ -204,12 +208,6 @@
204#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 208#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
205#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 209#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
206 210
207/* 44xx control status register offset */
208#define OMAP44XX_CONTROL_STATUS 0x2c4
209
210/* 44xx-only CONTROL_GENERAL register offsets */
211#define OMAP44XX_CONTROL_MMC1 0x628
212#define OMAP44XX_CONTROL_PBIAS_LITE 0x600
213/* 211/*
214 * REVISIT: This list of registers is not comprehensive - there are more 212 * REVISIT: This list of registers is not comprehensive - there are more
215 * that should be added. 213 * that should be added.
@@ -255,23 +253,6 @@
255#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) 253#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
256#define OMAP2_PBIASLITEVMODE0 (1 << 0) 254#define OMAP2_PBIASLITEVMODE0 (1 << 0)
257 255
258/* CONTROL_PBIAS_LITE bits for OMAP4 */
259#define OMAP4_MMC1_PWRDNZ (1 << 26)
260#define OMAP4_MMC1_PBIASLITE_HIZ_MODE (1 << 25)
261#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT (1 << 24)
262#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR (1 << 23)
263#define OMAP4_MMC1_PBIASLITE_PWRDNZ (1 << 22)
264#define OMAP4_MMC1_PBIASLITE_VMODE (1 << 21)
265#define OMAP4_USBC1_ICUSB_PWRDNZ (1 << 20)
266
267#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 (1 << 31)
268#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1 (1 << 30)
269#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 (1 << 29)
270#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3 (1 << 28)
271#define OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL (1 << 27)
272#define OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL (1 << 26)
273#define OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL (1 << 25)
274
275/* CONTROL_PROG_IO1 bits */ 256/* CONTROL_PROG_IO1 bits */
276#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) 257#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
277 258
@@ -354,9 +335,11 @@ extern void __iomem *omap_ctrl_base_get(void);
354extern u8 omap_ctrl_readb(u16 offset); 335extern u8 omap_ctrl_readb(u16 offset);
355extern u16 omap_ctrl_readw(u16 offset); 336extern u16 omap_ctrl_readw(u16 offset);
356extern u32 omap_ctrl_readl(u16 offset); 337extern u32 omap_ctrl_readl(u16 offset);
338extern u32 omap4_ctrl_pad_readl(u16 offset);
357extern void omap_ctrl_writeb(u8 val, u16 offset); 339extern void omap_ctrl_writeb(u8 val, u16 offset);
358extern void omap_ctrl_writew(u16 val, u16 offset); 340extern void omap_ctrl_writew(u16 val, u16 offset);
359extern void omap_ctrl_writel(u32 val, u16 offset); 341extern void omap_ctrl_writel(u32 val, u16 offset);
342extern void omap4_ctrl_pad_writel(u32 val, u16 offset);
360 343
361extern void omap3_save_scratchpad_contents(void); 344extern void omap3_save_scratchpad_contents(void);
362extern void omap3_clear_scratchpad_contents(void); 345extern void omap3_clear_scratchpad_contents(void);
@@ -371,9 +354,11 @@ extern void omap3_control_restore_context(void);
371#define omap_ctrl_readb(x) 0 354#define omap_ctrl_readb(x) 0
372#define omap_ctrl_readw(x) 0 355#define omap_ctrl_readw(x) 0
373#define omap_ctrl_readl(x) 0 356#define omap_ctrl_readl(x) 0
357#define omap4_ctrl_pad_readl(x) 0
374#define omap_ctrl_writeb(x, y) WARN_ON(1) 358#define omap_ctrl_writeb(x, y) WARN_ON(1)
375#define omap_ctrl_writew(x, y) WARN_ON(1) 359#define omap_ctrl_writew(x, y) WARN_ON(1)
376#define omap_ctrl_writel(x, y) WARN_ON(1) 360#define omap_ctrl_writel(x, y) WARN_ON(1)
361#define omap4_ctrl_pad_writel(x, y) WARN_ON(1)
377#endif 362#endif
378#endif /* __ASSEMBLY__ */ 363#endif /* __ASSEMBLY__ */
379 364
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index fb6ec74fe39e..3ea722072e2f 100644
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -32,6 +32,7 @@
32 32
33/* Powerdomain allowable state bitfields */ 33/* Powerdomain allowable state bitfields */
34#define PWRSTS_ON (1 << PWRDM_POWER_ON) 34#define PWRSTS_ON (1 << PWRDM_POWER_ON)
35#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
35#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ 36#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
36 (1 << PWRDM_POWER_ON)) 37 (1 << PWRDM_POWER_ON))
37 38