Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 into for-linus-1

* 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6: (9356 commits)
  [media] rc: update for bitop name changes
  fs: simplify iget & friends
  fs: pull inode->i_lock up out of writeback_single_inode
  fs: rename inode_lock to inode_hash_lock
  fs: move i_wb_list out from under inode_lock
  fs: move i_sb_list out from under inode_lock
  fs: remove inode_lock from iput_final and prune_icache
  fs: Lock the inode LRU list separately
  fs: factor inode disposal
  fs: protect inode->i_state with inode->i_lock
  lib, arch: add filter argument to show_mem and fix private implementations
  SLUB: Write to per cpu data when allocating it
  slub: Fix debugobjects with lockless fastpath
  autofs4: Do not potentially dereference NULL pointer returned by fget() in autofs_dev_ioctl_setpipefd()
  autofs4 - remove autofs4_lock
  autofs4 - fix d_manage() return on rcu-walk
  autofs4 - fix autofs4_expire_indirect() traversal
  autofs4 - fix dentry leak in autofs4_expire_direct()
  autofs4 - reinstate last used update on access
  vfs - check non-mountpoint dentry might block in __follow_mount_rcu()
  ...

NOTE!

This merge commit was created to fix compilation error. The block
tree was merged upstream and removed the 'elv_queue_empty()'
function which the new 'mtdswap' driver is using. So a simple
merge of the mtd tree with upstream does not compile. And the
mtd tree has already be published, so re-basing it is not an option.

To fix this unfortunate situation, I had to merge upstream into the
mtd-2.6.git tree without committing, put the fixup patch on top of
this, and then commit this. The result is that we do not have commits
which do not compile.

In other words, this merge commit "merges" 3 things: the MTD tree, the
upstream tree, and the fixup patch.

53 files changed, 845 insertions, 810 deletions

diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 18fe3cb195dc..cd5f993612fd 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -54,7 +54,7 @@ config OMAP_SMARTREFLEX
           user must write 1 to
                 /debug/voltage/vdd_<X>/smartreflex/autocomp,
           where X is mpu or core for OMAP3.
-          Optionallly autocompensation can be enabled in the kernel
+          Optionally autocompensation can be enabled in the kernel
           by default during system init via the enable_on_init flag
           which an be passed as platform data to the smartreflex driver.
 
@@ -144,12 +144,9 @@ config OMAP_IOMMU_DEBUG
 config OMAP_IOMMU_IVA2
         bool
 
-choice
-        prompt "System timer"
-        default OMAP_32K_TIMER if !ARCH_OMAP15XX
-
 config OMAP_MPU_TIMER
         bool "Use mpu timer"
+        depends on ARCH_OMAP1
         help
           Select this option if you want to use the OMAP mpu timer. This
           timer provides more intra-tick resolution than the 32KHz timer,
@@ -158,6 +155,7 @@ config OMAP_MPU_TIMER
 config OMAP_32K_TIMER
         bool "Use 32KHz timer"
         depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS
+        default y if (ARCH_OMAP16XX || ARCH_OMAP2PLUS)
         help
           Select this option if you want to enable the OMAP 32KHz timer.
           This timer saves power compared to the OMAP_MPU_TIMER, and has
@@ -165,8 +163,6 @@ config OMAP_32K_TIMER
           intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
           currently only available for OMAP16XX, 24XX, 34XX and OMAP4.
 
-endchoice
-
 config OMAP3_L2_AUX_SECURE_SAVE_RESTORE
         bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
         depends on ARCH_OMAP3 && PM
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index fc62fb5fc20b..c9122dd6ee8d 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -37,14 +37,16 @@ static struct clk_functions *arch_clock;
 int clk_enable(struct clk *clk)
 {
         unsigned long flags;
-        int ret = 0;
+        int ret;
 
         if (clk == NULL || IS_ERR(clk))
                 return -EINVAL;
 
+        if (!arch_clock || !arch_clock->clk_enable)
+                return -EINVAL;
+
         spin_lock_irqsave(&clockfw_lock, flags);
-        if (arch_clock->clk_enable)
-                ret = arch_clock->clk_enable(clk);
+        ret = arch_clock->clk_enable(clk);
         spin_unlock_irqrestore(&clockfw_lock, flags);
 
         return ret;
@@ -58,6 +60,9 @@ void clk_disable(struct clk *clk)
         if (clk == NULL || IS_ERR(clk))
                 return;
 
+        if (!arch_clock || !arch_clock->clk_disable)
+                return;
+
         spin_lock_irqsave(&clockfw_lock, flags);
         if (clk->usecount == 0) {
                 pr_err("Trying disable clock %s with 0 usecount\n",
@@ -66,8 +71,7 @@ void clk_disable(struct clk *clk)
                 goto out;
         }
 
-        if (arch_clock->clk_disable)
-                arch_clock->clk_disable(clk);
+        arch_clock->clk_disable(clk);
 
 out:
         spin_unlock_irqrestore(&clockfw_lock, flags);
@@ -77,7 +81,7 @@ EXPORT_SYMBOL(clk_disable);
 unsigned long clk_get_rate(struct clk *clk)
 {
         unsigned long flags;
-        unsigned long ret = 0;
+        unsigned long ret;
 
         if (clk == NULL || IS_ERR(clk))
                 return 0;
@@ -97,14 +101,16 @@ EXPORT_SYMBOL(clk_get_rate);
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
         unsigned long flags;
-        long ret = 0;
+        long ret;
 
         if (clk == NULL || IS_ERR(clk))
-                return ret;
+                return 0;
+
+        if (!arch_clock || !arch_clock->clk_round_rate)
+                return 0;
 
         spin_lock_irqsave(&clockfw_lock, flags);
-        if (arch_clock->clk_round_rate)
-                ret = arch_clock->clk_round_rate(clk, rate);
+        ret = arch_clock->clk_round_rate(clk, rate);
         spin_unlock_irqrestore(&clockfw_lock, flags);
 
         return ret;
@@ -119,14 +125,13 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
         if (clk == NULL || IS_ERR(clk))
                 return ret;
 
+        if (!arch_clock || !arch_clock->clk_set_rate)
+                return ret;
+
         spin_lock_irqsave(&clockfw_lock, flags);
-        if (arch_clock->clk_set_rate)
-                ret = arch_clock->clk_set_rate(clk, rate);
-        if (ret == 0) {
-                if (clk->recalc)
-                        clk->rate = clk->recalc(clk);
+        ret = arch_clock->clk_set_rate(clk, rate);
+        if (ret == 0)
                 propagate_rate(clk);
-        }
         spin_unlock_irqrestore(&clockfw_lock, flags);
 
         return ret;
@@ -141,15 +146,14 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
         if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
                 return ret;
 
+        if (!arch_clock || !arch_clock->clk_set_parent)
+                return ret;
+
         spin_lock_irqsave(&clockfw_lock, flags);
         if (clk->usecount == 0) {
-                if (arch_clock->clk_set_parent)
-                        ret = arch_clock->clk_set_parent(clk, parent);
-                if (ret == 0) {
-                        if (clk->recalc)
-                                clk->rate = clk->recalc(clk);
+                ret = arch_clock->clk_set_parent(clk, parent);
+                if (ret == 0)
                         propagate_rate(clk);
-                }
         } else
                 ret = -EBUSY;
         spin_unlock_irqrestore(&clockfw_lock, flags);
@@ -335,6 +339,38 @@ struct clk *omap_clk_get_by_name(const char *name)
         return ret;
 }
 
+int omap_clk_enable_autoidle_all(void)
+{
+        struct clk *c;
+        unsigned long flags;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+
+        list_for_each_entry(c, &clocks, node)
+                if (c->ops->allow_idle)
+                        c->ops->allow_idle(c);
+
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
+        return 0;
+}
+
+int omap_clk_disable_autoidle_all(void)
+{
+        struct clk *c;
+        unsigned long flags;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+
+        list_for_each_entry(c, &clocks, node)
+                if (c->ops->deny_idle)
+                        c->ops->deny_idle(c);
+
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
+        return 0;
+}
+
 /*
  * Low level helpers
  */
@@ -367,9 +403,11 @@ void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
 {
         unsigned long flags;
 
+        if (!arch_clock || !arch_clock->clk_init_cpufreq_table)
+                return;
+
         spin_lock_irqsave(&clockfw_lock, flags);
-        if (arch_clock->clk_init_cpufreq_table)
-                arch_clock->clk_init_cpufreq_table(table);
+        arch_clock->clk_init_cpufreq_table(table);
         spin_unlock_irqrestore(&clockfw_lock, flags);
 }
 
@@ -377,9 +415,11 @@ void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
 {
         unsigned long flags;
 
+        if (!arch_clock || !arch_clock->clk_exit_cpufreq_table)
+                return;
+
         spin_lock_irqsave(&clockfw_lock, flags);
-        if (arch_clock->clk_exit_cpufreq_table)
-                arch_clock->clk_exit_cpufreq_table(table);
+        arch_clock->clk_exit_cpufreq_table(table);
         spin_unlock_irqrestore(&clockfw_lock, flags);
 }
 #endif
@@ -397,6 +437,9 @@ static int __init clk_disable_unused(void)
         struct clk *ck;
         unsigned long flags;
 
+        if (!arch_clock || !arch_clock->clk_disable_unused)
+                return 0;
+
         pr_info("clock: disabling unused clocks to save power\n");
         list_for_each_entry(ck, &clocks, node) {
                 if (ck->ops == &clkops_null)
@@ -406,14 +449,14 @@ static int __init clk_disable_unused(void)
                         continue;
 
                 spin_lock_irqsave(&clockfw_lock, flags);
-                if (arch_clock->clk_disable_unused)
-                        arch_clock->clk_disable_unused(ck);
+                arch_clock->clk_disable_unused(ck);
                 spin_unlock_irqrestore(&clockfw_lock, flags);
         }
 
         return 0;
 }
 late_initcall(clk_disable_unused);
+late_initcall(omap_clk_enable_autoidle_all);
 #endif
 
 int __init clk_init(struct clk_functions * custom_clocks)
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index f04731820301..d9f10a31e604 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -24,10 +24,11 @@
 
 #define NO_LENGTH_CHECK 0xffffffff
 
-struct omap_board_config_kernel *omap_board_config;
+struct omap_board_config_kernel *omap_board_config __initdata;
 int omap_board_config_size;
 
-static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
+static const void *__init get_config(u16 tag, size_t len,
+                int skip, size_t *len_out)
 {
         struct omap_board_config_kernel *kinfo = NULL;
         int i;
@@ -49,17 +50,15 @@ static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
         return kinfo->data;
 }
 
-const void *__omap_get_config(u16 tag, size_t len, int nr)
+const void *__init __omap_get_config(u16 tag, size_t len, int nr)
 {
         return get_config(tag, len, nr, NULL);
 }
-EXPORT_SYMBOL(__omap_get_config);
 
-const void *omap_get_var_config(u16 tag, size_t *len)
+const void *__init omap_get_var_config(u16 tag, size_t *len)
 {
         return get_config(tag, NO_LENGTH_CHECK, 0, len);
 }
-EXPORT_SYMBOL(omap_get_var_config);
 
 void __init omap_reserve(void)
 {
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index ea4644021fb9..f7fed6080190 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -36,8 +36,6 @@
 
 #define OMAP16XX_TIMER_32K_SYNCHRONIZED         0xfffbc410
 
-#if !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX))
-
 #include <linux/clocksource.h>
 
 /*
@@ -56,7 +54,7 @@ static cycle_t notrace omap16xx_32k_read(struct clocksource *cs)
 #define omap16xx_32k_read       NULL
 #endif
 
-#ifdef CONFIG_ARCH_OMAP2420
+#ifdef CONFIG_SOC_OMAP2420
 static cycle_t notrace omap2420_32k_read(struct clocksource *cs)
 {
         return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k;
@@ -65,7 +63,7 @@ static cycle_t notrace omap2420_32k_read(struct clocksource *cs)
 #define omap2420_32k_read       NULL
 #endif
 
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 static cycle_t notrace omap2430_32k_read(struct clocksource *cs)
 {
         return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k;
@@ -122,12 +120,24 @@ static DEFINE_CLOCK_DATA(cd);
 #define SC_MULT         4000000000u
 #define SC_SHIFT        17
 
-unsigned long long notrace sched_clock(void)
+static inline unsigned long long notrace _omap_32k_sched_clock(void)
 {
         u32 cyc = clocksource_32k.read(&clocksource_32k);
         return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
 }
 
+#ifndef CONFIG_OMAP_MPU_TIMER
+unsigned long long notrace sched_clock(void)
+{
+        return _omap_32k_sched_clock();
+}
+#else
+unsigned long long notrace omap_32k_sched_clock(void)
+{
+        return _omap_32k_sched_clock();
+}
+#endif
+
 static void notrace omap_update_sched_clock(void)
 {
         u32 cyc = clocksource_32k.read(&clocksource_32k);
@@ -160,7 +170,7 @@ void read_persistent_clock(struct timespec *ts)
         *ts = *tsp;
 }
 
-static int __init omap_init_clocksource_32k(void)
+int __init omap_init_clocksource_32k(void)
 {
         static char err[] __initdata = KERN_ERR
                         "%s: can't register clocksource!\n";
@@ -195,7 +205,3 @@ static int __init omap_init_clocksource_32k(void)
         }
         return 0;
 }
-arch_initcall(omap_init_clocksource_32k);
-
-#endif  /* !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) */
-
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
index 11c54ec8d47f..da4f68dbba1d 100644
--- a/arch/arm/plat-omap/cpu-omap.c
+++ b/arch/arm/plat-omap/cpu-omap.c
@@ -101,7 +101,7 @@ static int omap_target(struct cpufreq_policy *policy,
         return ret;
 }
 
-static int __init omap_cpu_init(struct cpufreq_policy *policy)
+static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy)
 {
         int result = 0;
 
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 10245b837c10..7d9f815cedec 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -35,8 +35,8 @@
 
 static struct platform_device **omap_mcbsp_devices;
 
-void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
-                                        int size)
+void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
+                        struct omap_mcbsp_platform_data *config, int size)
 {
         int i;
 
@@ -54,6 +54,8 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
                 new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1);
                 if (!new_mcbsp)
                         continue;
+                platform_device_add_resources(new_mcbsp, &res[i * res_count],
+                                        res_count);
                 new_mcbsp->dev.platform_data = &config[i];
                 ret = platform_device_add(new_mcbsp);
                 if (ret) {
@@ -65,8 +67,8 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
 }
 
 #else
-void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
-                                        int size)
+void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
+                        struct omap_mcbsp_platform_data *config, int size)
 {  }
 #endif
 
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index c4b2b478b1a5..2ec3b5d9f214 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -53,7 +53,7 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
 #endif
 
 #define OMAP_DMA_ACTIVE                 0x01
-#define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
+#define OMAP2_DMA_CSR_CLEAR_MASK        0xffffffff
 
 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
 
@@ -134,7 +134,7 @@ static inline void omap_enable_channel_irq(int lch);
 
 #ifdef CONFIG_ARCH_OMAP15XX
 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
-int omap_dma_in_1510_mode(void)
+static int omap_dma_in_1510_mode(void)
 {
         return enable_1510_mode;
 }
@@ -1873,7 +1873,7 @@ static int omap2_dma_handle_ch(int ch)
                 printk(KERN_INFO "DMA misaligned error with device %d\n",
                        dma_chan[ch].dev_id);
 
-        p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, ch);
+        p->dma_write(status, CSR, ch);
         p->dma_write(1 << ch, IRQSTATUS_L0, ch);
         /* read back the register to flush the write */
         p->dma_read(IRQSTATUS_L0, ch);
@@ -1893,10 +1893,9 @@ static int omap2_dma_handle_ch(int ch)
                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
 
                 status = p->dma_read(CSR, ch);
+                p->dma_write(status, CSR, ch);
         }
 
-        p->dma_write(status, CSR, ch);
-
         if (likely(dma_chan[ch].callback != NULL))
                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
 
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 1d706cf63ca0..ee9f6ebba29b 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -342,6 +342,10 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
         l |= 0x02 << 3;  /* Set to smart-idle mode */
         l |= 0x2 << 8;   /* Set clock activity to perserve f-clock on idle */
 
+        /* Enable autoidle on OMAP2 / OMAP3 */
+        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+                l |= 0x1 << 0;
+
         /*
          * Enable wake-up on OMAP2 CPUs.
          */
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index a4f8003de664..3341ca4703e9 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -112,6 +112,7 @@ static inline int omap1_i2c_add_bus(int bus_id)
 }
 
 
+#ifdef CONFIG_ARCH_OMAP2PLUS
 /*
  * XXX This function is a temporary compatibility wrapper - only
  * needed until the I2C driver can be converted to call
@@ -130,7 +131,6 @@ static struct omap_device_pm_latency omap_i2c_latency[] = {
         },
 };
 
-#ifdef CONFIG_ARCH_OMAP2PLUS
 static inline int omap2_i2c_add_bus(int bus_id)
 {
         int l;
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index 3cf4fa25ab3d..97126dfd2888 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -151,14 +151,14 @@ struct omap_board_config_kernel {
         const void *data;
 };
 
-extern const void *__omap_get_config(u16 tag, size_t len, int nr);
+extern const void *__init __omap_get_config(u16 tag, size_t len, int nr);
 
 #define omap_get_config(tag, type) \
         ((const type *) __omap_get_config((tag), sizeof(type), 0))
 #define omap_get_nr_config(tag, type, nr) \
         ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
 
-extern const void *omap_get_var_config(u16 tag, size_t *len);
+extern const void *__init omap_get_var_config(u16 tag, size_t *len);
 
 extern struct omap_board_config_kernel *omap_board_config;
 extern int omap_board_config_size;
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index 256ab3f1ec8f..f1899a3e4174 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -38,6 +38,7 @@ struct omap_clk {
 #define CK_3517         (1 << 9)
 #define CK_36XX         (1 << 10)       /* 36xx/37xx-specific clocks */
 #define CK_443X         (1 << 11)
+#define CK_TI816X       (1 << 12)
 
 
 #define CK_34XX         (CK_3430ES1 | CK_3430ES2PLUS)
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 8eb0adab19ea..006e599c6613 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -25,6 +25,8 @@ struct clockdomain;
  * @disable: fn ptr that enables the current clock in hardware
  * @find_idlest: function returning the IDLEST register for the clock's IP blk
  * @find_companion: function returning the "companion" clk reg for the clock
+ * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
+ * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
  *
  * A "companion" clk is an accompanying clock to the one being queried
  * that must be enabled for the IP module connected to the clock to
@@ -42,6 +44,8 @@ struct clkops {
                                                u8 *, u8 *);
         void                    (*find_companion)(struct clk *, void __iomem **,
                                                   u8 *);
+        void                    (*allow_idle)(struct clk *);
+        void                    (*deny_idle)(struct clk *);
 };
 
 #ifdef CONFIG_ARCH_OMAP2PLUS
@@ -53,6 +57,7 @@ struct clkops {
 #define RATE_IN_3430ES2PLUS     (1 << 3)        /* 3430 ES >= 2 rates only */
 #define RATE_IN_36XX            (1 << 4)
 #define RATE_IN_4430            (1 << 5)
+#define RATE_IN_TI816X          (1 << 6)
 
 #define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
 #define RATE_IN_34XX            (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
@@ -104,7 +109,6 @@ struct clksel {
  * @clk_ref: struct clk pointer to the clock's reference clock input
  * @control_reg: register containing the DPLL mode bitfield
  * @enable_mask: mask of the DPLL mode bitfield in @control_reg
- * @rate_tolerance: maximum variance allowed from target rate (in Hz)
  * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
  * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
  * @max_multiplier: maximum valid non-bypass multiplier value (actual)
@@ -130,12 +134,9 @@ struct clksel {
  * XXX Some DPLLs have multiple bypass inputs, so it's not technically
  * correct to only have one @clk_bypass pointer.
  *
- * XXX @rate_tolerance should probably be deprecated - currently there
- * don't seem to be any usecases for DPLL rounding that is not exact.
- *
  * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
  * @last_rounded_n) should be separated from the runtime-fixed fields
- * and placed into a differenct structure, so that the runtime-fixed data
+ * and placed into a different structure, so that the runtime-fixed data
  * can be placed into read-only space.
  */
 struct dpll_data {
@@ -146,7 +147,6 @@ struct dpll_data {
         struct clk              *clk_ref;
         void __iomem            *control_reg;
         u32                     enable_mask;
-        unsigned int            rate_tolerance;
         unsigned long           last_rounded_rate;
         u16                     last_rounded_m;
         u16                     max_multiplier;
@@ -171,12 +171,24 @@ struct dpll_data {
 
 #endif
 
-/* struct clk.flags possibilities */
+/*
+ * struct clk.flags possibilities
+ *
+ * XXX document the rest of the clock flags here
+ *
+ * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
+ *     bits share the same register.  This flag allows the
+ *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
+ *     should be used.  This is a temporary solution - a better approach
+ *     would be to associate clock type-specific data with the clock,
+ *     similar to the struct dpll_data approach.
+ */
 #define ENABLE_REG_32BIT        (1 << 0)        /* Use 32-bit access */
 #define CLOCK_IDLE_CONTROL      (1 << 1)
 #define CLOCK_NO_IDLE_PARENT    (1 << 2)
 #define ENABLE_ON_INIT          (1 << 3)        /* Enable upon framework init */
 #define INVERT_ENABLE           (1 << 4)        /* 0 enables, 1 disables */
+#define CLOCK_CLKOUTX2          (1 << 5)
 
 /**
  * struct clk - OMAP struct clk
@@ -292,6 +304,8 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
 #endif
 extern struct clk *omap_clk_get_by_name(const char *name);
+extern int omap_clk_enable_autoidle_all(void);
+extern int omap_clk_disable_autoidle_all(void);
 
 extern const struct clkops clkops_null;
 
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 6b8088ec74af..5288130be96e 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -35,6 +35,9 @@ struct sys_timer;
 
 extern void omap_map_common_io(void);
 extern struct sys_timer omap_timer;
+extern bool omap_32k_timer_init(void);
+extern int __init omap_init_clocksource_32k(void);
+extern unsigned long long notrace omap_32k_sched_clock(void);
 
 extern void omap_reserve(void);
 
@@ -53,16 +56,13 @@ struct omap_globals {
         unsigned long   prm;            /* Power and Reset Management */
         unsigned long   cm;             /* Clock Management */
         unsigned long   cm2;
-        unsigned long   uart1_phys;
-        unsigned long   uart2_phys;
-        unsigned long   uart3_phys;
-        unsigned long   uart4_phys;
 };
 
 void omap2_set_globals_242x(void);
 void omap2_set_globals_243x(void);
 void omap2_set_globals_3xxx(void);
 void omap2_set_globals_443x(void);
+void omap2_set_globals_ti816x(void);
 
 /* These get called from omap2_set_globals_xxxx(), do not call these */
 void omap2_set_globals_tap(struct omap_globals *);
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 3fd8b4055727..8198bb6cdb5e 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -5,7 +5,7 @@
  *
  * Copyright (C) 2004, 2008 Nokia Corporation
  *
- * Copyright (C) 2009 Texas Instruments.
+ * Copyright (C) 2009-11 Texas Instruments.
  *
  * Written by Tony Lindgren <tony.lindgren@nokia.com>
  *
@@ -105,6 +105,12 @@ static inline int is_omap ##subclass (void)		\
         return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
 }
 
+#define IS_TI_SUBCLASS(subclass, id)                    \
+static inline int is_ti ##subclass (void)               \
+{                                                       \
+        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
+}
+
 IS_OMAP_CLASS(7xx, 0x07)
 IS_OMAP_CLASS(15xx, 0x15)
 IS_OMAP_CLASS(16xx, 0x16)
@@ -118,6 +124,8 @@ IS_OMAP_SUBCLASS(343x, 0x343)
 IS_OMAP_SUBCLASS(363x, 0x363)
 IS_OMAP_SUBCLASS(443x, 0x443)
 
+IS_TI_SUBCLASS(816x, 0x816)
+
 #define cpu_is_omap7xx()                0
 #define cpu_is_omap15xx()               0
 #define cpu_is_omap16xx()               0
@@ -126,6 +134,7 @@ IS_OMAP_SUBCLASS(443x, 0x443)
 #define cpu_is_omap243x()               0
 #define cpu_is_omap34xx()               0
 #define cpu_is_omap343x()               0
+#define cpu_is_ti816x()                 0
 #define cpu_is_omap44xx()               0
 #define cpu_is_omap443x()               0
 
@@ -170,11 +179,11 @@ IS_OMAP_SUBCLASS(443x, 0x443)
 #  undef  cpu_is_omap24xx
 #  define cpu_is_omap24xx()             is_omap24xx()
 # endif
-# if defined (CONFIG_ARCH_OMAP2420)
+# if defined (CONFIG_SOC_OMAP2420)
 #  undef  cpu_is_omap242x
 #  define cpu_is_omap242x()             is_omap242x()
 # endif
-# if defined (CONFIG_ARCH_OMAP2430)
+# if defined (CONFIG_SOC_OMAP2430)
 #  undef  cpu_is_omap243x
 #  define cpu_is_omap243x()             is_omap243x()
 # endif
@@ -189,11 +198,11 @@ IS_OMAP_SUBCLASS(443x, 0x443)
 #  undef  cpu_is_omap24xx
 #  define cpu_is_omap24xx()             1
 # endif
-# if defined(CONFIG_ARCH_OMAP2420)
+# if defined(CONFIG_SOC_OMAP2420)
 #  undef  cpu_is_omap242x
 #  define cpu_is_omap242x()             1
 # endif
-# if defined(CONFIG_ARCH_OMAP2430)
+# if defined(CONFIG_SOC_OMAP2430)
 #  undef  cpu_is_omap243x
 #  define cpu_is_omap243x()             1
 # endif
@@ -201,7 +210,7 @@ IS_OMAP_SUBCLASS(443x, 0x443)
 #  undef  cpu_is_omap34xx
 #  define cpu_is_omap34xx()             1
 # endif
-# if defined(CONFIG_ARCH_OMAP3430)
+# if defined(CONFIG_SOC_OMAP3430)
 #  undef  cpu_is_omap343x
 #  define cpu_is_omap343x()             1
 # endif
@@ -330,6 +339,7 @@ IS_OMAP_TYPE(3517, 0x3517)
 # undef cpu_is_omap3530
 # undef cpu_is_omap3505
 # undef cpu_is_omap3517
+# undef cpu_is_ti816x
 # define cpu_is_omap3430()              is_omap3430()
 # define cpu_is_omap3503()              (cpu_is_omap3430() &&           \
                                                 (!omap3_has_iva()) &&   \
@@ -345,6 +355,7 @@ IS_OMAP_TYPE(3517, 0x3517)
 # define cpu_is_omap3517()              is_omap3517()
 # undef cpu_is_omap3630
 # define cpu_is_omap3630()              is_omap363x()
+# define cpu_is_ti816x()                is_ti816x()
 #endif
 
 # if defined(CONFIG_ARCH_OMAP4)
@@ -389,9 +400,15 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define OMAP3505_REV(v)         (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
 #define OMAP3517_REV(v)         (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
 
+#define TI816X_CLASS            0x81600034
+#define TI8168_REV_ES1_0        TI816X_CLASS
+#define TI8168_REV_ES1_1        (TI816X_CLASS | (OMAP_REVBITS_01 << 8))
+
 #define OMAP443X_CLASS          0x44300044
-#define OMAP4430_REV_ES1_0      OMAP443X_CLASS
-#define OMAP4430_REV_ES2_0      0x44301044
+#define OMAP4430_REV_ES1_0      (OMAP443X_CLASS | (0x10 << 8))
+#define OMAP4430_REV_ES2_0      (OMAP443X_CLASS | (0x20 << 8))
+#define OMAP4430_REV_ES2_1      (OMAP443X_CLASS | (0x21 << 8))
+#define OMAP4430_REV_ES2_2      (OMAP443X_CLASS | (0x22 << 8))
 
 /*
  * omap_chip bits
@@ -419,11 +436,16 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define CHIP_IS_OMAP3630ES1_1           (1 << 9)
 #define CHIP_IS_OMAP3630ES1_2           (1 << 10)
 #define CHIP_IS_OMAP4430ES2             (1 << 11)
+#define CHIP_IS_OMAP4430ES2_1           (1 << 12)
+#define CHIP_IS_OMAP4430ES2_2           (1 << 13)
+#define CHIP_IS_TI816X                  (1 << 14)
 
 #define CHIP_IS_OMAP24XX                (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
 
-#define CHIP_IS_OMAP4430                (CHIP_IS_OMAP4430ES1 | \
-                                                 CHIP_IS_OMAP4430ES2)
+#define CHIP_IS_OMAP4430                (CHIP_IS_OMAP4430ES1 |          \
+                                         CHIP_IS_OMAP4430ES2 |          \
+                                         CHIP_IS_OMAP4430ES2_1 |        \
+                                         CHIP_IS_OMAP4430ES2_2)
 
 /*
  * "GE" here represents "greater than or equal to" in terms of ES
@@ -455,6 +477,7 @@ extern u32 omap3_features;
 #define OMAP3_HAS_ISP                   BIT(4)
 #define OMAP3_HAS_192MHZ_CLK            BIT(5)
 #define OMAP3_HAS_IO_WAKEUP             BIT(6)
+#define OMAP3_HAS_SDRC                  BIT(7)
 
 #define OMAP3_HAS_FEATURE(feat,flag)                    \
 static inline unsigned int omap3_has_ ##feat(void)      \
@@ -469,5 +492,6 @@ OMAP3_HAS_FEATURE(neon, NEON)
 OMAP3_HAS_FEATURE(isp, ISP)
 OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
 OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
+OMAP3_HAS_FEATURE(sdrc, SDRC)
 
 #endif
diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h
index 537f4e449f50..5e04ddc18fa8 100644
--- a/arch/arm/plat-omap/include/plat/display.h
+++ b/arch/arm/plat-omap/include/plat/display.h
@@ -23,6 +23,7 @@
 #include <linux/list.h>
 #include <linux/kobject.h>
 #include <linux/device.h>
+#include <linux/platform_device.h>
 #include <asm/atomic.h>
 
 #define DISPC_IRQ_FRAMEDONE             (1 << 0)
@@ -57,6 +58,7 @@ enum omap_display_type {
         OMAP_DISPLAY_TYPE_SDI           = 1 << 2,
         OMAP_DISPLAY_TYPE_DSI           = 1 << 3,
         OMAP_DISPLAY_TYPE_VENC          = 1 << 4,
+        OMAP_DISPLAY_TYPE_HDMI          = 1 << 5,
 };
 
 enum omap_plane {
@@ -226,6 +228,23 @@ struct omap_dss_board_info {
         struct omap_dss_device *default_device;
 };
 
+#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
+/* Init with the board info */
+extern int omap_display_init(struct omap_dss_board_info *board_data);
+#else
+static inline int omap_display_init(struct omap_dss_board_info *board_data)
+{
+        return 0;
+}
+#endif
+
+struct omap_display_platform_data {
+        struct omap_dss_board_info *board_data;
+        /* TODO: Additional members to be added when PM is considered */
+
+        bool (*opt_clock_available)(const char *clk_role);
+};
+
 struct omap_video_timings {
         /* Unit: pixels */
         u16 x_res;
@@ -385,8 +404,8 @@ struct omap_dss_device {
                         struct {
                                 u16 regn;
                                 u16 regm;
-                                u16 regm3;
-                                u16 regm4;
+                                u16 regm_dispc;
+                                u16 regm_dsi;
 
                                 u16 lp_clk_div;
 
@@ -544,6 +563,9 @@ int omap_dsi_update(struct omap_dss_device *dssdev,
                 int channel,
                 u16 x, u16 y, u16 w, u16 h,
                 void (*callback)(int, void *), void *data);
+int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
+int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
+void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
 
 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev);
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index dfa3aff9761b..d6c70d2f4030 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -3,6 +3,12 @@
  *
  * OMAP Dual-Mode Timers
  *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Tarun Kanti DebBarma <tarun.kanti@ti.com>
+ * Thara Gopinath <thara@ti.com>
+ *
+ * Platform device conversion and hwmod support.
+ *
  * Copyright (C) 2005 Nokia Corporation
  * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
  * PWM and clock framwork support by Timo Teras.
@@ -44,6 +50,11 @@
 #define OMAP_TIMER_TRIGGER_OVERFLOW             0x01
 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
 
+/*
+ * IP revision identifier so that Highlander IP
+ * in OMAP4 can be distinguished.
+ */
+#define OMAP_TIMER_IP_VERSION_1                        0x1
 struct omap_dm_timer;
 extern struct omap_dm_timer *gptimer_wakeup;
 extern struct sys_timer omap_timer;
diff --git a/arch/arm/plat-omap/include/plat/fpga.h b/arch/arm/plat-omap/include/plat/fpga.h
index ae39bcb3f5ba..bd3c6324ae1f 100644
--- a/arch/arm/plat-omap/include/plat/fpga.h
+++ b/arch/arm/plat-omap/include/plat/fpga.h
@@ -30,18 +30,18 @@ extern void omap1510_fpga_init_irq(void);
  * ---------------------------------------------------------------------------
  */
 /* maps in the FPGA registers and the ETHR registers */
-#define H2P2_DBG_FPGA_BASE              IOMEM(0xE8000000)       /* VA */
+#define H2P2_DBG_FPGA_BASE              0xE8000000              /* VA */
 #define H2P2_DBG_FPGA_SIZE              SZ_4K                   /* SIZE */
 #define H2P2_DBG_FPGA_START             0x04000000              /* PA */
 
 #define H2P2_DBG_FPGA_ETHR_START        (H2P2_DBG_FPGA_START + 0x300)
-#define H2P2_DBG_FPGA_FPGA_REV          (H2P2_DBG_FPGA_BASE + 0x10)     /* FPGA Revision */
-#define H2P2_DBG_FPGA_BOARD_REV         (H2P2_DBG_FPGA_BASE + 0x12)     /* Board Revision */
-#define H2P2_DBG_FPGA_GPIO              (H2P2_DBG_FPGA_BASE + 0x14)     /* GPIO outputs */
-#define H2P2_DBG_FPGA_LEDS              (H2P2_DBG_FPGA_BASE + 0x16)     /* LEDs outputs */
-#define H2P2_DBG_FPGA_MISC_INPUTS       (H2P2_DBG_FPGA_BASE + 0x18)     /* Misc inputs */
-#define H2P2_DBG_FPGA_LAN_STATUS        (H2P2_DBG_FPGA_BASE + 0x1A)     /* LAN Status line */
-#define H2P2_DBG_FPGA_LAN_RESET         (H2P2_DBG_FPGA_BASE + 0x1C)     /* LAN Reset line */
+#define H2P2_DBG_FPGA_FPGA_REV          IOMEM(H2P2_DBG_FPGA_BASE + 0x10)        /* FPGA Revision */
+#define H2P2_DBG_FPGA_BOARD_REV         IOMEM(H2P2_DBG_FPGA_BASE + 0x12)        /* Board Revision */
+#define H2P2_DBG_FPGA_GPIO              IOMEM(H2P2_DBG_FPGA_BASE + 0x14)        /* GPIO outputs */
+#define H2P2_DBG_FPGA_LEDS              IOMEM(H2P2_DBG_FPGA_BASE + 0x16)        /* LEDs outputs */
+#define H2P2_DBG_FPGA_MISC_INPUTS       IOMEM(H2P2_DBG_FPGA_BASE + 0x18)        /* Misc inputs */
+#define H2P2_DBG_FPGA_LAN_STATUS        IOMEM(H2P2_DBG_FPGA_BASE + 0x1A)        /* LAN Status line */
+#define H2P2_DBG_FPGA_LAN_RESET         IOMEM(H2P2_DBG_FPGA_BASE + 0x1C)        /* LAN Reset line */
 
 /* NOTE:  most boards don't have a static mapping for the FPGA ... */
 struct h2p2_dbg_fpga {
@@ -81,55 +81,55 @@ struct h2p2_dbg_fpga {
  *  OMAP-1510 FPGA
  * ---------------------------------------------------------------------------
  */
-#define OMAP1510_FPGA_BASE              IOMEM(0xE8000000)       /* VA */
+#define OMAP1510_FPGA_BASE              0xE8000000              /* VA */
 #define OMAP1510_FPGA_SIZE              SZ_4K
 #define OMAP1510_FPGA_START             0x08000000              /* PA */
 
 /* Revision */
-#define OMAP1510_FPGA_REV_LOW                   (OMAP1510_FPGA_BASE + 0x0)
-#define OMAP1510_FPGA_REV_HIGH                  (OMAP1510_FPGA_BASE + 0x1)
+#define OMAP1510_FPGA_REV_LOW                   IOMEM(OMAP1510_FPGA_BASE + 0x0)
+#define OMAP1510_FPGA_REV_HIGH                  IOMEM(OMAP1510_FPGA_BASE + 0x1)
 
-#define OMAP1510_FPGA_LCD_PANEL_CONTROL         (OMAP1510_FPGA_BASE + 0x2)
-#define OMAP1510_FPGA_LED_DIGIT                 (OMAP1510_FPGA_BASE + 0x3)
-#define INNOVATOR_FPGA_HID_SPI                  (OMAP1510_FPGA_BASE + 0x4)
-#define OMAP1510_FPGA_POWER                     (OMAP1510_FPGA_BASE + 0x5)
+#define OMAP1510_FPGA_LCD_PANEL_CONTROL         IOMEM(OMAP1510_FPGA_BASE + 0x2)
+#define OMAP1510_FPGA_LED_DIGIT                 IOMEM(OMAP1510_FPGA_BASE + 0x3)
+#define INNOVATOR_FPGA_HID_SPI                  IOMEM(OMAP1510_FPGA_BASE + 0x4)
+#define OMAP1510_FPGA_POWER                     IOMEM(OMAP1510_FPGA_BASE + 0x5)
 
 /* Interrupt status */
-#define OMAP1510_FPGA_ISR_LO                    (OMAP1510_FPGA_BASE + 0x6)
-#define OMAP1510_FPGA_ISR_HI                    (OMAP1510_FPGA_BASE + 0x7)
+#define OMAP1510_FPGA_ISR_LO                    IOMEM(OMAP1510_FPGA_BASE + 0x6)
+#define OMAP1510_FPGA_ISR_HI                    IOMEM(OMAP1510_FPGA_BASE + 0x7)
 
 /* Interrupt mask */
-#define OMAP1510_FPGA_IMR_LO                    (OMAP1510_FPGA_BASE + 0x8)
-#define OMAP1510_FPGA_IMR_HI                    (OMAP1510_FPGA_BASE + 0x9)
+#define OMAP1510_FPGA_IMR_LO                    IOMEM(OMAP1510_FPGA_BASE + 0x8)
+#define OMAP1510_FPGA_IMR_HI                    IOMEM(OMAP1510_FPGA_BASE + 0x9)
 
 /* Reset registers */
-#define OMAP1510_FPGA_HOST_RESET                (OMAP1510_FPGA_BASE + 0xa)
-#define OMAP1510_FPGA_RST                       (OMAP1510_FPGA_BASE + 0xb)
-
-#define OMAP1510_FPGA_AUDIO                     (OMAP1510_FPGA_BASE + 0xc)
-#define OMAP1510_FPGA_DIP                       (OMAP1510_FPGA_BASE + 0xe)
-#define OMAP1510_FPGA_FPGA_IO                   (OMAP1510_FPGA_BASE + 0xf)
-#define OMAP1510_FPGA_UART1                     (OMAP1510_FPGA_BASE + 0x14)
-#define OMAP1510_FPGA_UART2                     (OMAP1510_FPGA_BASE + 0x15)
-#define OMAP1510_FPGA_OMAP1510_STATUS           (OMAP1510_FPGA_BASE + 0x16)
-#define OMAP1510_FPGA_BOARD_REV                 (OMAP1510_FPGA_BASE + 0x18)
-#define OMAP1510P1_PPT_DATA                     (OMAP1510_FPGA_BASE + 0x100)
-#define OMAP1510P1_PPT_STATUS                   (OMAP1510_FPGA_BASE + 0x101)
-#define OMAP1510P1_PPT_CONTROL                  (OMAP1510_FPGA_BASE + 0x102)
-
-#define OMAP1510_FPGA_TOUCHSCREEN               (OMAP1510_FPGA_BASE + 0x204)
-
-#define INNOVATOR_FPGA_INFO                     (OMAP1510_FPGA_BASE + 0x205)
-#define INNOVATOR_FPGA_LCD_BRIGHT_LO            (OMAP1510_FPGA_BASE + 0x206)
-#define INNOVATOR_FPGA_LCD_BRIGHT_HI            (OMAP1510_FPGA_BASE + 0x207)
-#define INNOVATOR_FPGA_LED_GRN_LO               (OMAP1510_FPGA_BASE + 0x208)
-#define INNOVATOR_FPGA_LED_GRN_HI               (OMAP1510_FPGA_BASE + 0x209)
-#define INNOVATOR_FPGA_LED_RED_LO               (OMAP1510_FPGA_BASE + 0x20a)
-#define INNOVATOR_FPGA_LED_RED_HI               (OMAP1510_FPGA_BASE + 0x20b)
-#define INNOVATOR_FPGA_CAM_USB_CONTROL          (OMAP1510_FPGA_BASE + 0x20c)
-#define INNOVATOR_FPGA_EXP_CONTROL              (OMAP1510_FPGA_BASE + 0x20d)
-#define INNOVATOR_FPGA_ISR2                     (OMAP1510_FPGA_BASE + 0x20e)
-#define INNOVATOR_FPGA_IMR2                     (OMAP1510_FPGA_BASE + 0x210)
+#define OMAP1510_FPGA_HOST_RESET                IOMEM(OMAP1510_FPGA_BASE + 0xa)
+#define OMAP1510_FPGA_RST                       IOMEM(OMAP1510_FPGA_BASE + 0xb)
+
+#define OMAP1510_FPGA_AUDIO                     IOMEM(OMAP1510_FPGA_BASE + 0xc)
+#define OMAP1510_FPGA_DIP                       IOMEM(OMAP1510_FPGA_BASE + 0xe)
+#define OMAP1510_FPGA_FPGA_IO                   IOMEM(OMAP1510_FPGA_BASE + 0xf)
+#define OMAP1510_FPGA_UART1                     IOMEM(OMAP1510_FPGA_BASE + 0x14)
+#define OMAP1510_FPGA_UART2                     IOMEM(OMAP1510_FPGA_BASE + 0x15)
+#define OMAP1510_FPGA_OMAP1510_STATUS           IOMEM(OMAP1510_FPGA_BASE + 0x16)
+#define OMAP1510_FPGA_BOARD_REV                 IOMEM(OMAP1510_FPGA_BASE + 0x18)
+#define OMAP1510P1_PPT_DATA                     IOMEM(OMAP1510_FPGA_BASE + 0x100)
+#define OMAP1510P1_PPT_STATUS                   IOMEM(OMAP1510_FPGA_BASE + 0x101)
+#define OMAP1510P1_PPT_CONTROL                  IOMEM(OMAP1510_FPGA_BASE + 0x102)
+
+#define OMAP1510_FPGA_TOUCHSCREEN               IOMEM(OMAP1510_FPGA_BASE + 0x204)
+
+#define INNOVATOR_FPGA_INFO                     IOMEM(OMAP1510_FPGA_BASE + 0x205)
+#define INNOVATOR_FPGA_LCD_BRIGHT_LO            IOMEM(OMAP1510_FPGA_BASE + 0x206)
+#define INNOVATOR_FPGA_LCD_BRIGHT_HI            IOMEM(OMAP1510_FPGA_BASE + 0x207)
+#define INNOVATOR_FPGA_LED_GRN_LO               IOMEM(OMAP1510_FPGA_BASE + 0x208)
+#define INNOVATOR_FPGA_LED_GRN_HI               IOMEM(OMAP1510_FPGA_BASE + 0x209)
+#define INNOVATOR_FPGA_LED_RED_LO               IOMEM(OMAP1510_FPGA_BASE + 0x20a)
+#define INNOVATOR_FPGA_LED_RED_HI               IOMEM(OMAP1510_FPGA_BASE + 0x20b)
+#define INNOVATOR_FPGA_CAM_USB_CONTROL          IOMEM(OMAP1510_FPGA_BASE + 0x20c)
+#define INNOVATOR_FPGA_EXP_CONTROL              IOMEM(OMAP1510_FPGA_BASE + 0x20d)
+#define INNOVATOR_FPGA_ISR2                     IOMEM(OMAP1510_FPGA_BASE + 0x20e)
+#define INNOVATOR_FPGA_IMR2                     IOMEM(OMAP1510_FPGA_BASE + 0x210)
 
 #define OMAP1510_FPGA_ETHR_START                (OMAP1510_FPGA_START + 0x300)
 
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 85ded598853e..12b316165037 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -41,6 +41,8 @@
 #define GPMC_NAND_ADDRESS       0x0000000b
 #define GPMC_NAND_DATA          0x0000000c
 
+#define GPMC_ENABLE_IRQ         0x0000000d
+
 /* ECC commands */
 #define GPMC_ECC_READ           0 /* Reset Hardware ECC for read */
 #define GPMC_ECC_WRITE          1 /* Reset Hardware ECC for write */
@@ -78,6 +80,19 @@
 #define WR_RD_PIN_MONITORING            0x00600000
 #define GPMC_PREFETCH_STATUS_FIFO_CNT(val)      ((val >> 24) & 0x7F)
 #define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
+#define GPMC_IRQ_FIFOEVENTENABLE        0x01
+#define GPMC_IRQ_COUNT_EVENT            0x02
+
+#define PREFETCH_FIFOTHRESHOLD_MAX      0x40
+#define PREFETCH_FIFOTHRESHOLD(val)     ((val) << 8)
+
+enum omap_ecc {
+                /* 1-bit ecc: stored at end of spare area */
+        OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
+        OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
+                /* 1-bit ecc: stored at begining of spare area as romcode */
+        OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
+};
 
 /*
  * Note that all values in this struct are in nanoseconds except sync_clk
@@ -130,12 +145,11 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
 extern void gpmc_cs_free(int cs);
 extern int gpmc_cs_set_reserved(int cs, int reserved);
 extern int gpmc_cs_reserved(int cs);
-extern int gpmc_prefetch_enable(int cs, int dma_mode,
+extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
                                         unsigned int u32_count, int is_write);
 extern int gpmc_prefetch_reset(int cs);
 extern void omap3_gpmc_save_context(void);
 extern void omap3_gpmc_restore_context(void);
-extern void gpmc_init(void);
 extern int gpmc_read_status(int cmd);
 extern int gpmc_cs_configure(int cs, int cmd, int wval);
 extern int gpmc_nand_read(int cs, int cmd);
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index d5b26adfb890..e87efe1499b8 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -286,5 +286,6 @@
 #include <plat/omap24xx.h>
 #include <plat/omap34xx.h>
 #include <plat/omap44xx.h>
+#include <plat/ti816x.h>
 
 #endif  /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index ef4106c13183..d72ec85c97e6 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -259,7 +259,7 @@ struct omap_sdrc_params;
 extern void omap1_map_common_io(void);
 extern void omap1_init_common_hw(void);
 
-#ifdef CONFIG_ARCH_OMAP2420
+#ifdef CONFIG_SOC_OMAP2420
 extern void omap242x_map_common_io(void);
 #else
 static inline void omap242x_map_common_io(void)
@@ -267,7 +267,7 @@ static inline void omap242x_map_common_io(void)
 }
 #endif
 
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 extern void omap243x_map_common_io(void);
 #else
 static inline void omap243x_map_common_io(void)
@@ -283,6 +283,14 @@ static inline void omap34xx_map_common_io(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_OMAPTI816X
+extern void omapti816x_map_common_io(void);
+#else
+static inline void omapti816x_map_common_io(void)
+{
+}
+#endif
+
 #ifdef CONFIG_ARCH_OMAP4
 extern void omap44xx_map_common_io(void);
 #else
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 69230d685538..174f1b9c8c03 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -31,6 +31,7 @@ struct iommu {
         struct clk      *clk;
         void __iomem    *regbase;
         struct device   *dev;
+        void            *isr_priv;
 
         unsigned int    refcount;
         struct mutex    iommu_lock;     /* global for this whole object */
@@ -47,7 +48,7 @@ struct iommu {
         struct list_head        mmap;
         struct mutex            mmap_lock; /* protect mmap */
 
-        int (*isr)(struct iommu *obj);
+        int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, void *priv);
 
         void *ctx; /* iommu context: registres saved area */
         u32 da_start;
@@ -109,6 +110,13 @@ struct iommu_platform_data {
         u32 da_end;
 };
 
+/* IOMMU errors */
+#define OMAP_IOMMU_ERR_TLB_MISS         (1 << 0)
+#define OMAP_IOMMU_ERR_TRANS_FAULT      (1 << 1)
+#define OMAP_IOMMU_ERR_EMU_MISS         (1 << 2)
+#define OMAP_IOMMU_ERR_TBLWALK_FAULT    (1 << 3)
+#define OMAP_IOMMU_ERR_MULTIHIT_FAULT   (1 << 4)
+
 #if defined(CONFIG_ARCH_OMAP1)
 #error "iommu for this processor not implemented yet"
 #else
@@ -154,11 +162,17 @@ extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
 extern void flush_iotlb_all(struct iommu *obj);
 
 extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e);
+extern void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd,
+                                   u32 **ppte);
 extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
 
 extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end);
 extern struct iommu *iommu_get(const char *name);
 extern void iommu_put(struct iommu *obj);
+extern int iommu_set_isr(const char *name,
+                         int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs,
+                                    void *priv),
+                         void *isr_priv);
 
 extern void iommu_save_ctx(struct iommu *obj);
 extern void iommu_restore_ctx(struct iommu *obj);
diff --git a/arch/arm/plat-omap/include/plat/iovmm.h b/arch/arm/plat-omap/include/plat/iovmm.h
index bdc7ce5d7a4a..32a2f6c4d39e 100644
--- a/arch/arm/plat-omap/include/plat/iovmm.h
+++ b/arch/arm/plat-omap/include/plat/iovmm.h
@@ -71,8 +71,6 @@ struct iovm_struct {
 #define IOVMF_LINEAR_MASK       (3 << (2 + IOVMF_SW_SHIFT))
 
 #define IOVMF_DA_FIXED          (1 << (4 + IOVMF_SW_SHIFT))
-#define IOVMF_DA_ANON           (2 << (4 + IOVMF_SW_SHIFT))
-#define IOVMF_DA_MASK           (3 << (4 + IOVMF_SW_SHIFT))
 
 
 extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da);
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 2910de921c52..d77928370463 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -315,9 +315,12 @@
 #define INT_34XX_SSM_ABORT_IRQ  6
 #define INT_34XX_SYS_NIRQ       7
 #define INT_34XX_D2D_FW_IRQ     8
+#define INT_34XX_L3_DBG_IRQ     9
+#define INT_34XX_L3_APP_IRQ     10
 #define INT_34XX_PRCM_MPU_IRQ   11
 #define INT_34XX_MCBSP1_IRQ     16
 #define INT_34XX_MCBSP2_IRQ     17
+#define INT_34XX_GPMC_IRQ       20
 #define INT_34XX_MCBSP3_IRQ     22
 #define INT_34XX_MCBSP4_IRQ     23
 #define INT_34XX_CAM_IRQ        24
@@ -411,7 +414,13 @@
 #define TWL_IRQ_END             TWL6030_IRQ_END
 #endif
 
-#define NR_IRQS                 TWL_IRQ_END
+/* GPMC related */
+#define OMAP_GPMC_IRQ_BASE      (TWL_IRQ_END)
+#define OMAP_GPMC_NR_IRQS       7
+#define OMAP_GPMC_IRQ_END       (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
+
+
+#define NR_IRQS                 OMAP_GPMC_IRQ_END
 
 #define OMAP_IRQ_BIT(irq)       (1 << ((irq) % 32))
 
diff --git a/arch/arm/plat-omap/include/plat/l3_2xxx.h b/arch/arm/plat-omap/include/plat/l3_2xxx.h
new file mode 100644
index 000000000000..b8b5641379b0
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/l3_2xxx.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Sumit Semwal
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
+
+/* L3 CONNIDs */
+/* Display Sub system (DSS) */
+#define OMAP2_L3_CORE_FW_CONNID_DSS                     8
+
+#endif
diff --git a/arch/arm/plat-omap/include/plat/l3_3xxx.h b/arch/arm/plat-omap/include/plat/l3_3xxx.h
new file mode 100644
index 000000000000..cde1938c5f82
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/l3_3xxx.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/plat-omap/include/plat/l3_3xxx.h - L3 firewall definitions
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Sumit Semwal
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
+
+/* L3 Initiator IDs */
+/* Display Sub system (DSS) */
+#define OMAP3_L3_CORE_FW_INIT_ID_DSS                    29
+
+#endif
diff --git a/arch/arm/plat-omap/include/plat/l4_2xxx.h b/arch/arm/plat-omap/include/plat/l4_2xxx.h
new file mode 100644
index 000000000000..3f39cf8a35c6
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/l4_2xxx.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/plat-omap/include/plat/l4_2xxx.h - L4 firewall definitions
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Sumit Semwal
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
+
+/* L4 CORE */
+/* Display Sub system (DSS) */
+#define OMAP2420_L4_CORE_FW_DSS_CORE_REGION                     28
+#define OMAP2420_L4_CORE_FW_DSS_DISPC_REGION                    29
+#define OMAP2420_L4_CORE_FW_DSS_RFBI_REGION                     30
+#define OMAP2420_L4_CORE_FW_DSS_VENC_REGION                     31
+#define OMAP2420_L4_CORE_FW_DSS_TA_REGION                       32
+
+#endif
diff --git a/arch/arm/plat-omap/include/plat/l4_3xxx.h b/arch/arm/plat-omap/include/plat/l4_3xxx.h
index 5e1949375422..881a858b1ffc 100644
--- a/arch/arm/plat-omap/include/plat/l4_3xxx.h
+++ b/arch/arm/plat-omap/include/plat/l4_3xxx.h
@@ -21,4 +21,14 @@
 #define OMAP3_L4_CORE_FW_I2C3_REGION                            73
 #define OMAP3_L4_CORE_FW_I2C3_TA_REGION                         74
 
+/* Display Sub system (DSS) */
+#define OMAP3_L4_CORE_FW_DSS_PROT_GROUP                         2
+
+#define OMAP3_L4_CORE_FW_DSS_DSI_REGION                         104
+#define OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION                     3
+#define OMAP3_L4_CORE_FW_DSS_CORE_REGION                        4
+#define OMAP3_L4_CORE_FW_DSS_DISPC_REGION                       4
+#define OMAP3_L4_CORE_FW_DSS_RFBI_REGION                        5
+#define OMAP3_L4_CORE_FW_DSS_VENC_REGION                        6
+#define OMAP3_L4_CORE_FW_DSS_TA_REGION                          7
 #endif
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index b87d83ccd545..f8f690ab2997 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -37,6 +37,10 @@ static struct platform_device omap_mcbsp##port_nr = {	\
         .id     = OMAP_MCBSP##port_nr,                  \
 }
 
+#define MCBSP_CONFIG_TYPE2      0x2
+#define MCBSP_CONFIG_TYPE3      0x3
+#define MCBSP_CONFIG_TYPE4      0x4
+
 #define OMAP7XX_MCBSP1_BASE     0xfffb1000
 #define OMAP7XX_MCBSP2_BASE     0xfffb1800
 
@@ -48,32 +52,14 @@ static struct platform_device omap_mcbsp##port_nr = {	\
 #define OMAP1610_MCBSP2_BASE    0xfffb1000
 #define OMAP1610_MCBSP3_BASE    0xe1017000
 
-#define OMAP24XX_MCBSP1_BASE    0x48074000
-#define OMAP24XX_MCBSP2_BASE    0x48076000
-#define OMAP2430_MCBSP3_BASE    0x4808c000
-#define OMAP2430_MCBSP4_BASE    0x4808e000
-#define OMAP2430_MCBSP5_BASE    0x48096000
-
-#define OMAP34XX_MCBSP1_BASE    0x48074000
-#define OMAP34XX_MCBSP2_BASE    0x49022000
-#define OMAP34XX_MCBSP2_ST_BASE 0x49028000
-#define OMAP34XX_MCBSP3_BASE    0x49024000
-#define OMAP34XX_MCBSP3_ST_BASE 0x4902A000
-#define OMAP34XX_MCBSP3_BASE    0x49024000
-#define OMAP34XX_MCBSP4_BASE    0x49026000
-#define OMAP34XX_MCBSP5_BASE    0x48096000
-
-#define OMAP44XX_MCBSP1_BASE    0x49022000
-#define OMAP44XX_MCBSP2_BASE    0x49024000
-#define OMAP44XX_MCBSP3_BASE    0x49026000
-#define OMAP44XX_MCBSP4_BASE    0x48096000
-
-#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+#ifdef CONFIG_ARCH_OMAP1
 
 #define OMAP_MCBSP_REG_DRR2     0x00
 #define OMAP_MCBSP_REG_DRR1     0x02
 #define OMAP_MCBSP_REG_DXR2     0x04
 #define OMAP_MCBSP_REG_DXR1     0x06
+#define OMAP_MCBSP_REG_DRR      0x02
+#define OMAP_MCBSP_REG_DXR      0x06
 #define OMAP_MCBSP_REG_SPCR2    0x08
 #define OMAP_MCBSP_REG_SPCR1    0x0a
 #define OMAP_MCBSP_REG_RCR2     0x0c
@@ -106,13 +92,6 @@ static struct platform_device omap_mcbsp##port_nr = {	\
 #define OMAP_MCBSP_REG_XCCR     0x00
 #define OMAP_MCBSP_REG_RCCR     0x00
 
-#define AUDIO_MCBSP_DATAWRITE   (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
-#define AUDIO_MCBSP_DATAREAD    (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
-
-#define AUDIO_MCBSP             OMAP_MCBSP1
-#define AUDIO_DMA_TX            OMAP_DMA_MCBSP1_TX
-#define AUDIO_DMA_RX            OMAP_DMA_MCBSP1_RX
-
 #else
 
 #define OMAP_MCBSP_REG_DRR2     0x00
@@ -168,13 +147,6 @@ static struct platform_device omap_mcbsp##port_nr = {	\
 #define OMAP_ST_REG_SFIRCR      0x28
 #define OMAP_ST_REG_SSELCR      0x2C
 
-#define AUDIO_MCBSP_DATAWRITE   (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
-#define AUDIO_MCBSP_DATAREAD    (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
-
-#define AUDIO_MCBSP             OMAP_MCBSP2
-#define AUDIO_DMA_TX            OMAP24XX_DMA_MCBSP2_TX
-#define AUDIO_DMA_RX            OMAP24XX_DMA_MCBSP2_RX
-
 #endif
 
 /************************** McBSP SPCR1 bit definitions ***********************/
@@ -428,8 +400,9 @@ struct omap_mcbsp_platform_data {
 #ifdef CONFIG_ARCH_OMAP3
         /* Sidetone block for McBSP 2 and 3 */
         unsigned long phys_base_st;
-        u16 buffer_size;
 #endif
+        u16 buffer_size;
+        unsigned int mcbsp_config_type;
 };
 
 struct omap_mcbsp_st_data {
@@ -445,6 +418,7 @@ struct omap_mcbsp_st_data {
 struct omap_mcbsp {
         struct device *dev;
         unsigned long phys_base;
+        unsigned long phys_dma_base;
         void __iomem *io_base;
         u8 id;
         u8 free;
@@ -471,7 +445,6 @@ struct omap_mcbsp {
         /* Protect the field .free, while checking if the mcbsp is in use */
         spinlock_t lock;
         struct omap_mcbsp_platform_data *pdata;
-        struct clk *iclk;
         struct clk *fclk;
 #ifdef CONFIG_ARCH_OMAP3
         struct omap_mcbsp_st_data *st_data;
@@ -480,7 +453,17 @@ struct omap_mcbsp {
         u16 max_rx_thres;
 #endif
         void *reg_cache;
+        unsigned int mcbsp_config_type;
 };
+
+/**
+ * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod
+ * @sidetone: name of the sidetone device
+ */
+struct omap_mcbsp_dev_attr {
+        const char *sidetone;
+};
+
 extern struct omap_mcbsp **mcbsp_ptr;
 extern int omap_mcbsp_count, omap_mcbsp_cache_size;
 
@@ -488,8 +471,8 @@ extern int omap_mcbsp_count, omap_mcbsp_cache_size;
 #define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
 
 int omap_mcbsp_init(void);
-void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
-                                        int size);
+void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
+                        struct omap_mcbsp_platform_data *config, int size);
 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
 #ifdef CONFIG_ARCH_OMAP3
 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
@@ -539,6 +522,9 @@ int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
 void omap2_mcbsp1_mux_clkr_src(u8 mux);
 void omap2_mcbsp1_mux_fsr_src(u8 mux);
 
+int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream);
+int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream);
+
 #ifdef CONFIG_ARCH_OMAP3
 /* Sidetone specific API */
 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
index 1254e4945b6f..3d51b18131cc 100644
--- a/arch/arm/plat-omap/include/plat/mcspi.h
+++ b/arch/arm/plat-omap/include/plat/mcspi.h
@@ -1,8 +1,19 @@
 #ifndef _OMAP2_MCSPI_H
 #define _OMAP2_MCSPI_H
 
+#define OMAP2_MCSPI_REV 0
+#define OMAP3_MCSPI_REV 1
+#define OMAP4_MCSPI_REV 2
+
+#define OMAP4_MCSPI_REG_OFFSET 0x100
+
 struct omap2_mcspi_platform_config {
         unsigned short  num_cs;
+        unsigned int regs_offset;
+};
+
+struct omap2_mcspi_dev_attr {
+        unsigned short num_chipselect;
 };
 
 struct omap2_mcspi_device_config {
diff --git a/arch/arm/plat-omap/include/plat/memory.h b/arch/arm/plat-omap/include/plat/memory.h
index f8d922fb5584..e6720aa2d553 100644
--- a/arch/arm/plat-omap/include/plat/memory.h
+++ b/arch/arm/plat-omap/include/plat/memory.h
@@ -37,9 +37,9 @@
  * Physical DRAM offset.
  */
 #if defined(CONFIG_ARCH_OMAP1)
-#define PHYS_OFFSET             UL(0x10000000)
+#define PLAT_PHYS_OFFSET                UL(0x10000000)
 #else
-#define PHYS_OFFSET             UL(0x80000000)
+#define PLAT_PHYS_OFFSET                UL(0x80000000)
 #endif
 
 /*
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index f57f36abb07e..f38fef9f1310 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -24,25 +24,19 @@
 #define OMAP1_MMC2_BASE         0xfffb7c00      /* omap16xx only */
 
 #define OMAP24XX_NR_MMC         2
-#define OMAP34XX_NR_MMC         3
-#define OMAP44XX_NR_MMC         5
 #define OMAP2420_MMC_SIZE       OMAP1_MMC_SIZE
-#define OMAP3_HSMMC_SIZE        0x200
-#define OMAP4_HSMMC_SIZE        0x1000
 #define OMAP2_MMC1_BASE         0x4809c000
-#define OMAP2_MMC2_BASE         0x480b4000
-#define OMAP3_MMC3_BASE         0x480ad000
-#define OMAP4_MMC4_BASE         0x480d1000
-#define OMAP4_MMC5_BASE         0x480d5000
+
 #define OMAP4_MMC_REG_OFFSET    0x100
-#define HSMMC5                  (1 << 4)
-#define HSMMC4                  (1 << 3)
-#define HSMMC3                  (1 << 2)
-#define HSMMC2                  (1 << 1)
-#define HSMMC1                  (1 << 0)
 
 #define OMAP_MMC_MAX_SLOTS      2
 
+#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT   BIT(1)
+
+struct omap_mmc_dev_attr {
+        u8 flags;
+};
+
 struct omap_mmc_platform_data {
         /* back-link to device */
         struct device *dev;
@@ -71,6 +65,9 @@ struct omap_mmc_platform_data {
 
         u64 dma_mask;
 
+        /* Integrating attributes from the omap_hwmod layer */
+        u8 controller_flags;
+
         /* Register offset deviation */
         u16 reg_offset;
 
@@ -159,8 +156,7 @@ extern void omap_mmc_notify_cover_event(struct device *dev, int slot,
         defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
                                 int nr_controllers);
-void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
-                                int nr_controllers);
+void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data);
 int omap_mmc_add(const char *name, int id, unsigned long base,
                                 unsigned long size, unsigned int irq,
                                 struct omap_mmc_platform_data *data);
@@ -169,8 +165,7 @@ static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
                                 int nr_controllers)
 {
 }
-static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
-                                int nr_controllers)
+static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
 {
 }
 static inline int omap_mmc_add(const char *name, int id, unsigned long base,
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
index ffd909fa5287..999ffba2690c 100644
--- a/arch/arm/plat-omap/include/plat/multi.h
+++ b/arch/arm/plat-omap/include/plat/multi.h
@@ -66,7 +66,7 @@
 #  error "OMAP1 and OMAP2PLUS can't be selected at the same time"
 # endif
 #endif
-#ifdef CONFIG_ARCH_OMAP2420
+#ifdef CONFIG_SOC_OMAP2420
 # ifdef OMAP_NAME
 #  undef  MULTI_OMAP2
 #  define MULTI_OMAP2
@@ -74,7 +74,7 @@
 #  define OMAP_NAME omap2420
 # endif
 #endif
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 # ifdef OMAP_NAME
 #  undef  MULTI_OMAP2
 #  define MULTI_OMAP2
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index 6562cd082bb1..d86d1ecf0068 100644
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -8,8 +8,16 @@
  * published by the Free Software Foundation.
  */
 
+#include <plat/gpmc.h>
 #include <linux/mtd/partitions.h>
 
+enum nand_io {
+        NAND_OMAP_PREFETCH_POLLED = 0,  /* prefetch polled mode, default */
+        NAND_OMAP_POLLED,               /* polled mode, without prefetch */
+        NAND_OMAP_PREFETCH_DMA,         /* prefetch enabled sDMA mode */
+        NAND_OMAP_PREFETCH_IRQ          /* prefetch enabled irq mode */
+};
+
 struct omap_nand_platform_data {
         unsigned int            options;
         int                     cs;
@@ -20,8 +28,11 @@ struct omap_nand_platform_data {
         int                     (*nand_setup)(void);
         int                     (*dev_ready)(struct omap_nand_platform_data *);
         int                     dma_channel;
+        int                     gpmc_irq;
+        enum nand_io            xfer_type;
         unsigned long           phys_base;
         int                     devsize;
+        enum omap_ecc           ecc_opt;
 };
 
 /* minimum size for IO mapping */
diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h
index 98fc8b4a4cc4..b9e85886b9d6 100644
--- a/arch/arm/plat-omap/include/plat/omap34xx.h
+++ b/arch/arm/plat-omap/include/plat/omap34xx.h
@@ -56,8 +56,12 @@
 #define OMAP3430_ISP_RESZ_BASE          (OMAP3430_ISP_BASE + 0x1000)
 #define OMAP3430_ISP_SBL_BASE           (OMAP3430_ISP_BASE + 0x1200)
 #define OMAP3430_ISP_MMU_BASE           (OMAP3430_ISP_BASE + 0x1400)
-#define OMAP3430_ISP_CSI2A_BASE         (OMAP3430_ISP_BASE + 0x1800)
-#define OMAP3430_ISP_CSI2PHY_BASE       (OMAP3430_ISP_BASE + 0x1970)
+#define OMAP3430_ISP_CSI2A_REGS1_BASE   (OMAP3430_ISP_BASE + 0x1800)
+#define OMAP3430_ISP_CSIPHY2_BASE       (OMAP3430_ISP_BASE + 0x1970)
+#define OMAP3630_ISP_CSI2A_REGS2_BASE   (OMAP3430_ISP_BASE + 0x19C0)
+#define OMAP3630_ISP_CSI2C_REGS1_BASE   (OMAP3430_ISP_BASE + 0x1C00)
+#define OMAP3630_ISP_CSIPHY1_BASE       (OMAP3430_ISP_BASE + 0x1D70)
+#define OMAP3630_ISP_CSI2C_REGS2_BASE   (OMAP3430_ISP_BASE + 0x1DC0)
 
 #define OMAP3430_ISP_END                (OMAP3430_ISP_BASE         + 0x06F)
 #define OMAP3430_ISP_CBUFF_END          (OMAP3430_ISP_CBUFF_BASE   + 0x077)
@@ -69,8 +73,12 @@
 #define OMAP3430_ISP_RESZ_END           (OMAP3430_ISP_RESZ_BASE    + 0x0AB)
 #define OMAP3430_ISP_SBL_END            (OMAP3430_ISP_SBL_BASE     + 0x0FB)
 #define OMAP3430_ISP_MMU_END            (OMAP3430_ISP_MMU_BASE     + 0x06F)
-#define OMAP3430_ISP_CSI2A_END          (OMAP3430_ISP_CSI2A_BASE   + 0x16F)
-#define OMAP3430_ISP_CSI2PHY_END        (OMAP3430_ISP_CSI2PHY_BASE + 0x007)
+#define OMAP3430_ISP_CSI2A_REGS1_END    (OMAP3430_ISP_CSI2A_REGS1_BASE + 0x16F)
+#define OMAP3430_ISP_CSIPHY2_END        (OMAP3430_ISP_CSIPHY2_BASE + 0x00B)
+#define OMAP3630_ISP_CSI2A_REGS2_END    (OMAP3630_ISP_CSI2A_REGS2_BASE + 0x3F)
+#define OMAP3630_ISP_CSI2C_REGS1_END    (OMAP3630_ISP_CSI2C_REGS1_BASE + 0x16F)
+#define OMAP3630_ISP_CSIPHY1_END        (OMAP3630_ISP_CSIPHY1_BASE + 0x00B)
+#define OMAP3630_ISP_CSI2C_REGS2_END    (OMAP3630_ISP_CSI2C_REGS2_BASE + 0x3F)
 
 #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
 #define OMAP34XX_USBTLL_BASE    (L4_34XX_BASE + 0x62000)
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 1eee85a8abb3..1adea9c62984 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -1,7 +1,7 @@
 /*
  * omap_hwmod macros, structures
  *
- * Copyright (C) 2009-2010 Nokia Corporation
+ * Copyright (C) 2009-2011 Nokia Corporation
  * Paul Walmsley
  *
  * Created in collaboration with (alphabetical order): Benoît Cousson,
@@ -30,11 +30,11 @@
 #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
 
 #include <linux/kernel.h>
+#include <linux/init.h>
 #include <linux/list.h>
 #include <linux/ioport.h>
 #include <linux/spinlock.h>
 #include <plat/cpu.h>
-#include <plat/voltage.h>
 
 struct omap_device;
 
@@ -90,6 +90,9 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
 struct omap_hwmod_mux_info {
         int                             nr_pads;
         struct omap_device_pad          *pads;
+        int                             nr_pads_dynamic;
+        struct omap_device_pad          **pads_dynamic;
+        bool                            enabled;
 };
 
 /**
@@ -124,6 +127,7 @@ struct omap_hwmod_dma_info {
  * struct omap_hwmod_rst_info - IPs reset lines use by hwmod
  * @name: name of the reset line (module local name)
  * @rst_shift: Offset of the reset bit
+ * @st_shift: Offset of the reset status bit (OMAP2/3 only)
  *
  * @name should be something short, e.g., "cpu0" or "rst". It is defined
  * locally to the hwmod.
@@ -131,6 +135,7 @@ struct omap_hwmod_dma_info {
 struct omap_hwmod_rst_info {
         const char      *name;
         u8              rst_shift;
+        u8              st_shift;
 };
 
 /**
@@ -178,7 +183,8 @@ struct omap_hwmod_omap2_firewall {
 #define ADDR_TYPE_RT            (1 << 1)
 
 /**
- * struct omap_hwmod_addr_space - MPU address space handled by the hwmod
+ * struct omap_hwmod_addr_space - address space handled by the hwmod
+ * @name: name of the address space
  * @pa_start: starting physical address
  * @pa_end: ending physical address
  * @flags: (see omap_hwmod_addr_space.flags macros above)
@@ -187,6 +193,7 @@ struct omap_hwmod_omap2_firewall {
  * structure.  GPMC is one example.
  */
 struct omap_hwmod_addr_space {
+        const char *name;
         u32 pa_start;
         u32 pa_end;
         u8 flags;
@@ -370,9 +377,11 @@ struct omap_hwmod_omap4_prcm {
  *     of standby, rather than relying on module smart-standby
  * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
  *     SDRAM controller, etc. XXX probably belongs outside the main hwmod file
+ *     XXX Should be HWMOD_SETUP_NO_RESET
  * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
  *     controller, etc. XXX probably belongs outside the main hwmod file
- * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
+ *     XXX Should be HWMOD_SETUP_NO_IDLE
+ * HWMOD_NO_OCP_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
  *     when module is enabled, rather than the default, which is to
  *     enable autoidle
  * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
@@ -535,11 +544,12 @@ struct omap_hwmod {
         const struct omap_chip_id       omap_chip;
 };
 
-int omap_hwmod_init(struct omap_hwmod **ohs);
+int omap_hwmod_register(struct omap_hwmod **ohs);
 struct omap_hwmod *omap_hwmod_lookup(const char *name);
 int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
                         void *data);
-int omap_hwmod_late_init(void);
+
+int __init omap_hwmod_setup_one(const char *name);
 
 int omap_hwmod_enable(struct omap_hwmod *oh);
 int _omap_hwmod_enable(struct omap_hwmod *oh);
@@ -555,6 +565,7 @@ int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
 int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
 
 int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode);
+int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle);
 
 int omap_hwmod_reset(struct omap_hwmod *oh);
 void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
@@ -589,6 +600,8 @@ int omap_hwmod_for_each_by_class(const char *classname,
 int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state);
 u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
 
+int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);
+
 /*
  * Chip variant-specific hwmod init routines - XXX should be converted
  * to use initcalls once the initial boot ordering is straightened out
diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h
index 1b430d5fdd54..2858667d2e4f 100644
--- a/arch/arm/plat-omap/include/plat/onenand.h
+++ b/arch/arm/plat-omap/include/plat/onenand.h
@@ -15,12 +15,20 @@
 #define ONENAND_SYNC_READ       (1 << 0)
 #define ONENAND_SYNC_READWRITE  (1 << 1)
 
+struct onenand_freq_info {
+        u16                     maf_id;
+        u16                     dev_id;
+        u16                     ver_id;
+};
+
 struct omap_onenand_platform_data {
         int                     cs;
         int                     gpio_irq;
         struct mtd_partition    *parts;
         int                     nr_parts;
-        int                     (*onenand_setup)(void __iomem *, int freq);
+        int                     (*onenand_setup)(void __iomem *, int *freq_ptr);
+        int             (*get_freq)(const struct onenand_freq_info *freq_info,
+                                    bool *clk_dep);
         int                     dma_channel;
         u8                      flags;
         u8                      regulator_can_sleep;
diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h
index 2fdf8c80d390..267f43bb2a4e 100644
--- a/arch/arm/plat-omap/include/plat/prcm.h
+++ b/arch/arm/plat-omap/include/plat/prcm.h
@@ -28,7 +28,6 @@
 #define __ASM_ARM_ARCH_OMAP_PRCM_H
 
 u32 omap_prcm_get_reset_sources(void);
-void omap_prcm_arch_reset(char mode, const char *cmd);
 int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
                          const char *name);
 
diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
index efd87c8dda69..925b12b500dc 100644
--- a/arch/arm/plat-omap/include/plat/sdrc.h
+++ b/arch/arm/plat-omap/include/plat/sdrc.h
@@ -124,8 +124,14 @@ struct omap_sdrc_params {
         u32 mr;
 };
 
-void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                             struct omap_sdrc_params *sdrc_cs1);
+#else
+static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+                                          struct omap_sdrc_params *sdrc_cs1) {};
+#endif
+
 int omap2_sdrc_get_params(unsigned long r,
                           struct omap_sdrc_params **sdrc_cs0,
                           struct omap_sdrc_params **sdrc_cs1);
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index cec5d56db2eb..2723f9166ea2 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -27,7 +27,7 @@
  * 2. We assume printascii is called at least once before paging_init,
  *    and addruart has a chance to read OMAP_UART_INFO
  */
-#define OMAP_UART_INFO          (PHYS_OFFSET + 0x3ffc)
+#define OMAP_UART_INFO          (PLAT_PHYS_OFFSET + 0x3ffc)
 
 /* OMAP1 serial ports */
 #define OMAP1_UART1_BASE        0xfffb0000
@@ -51,6 +51,11 @@
 #define OMAP4_UART3_BASE        0x48020000
 #define OMAP4_UART4_BASE        0x4806e000
 
+/* TI816X serial ports */
+#define TI816X_UART1_BASE       0x48020000
+#define TI816X_UART2_BASE       0x48022000
+#define TI816X_UART3_BASE       0x48024000
+
 /* External port on Zoom2/3 */
 #define ZOOM_UART_BASE          0x10000000
 #define ZOOM_UART_VIRT          0xfa400000
@@ -81,6 +86,9 @@
 #define OMAP4UART2              OMAP2UART2
 #define OMAP4UART3              43
 #define OMAP4UART4              44
+#define TI816XUART1             81
+#define TI816XUART2             82
+#define TI816XUART3             83
 #define ZOOM_UART               95              /* Only on zoom2/3 */
 
 /* This is only used by 8250.c for omap1510 */
@@ -96,7 +104,6 @@
 
 struct omap_board_data;
 
-extern void __init omap_serial_early_init(void);
 extern void omap_serial_init(void);
 extern void omap_serial_init_port(struct omap_board_data *bdata);
 extern int omap_uart_can_sleep(void);
diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h b/arch/arm/plat-omap/include/plat/smartreflex.h
deleted file mode 100644
index 6568c885f37a..000000000000
--- a/arch/arm/plat-omap/include/plat/smartreflex.h
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * OMAP Smartreflex Defines and Routines
- *
- * Author: Thara Gopinath       <thara@ti.com>
- *
- * Copyright (C) 2010 Texas Instruments, Inc.
- * Thara Gopinath <thara@ti.com>
- *
- * Copyright (C) 2008 Nokia Corporation
- * Kalle Jokiniemi
- *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Lesly A M <x0080970@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARM_OMAP_SMARTREFLEX_H
-#define __ASM_ARM_OMAP_SMARTREFLEX_H
-
-#include <linux/platform_device.h>
-#include <plat/voltage.h>
-
-/*
- * Different Smartreflex IPs version. The v1 is the 65nm version used in
- * OMAP3430. The v2 is the update for the 45nm version of the IP
- * used in OMAP3630 and OMAP4430
- */
-#define SR_TYPE_V1      1
-#define SR_TYPE_V2      2
-
-/* SMART REFLEX REG ADDRESS OFFSET */
-#define SRCONFIG                0x00
-#define SRSTATUS                0x04
-#define SENVAL                  0x08
-#define SENMIN                  0x0C
-#define SENMAX                  0x10
-#define SENAVG                  0x14
-#define AVGWEIGHT               0x18
-#define NVALUERECIPROCAL        0x1c
-#define SENERROR_V1             0x20
-#define ERRCONFIG_V1            0x24
-#define IRQ_EOI                 0x20
-#define IRQSTATUS_RAW           0x24
-#define IRQSTATUS               0x28
-#define IRQENABLE_SET           0x2C
-#define IRQENABLE_CLR           0x30
-#define SENERROR_V2             0x34
-#define ERRCONFIG_V2            0x38
-
-/* Bit/Shift Positions */
-
-/* SRCONFIG */
-#define SRCONFIG_ACCUMDATA_SHIFT        22
-#define SRCONFIG_SRCLKLENGTH_SHIFT      12
-#define SRCONFIG_SENNENABLE_V1_SHIFT    5
-#define SRCONFIG_SENPENABLE_V1_SHIFT    3
-#define SRCONFIG_SENNENABLE_V2_SHIFT    1
-#define SRCONFIG_SENPENABLE_V2_SHIFT    0
-#define SRCONFIG_CLKCTRL_SHIFT          0
-
-#define SRCONFIG_ACCUMDATA_MASK         (0x3ff << 22)
-
-#define SRCONFIG_SRENABLE               BIT(11)
-#define SRCONFIG_SENENABLE              BIT(10)
-#define SRCONFIG_ERRGEN_EN              BIT(9)
-#define SRCONFIG_MINMAXAVG_EN           BIT(8)
-#define SRCONFIG_DELAYCTRL              BIT(2)
-
-/* AVGWEIGHT */
-#define AVGWEIGHT_SENPAVGWEIGHT_SHIFT   2
-#define AVGWEIGHT_SENNAVGWEIGHT_SHIFT   0
-
-/* NVALUERECIPROCAL */
-#define NVALUERECIPROCAL_SENPGAIN_SHIFT 20
-#define NVALUERECIPROCAL_SENNGAIN_SHIFT 16
-#define NVALUERECIPROCAL_RNSENP_SHIFT   8
-#define NVALUERECIPROCAL_RNSENN_SHIFT   0
-
-/* ERRCONFIG */
-#define ERRCONFIG_ERRWEIGHT_SHIFT       16
-#define ERRCONFIG_ERRMAXLIMIT_SHIFT     8
-#define ERRCONFIG_ERRMINLIMIT_SHIFT     0
-
-#define SR_ERRWEIGHT_MASK               (0x07 << 16)
-#define SR_ERRMAXLIMIT_MASK             (0xff << 8)
-#define SR_ERRMINLIMIT_MASK             (0xff << 0)
-
-#define ERRCONFIG_VPBOUNDINTEN_V1       BIT(31)
-#define ERRCONFIG_VPBOUNDINTST_V1       BIT(30)
-#define ERRCONFIG_MCUACCUMINTEN         BIT(29)
-#define ERRCONFIG_MCUACCUMINTST         BIT(28)
-#define ERRCONFIG_MCUVALIDINTEN         BIT(27)
-#define ERRCONFIG_MCUVALIDINTST         BIT(26)
-#define ERRCONFIG_MCUBOUNDINTEN         BIT(25)
-#define ERRCONFIG_MCUBOUNDINTST         BIT(24)
-#define ERRCONFIG_MCUDISACKINTEN        BIT(23)
-#define ERRCONFIG_VPBOUNDINTST_V2       BIT(23)
-#define ERRCONFIG_MCUDISACKINTST        BIT(22)
-#define ERRCONFIG_VPBOUNDINTEN_V2       BIT(22)
-
-#define ERRCONFIG_STATUS_V1_MASK        (ERRCONFIG_VPBOUNDINTST_V1 | \
-                                        ERRCONFIG_MCUACCUMINTST | \
-                                        ERRCONFIG_MCUVALIDINTST | \
-                                        ERRCONFIG_MCUBOUNDINTST | \
-                                        ERRCONFIG_MCUDISACKINTST)
-/* IRQSTATUS */
-#define IRQSTATUS_MCUACCUMINT           BIT(3)
-#define IRQSTATUS_MCVALIDINT            BIT(2)
-#define IRQSTATUS_MCBOUNDSINT           BIT(1)
-#define IRQSTATUS_MCUDISABLEACKINT      BIT(0)
-
-/* IRQENABLE_SET and IRQENABLE_CLEAR */
-#define IRQENABLE_MCUACCUMINT           BIT(3)
-#define IRQENABLE_MCUVALIDINT           BIT(2)
-#define IRQENABLE_MCUBOUNDSINT          BIT(1)
-#define IRQENABLE_MCUDISABLEACKINT      BIT(0)
-
-/* Common Bit values */
-
-#define SRCLKLENGTH_12MHZ_SYSCLK        0x3c
-#define SRCLKLENGTH_13MHZ_SYSCLK        0x41
-#define SRCLKLENGTH_19MHZ_SYSCLK        0x60
-#define SRCLKLENGTH_26MHZ_SYSCLK        0x82
-#define SRCLKLENGTH_38MHZ_SYSCLK        0xC0
-
-/*
- * 3430 specific values. Maybe these should be passed from board file or
- * pmic structures.
- */
-#define OMAP3430_SR_ACCUMDATA           0x1f4
-
-#define OMAP3430_SR1_SENPAVGWEIGHT      0x03
-#define OMAP3430_SR1_SENNAVGWEIGHT      0x03
-
-#define OMAP3430_SR2_SENPAVGWEIGHT      0x01
-#define OMAP3430_SR2_SENNAVGWEIGHT      0x01
-
-#define OMAP3430_SR_ERRWEIGHT           0x04
-#define OMAP3430_SR_ERRMAXLIMIT         0x02
-
-/**
- * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
- *                              pmic specific info to smartreflex driver
- *
- * @sr_pmic_init:       API to initialize smartreflex on the PMIC side.
- */
-struct omap_sr_pmic_data {
-        void (*sr_pmic_init) (void);
-};
-
-#ifdef CONFIG_OMAP_SMARTREFLEX
-/*
- * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
- * The smartreflex class driver should pass the class type.
- * Should be used to populate the class_type field of the
- * omap_smartreflex_class_data structure.
- */
-#define SR_CLASS1       0x1
-#define SR_CLASS2       0x2
-#define SR_CLASS3       0x3
-
-/**
- * struct omap_sr_class_data - Smartreflex class driver info
- *
- * @enable:             API to enable a particular class smaartreflex.
- * @disable:            API to disable a particular class smartreflex.
- * @configure:          API to configure a particular class smartreflex.
- * @notify:             API to notify the class driver about an event in SR.
- *                      Not needed for class3.
- * @notify_flags:       specify the events to be notified to the class driver
- * @class_type:         specify which smartreflex class.
- *                      Can be used by the SR driver to take any class
- *                      based decisions.
- */
-struct omap_sr_class_data {
-        int (*enable)(struct voltagedomain *voltdm);
-        int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
-        int (*configure)(struct voltagedomain *voltdm);
-        int (*notify)(struct voltagedomain *voltdm, u32 status);
-        u8 notify_flags;
-        u8 class_type;
-};
-
-/**
- * struct omap_sr_nvalue_table  - Smartreflex n-target value info
- *
- * @efuse_offs: The offset of the efuse where n-target values are stored.
- * @nvalue:     The n-target value.
- */
-struct omap_sr_nvalue_table {
-        u32 efuse_offs;
-        u32 nvalue;
-};
-
-/**
- * struct omap_sr_data - Smartreflex platform data.
- *
- * @ip_type:            Smartreflex IP type.
- * @senp_mod:           SENPENABLE value for the sr
- * @senn_mod:           SENNENABLE value for sr
- * @nvalue_count:       Number of distinct nvalues in the nvalue table
- * @enable_on_init:     whether this sr module needs to enabled at
- *                      boot up or not.
- * @nvalue_table:       table containing the  efuse offsets and nvalues
- *                      corresponding to them.
- * @voltdm:             Pointer to the voltage domain associated with the SR
- */
-struct omap_sr_data {
-        int                             ip_type;
-        u32                             senp_mod;
-        u32                             senn_mod;
-        int                             nvalue_count;
-        bool                            enable_on_init;
-        struct omap_sr_nvalue_table     *nvalue_table;
-        struct voltagedomain            *voltdm;
-};
-
-/* Smartreflex module enable/disable interface */
-void omap_sr_enable(struct voltagedomain *voltdm);
-void omap_sr_disable(struct voltagedomain *voltdm);
-void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
-
-/* API to register the pmic specific data with the smartreflex driver. */
-void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
-
-/* Smartreflex driver hooks to be called from Smartreflex class driver */
-int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
-void sr_disable(struct voltagedomain *voltdm);
-int sr_configure_errgen(struct voltagedomain *voltdm);
-int sr_configure_minmax(struct voltagedomain *voltdm);
-
-/* API to register the smartreflex class driver with the smartreflex driver */
-int sr_register_class(struct omap_sr_class_data *class_data);
-#else
-static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
-static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
-static inline void omap_sr_disable_reset_volt(
-                struct voltagedomain *voltdm) {}
-static inline void omap_sr_register_pmic(
-                struct omap_sr_pmic_data *pmic_data) {}
-#endif
-#endif
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 9967d5e855c7..f500fc34d065 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -12,7 +12,19 @@
 #define __ARCH_ARM_OMAP_SRAM_H
 
 #ifndef __ASSEMBLY__
-extern void * omap_sram_push(void * start, unsigned long size);
+#include <asm/fncpy.h>
+
+extern void *omap_sram_push_address(unsigned long size);
+
+/* Macro to push a function to the internal SRAM, using the fncpy API */
+#define omap_sram_push(funcp, size) ({                          \
+        typeof(&(funcp)) _res = NULL;                           \
+        void *_sram_address = omap_sram_push_address(size);     \
+        if (_sram_address)                                      \
+                _res = fncpy(_sram_address, &(funcp), size);    \
+        _res;                                                   \
+})
+
 extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
 
 extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
diff --git a/arch/arm/plat-omap/include/plat/system.h b/arch/arm/plat-omap/include/plat/system.h
index d0a119f735b4..c5fa9e929009 100644
--- a/arch/arm/plat-omap/include/plat/system.h
+++ b/arch/arm/plat-omap/include/plat/system.h
@@ -4,48 +4,14 @@
  */
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
-#include <linux/clk.h>
 
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-
-#include <plat/prcm.h>
-
-#ifndef CONFIG_MACH_VOICEBLUE
-#define voiceblue_reset()               do {} while (0)
-#else
-extern void voiceblue_reset(void);
-#endif
+#include <asm/proc-fns.h>
 
 static inline void arch_idle(void)
 {
         cpu_do_idle();
 }
 
-static inline void omap1_arch_reset(char mode, const char *cmd)
-{
-        /*
-         * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
-         * "Global Software Reset Affects Traffic Controller Frequency".
-         */
-        if (cpu_is_omap5912()) {
-                omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
-                                 DPLL_CTL);
-                omap_writew(0x8, ARM_RSTCT1);
-        }
-
-        if (machine_is_voiceblue())
-                voiceblue_reset();
-        else
-                omap_writew(1, ARM_RSTCT1);
-}
-
-static inline void arch_reset(char mode, const char *cmd)
-{
-        if (!cpu_class_is_omap2())
-                omap1_arch_reset(mode, cmd);
-        else
-                omap_prcm_arch_reset(mode, cmd);
-}
+extern void (*arch_reset)(char, const char *);
 
 #endif
diff --git a/arch/arm/plat-omap/include/plat/ti816x.h b/arch/arm/plat-omap/include/plat/ti816x.h
new file mode 100644
index 000000000000..50510f5dda1e
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/ti816x.h
@@ -0,0 +1,27 @@
+/*
+ * This file contains the address data for various TI816X modules.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_TI816X_H
+#define __ASM_ARCH_TI816X_H
+
+#define L4_SLOW_TI816X_BASE     0x48000000
+
+#define TI816X_SCM_BASE         0x48140000
+#define TI816X_CTRL_BASE        TI816X_SCM_BASE
+#define TI816X_PRCM_BASE        0x48180000
+
+#define TI816X_ARM_INTC_BASE    0x48200000
+
+#endif /* __ASM_ARCH_TI816X_H */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index ad98b85cae21..30b891c4a93f 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -93,6 +93,10 @@ static inline void flush(void)
 #define DEBUG_LL_ZOOM(mach)                                             \
         _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
 
+#define DEBUG_LL_TI816X(p, mach)                                        \
+        _DEBUG_LL_ENTRY(mach, TI816X_UART##p##_BASE, OMAP_PORT_SHIFT,   \
+                TI816XUART##p)
+
 static inline void __arch_decomp_setup(unsigned long arch_id)
 {
         int port = 0;
@@ -166,6 +170,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                 DEBUG_LL_ZOOM(omap_zoom2);
                 DEBUG_LL_ZOOM(omap_zoom3);
 
+                /* TI8168 base boards using UART3 */
+                DEBUG_LL_TI816X(3, ti8168evm);
+
         } while (0);
 }
 
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 450a332f1009..02b96c8f6a17 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -7,15 +7,12 @@
 #include <plat/board.h>
 
 #define OMAP3_HS_USB_PORTS      3
-enum ehci_hcd_omap_mode {
-        EHCI_HCD_OMAP_MODE_UNKNOWN,
-        EHCI_HCD_OMAP_MODE_PHY,
-        EHCI_HCD_OMAP_MODE_TLL,
-        EHCI_HCD_OMAP_MODE_HSIC,
-};
 
-enum ohci_omap3_port_mode {
-        OMAP_OHCI_PORT_MODE_UNUSED,
+enum usbhs_omap_port_mode {
+        OMAP_USBHS_PORT_MODE_UNUSED,
+        OMAP_EHCI_PORT_MODE_PHY,
+        OMAP_EHCI_PORT_MODE_TLL,
+        OMAP_EHCI_PORT_MODE_HSIC,
         OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
         OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
         OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
@@ -25,24 +22,45 @@ enum ohci_omap3_port_mode {
         OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
         OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
         OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
-        OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM,
+        OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
 };
 
-struct ehci_hcd_omap_platform_data {
-        enum ehci_hcd_omap_mode         port_mode[OMAP3_HS_USB_PORTS];
-        unsigned                        phy_reset:1;
+struct usbhs_omap_board_data {
+        enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
 
         /* have to be valid if phy_reset is true and portx is in phy mode */
         int     reset_gpio_port[OMAP3_HS_USB_PORTS];
+
+        /* Set this to true for ES2.x silicon */
+        unsigned                        es2_compatibility:1;
+
+        unsigned                        phy_reset:1;
+
+        /*
+         * Regulators for USB PHYs.
+         * Each PHY can have a separate regulator.
+         */
+        struct regulator                *regulator[OMAP3_HS_USB_PORTS];
 };
 
-struct ohci_hcd_omap_platform_data {
-        enum ohci_omap3_port_mode       port_mode[OMAP3_HS_USB_PORTS];
+struct ehci_hcd_omap_platform_data {
+        enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
+        int                             reset_gpio_port[OMAP3_HS_USB_PORTS];
+        struct regulator                *regulator[OMAP3_HS_USB_PORTS];
+        unsigned                        phy_reset:1;
+};
 
-        /* Set this to true for ES2.x silicon */
+struct ohci_hcd_omap_platform_data {
+        enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
         unsigned                        es2_compatibility:1;
 };
 
+struct usbhs_omap_platform_data {
+        enum usbhs_omap_port_mode               port_mode[OMAP3_HS_USB_PORTS];
+
+        struct ehci_hcd_omap_platform_data      *ehci_data;
+        struct ohci_hcd_omap_platform_data      *ohci_data;
+};
 /*-------------------------------------------------------------------------*/
 
 #define OMAP1_OTG_BASE                  0xfffb0400
@@ -80,17 +98,22 @@ enum musb_interface    {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
 
 extern void usb_musb_init(struct omap_musb_board_data *board_data);
 
-extern void usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata);
+extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
 
-extern void usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata);
+extern int omap_usbhs_enable(struct device *dev);
+extern void omap_usbhs_disable(struct device *dev);
 
 extern int omap4430_phy_power(struct device *dev, int ID, int on);
 extern int omap4430_phy_set_clk(struct device *dev, int on);
 extern int omap4430_phy_init(struct device *dev);
 extern int omap4430_phy_exit(struct device *dev);
-
+extern int omap4430_phy_suspend(struct device *dev, int suspend);
 #endif
 
+extern void am35x_musb_reset(void);
+extern void am35x_musb_phy_power(u8 on);
+extern void am35x_musb_clear_irq(void);
+extern void am35x_musb_set_mode(u8 musb_mode);
 
 /*
  * FIXME correct answer depends on hmc_mode,
diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
deleted file mode 100644
index 5bd204e55c32..000000000000
--- a/arch/arm/plat-omap/include/plat/voltage.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * OMAP Voltage Management Routines
- *
- * Author: Thara Gopinath       <thara@ti.com>
- *
- * Copyright (C) 2009 Texas Instruments, Inc.
- * Thara Gopinath <thara@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_VOLTAGE_H
-#define __ARCH_ARM_MACH_OMAP2_VOLTAGE_H
-
-#include <linux/err.h>
-
-#define VOLTSCALE_VPFORCEUPDATE         1
-#define VOLTSCALE_VCBYPASS              2
-
-/*
- * OMAP3 GENERIC setup times. Revisit to see if these needs to be
- * passed from board or PMIC file
- */
-#define OMAP3_CLKSETUP          0xff
-#define OMAP3_VOLTOFFSET        0xff
-#define OMAP3_VOLTSETUP2        0xff
-
-/* Voltage value defines */
-#define OMAP3430_VDD_MPU_OPP1_UV                975000
-#define OMAP3430_VDD_MPU_OPP2_UV                1075000
-#define OMAP3430_VDD_MPU_OPP3_UV                1200000
-#define OMAP3430_VDD_MPU_OPP4_UV                1270000
-#define OMAP3430_VDD_MPU_OPP5_UV                1350000
-
-#define OMAP3430_VDD_CORE_OPP1_UV               975000
-#define OMAP3430_VDD_CORE_OPP2_UV               1050000
-#define OMAP3430_VDD_CORE_OPP3_UV               1150000
-
-#define OMAP3630_VDD_MPU_OPP50_UV               1012500
-#define OMAP3630_VDD_MPU_OPP100_UV              1200000
-#define OMAP3630_VDD_MPU_OPP120_UV              1325000
-#define OMAP3630_VDD_MPU_OPP1G_UV               1375000
-
-#define OMAP3630_VDD_CORE_OPP50_UV              1000000
-#define OMAP3630_VDD_CORE_OPP100_UV             1200000
-
-#define OMAP4430_VDD_MPU_OPP50_UV               930000
-#define OMAP4430_VDD_MPU_OPP100_UV              1100000
-#define OMAP4430_VDD_MPU_OPPTURBO_UV            1260000
-#define OMAP4430_VDD_MPU_OPPNITRO_UV            1350000
-
-#define OMAP4430_VDD_IVA_OPP50_UV               930000
-#define OMAP4430_VDD_IVA_OPP100_UV              1100000
-#define OMAP4430_VDD_IVA_OPPTURBO_UV            1260000
-
-#define OMAP4430_VDD_CORE_OPP50_UV              930000
-#define OMAP4430_VDD_CORE_OPP100_UV             1100000
-
-/**
- * struct voltagedomain - omap voltage domain global structure.
- * @name:       Name of the voltage domain which can be used as a unique
- *              identifier.
- */
-struct voltagedomain {
-        char *name;
-};
-
-/**
- * struct omap_volt_data - Omap voltage specific data.
- * @voltage_nominal:    The possible voltage value in uV
- * @sr_efuse_offs:      The offset of the efuse register(from system
- *                      control module base address) from where to read
- *                      the n-target value for the smartreflex module.
- * @sr_errminlimit:     Error min limit value for smartreflex. This value
- *                      differs at differnet opp and thus is linked
- *                      with voltage.
- * @vp_errorgain:       Error gain value for the voltage processor. This
- *                      field also differs according to the voltage/opp.
- */
-struct omap_volt_data {
-        u32     volt_nominal;
-        u32     sr_efuse_offs;
-        u8      sr_errminlimit;
-        u8      vp_errgain;
-};
-
-/**
- * struct omap_volt_pmic_info - PMIC specific data required by voltage driver.
- * @slew_rate:  PMIC slew rate (in uv/us)
- * @step_size:  PMIC voltage step size (in uv)
- * @vsel_to_uv: PMIC API to convert vsel value to actual voltage in uV.
- * @uv_to_vsel: PMIC API to convert voltage in uV to vsel value.
- */
-struct omap_volt_pmic_info {
-        int slew_rate;
-        int step_size;
-        u32 on_volt;
-        u32 onlp_volt;
-        u32 ret_volt;
-        u32 off_volt;
-        u16 volt_setup_time;
-        u8 vp_erroroffset;
-        u8 vp_vstepmin;
-        u8 vp_vstepmax;
-        u8 vp_vddmin;
-        u8 vp_vddmax;
-        u8 vp_timeout_us;
-        u8 i2c_slave_addr;
-        u8 pmic_reg;
-        unsigned long (*vsel_to_uv) (const u8 vsel);
-        u8 (*uv_to_vsel) (unsigned long uV);
-};
-
-unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm);
-void omap_vp_enable(struct voltagedomain *voltdm);
-void omap_vp_disable(struct voltagedomain *voltdm);
-int omap_voltage_scale_vdd(struct voltagedomain *voltdm,
-                unsigned long target_volt);
-void omap_voltage_reset(struct voltagedomain *voltdm);
-void omap_voltage_get_volttable(struct voltagedomain *voltdm,
-                struct omap_volt_data **volt_data);
-struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
-                unsigned long volt);
-unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm);
-struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm);
-#ifdef CONFIG_PM
-int omap_voltage_register_pmic(struct voltagedomain *voltdm,
-                struct omap_volt_pmic_info *pmic_info);
-void omap_change_voltscale_method(struct voltagedomain *voltdm,
-                int voltscale_method);
-/* API to get the voltagedomain pointer */
-struct voltagedomain *omap_voltage_domain_lookup(char *name);
-
-int omap_voltage_late_init(void);
-#else
-static inline int omap_voltage_register_pmic(struct voltagedomain *voltdm,
-                struct omap_volt_pmic_info *pmic_info)
-{
-        return -EINVAL;
-}
-static inline  void omap_change_voltscale_method(struct voltagedomain *voltdm,
-                int voltscale_method) {}
-static inline int omap_voltage_late_init(void)
-{
-        return -EINVAL;
-}
-static inline struct voltagedomain *omap_voltage_domain_lookup(char *name)
-{
-        return ERR_PTR(-EINVAL);
-}
-#endif
-
-#endif
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index f1295fafcd31..f1ecfa9fc61d 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -85,7 +85,10 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
         }
 #endif
 #ifdef CONFIG_ARCH_OMAP3
-        if (cpu_is_omap34xx()) {
+        if (cpu_is_ti816x()) {
+                if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
+                        return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
+        } else if (cpu_is_omap34xx()) {
                 if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE))
                         return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);
                 if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index b1107c08da56..8a51fd58f656 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -104,6 +104,9 @@ static int iommu_enable(struct iommu *obj)
         if (!obj)
                 return -EINVAL;
 
+        if (!arch_iommu)
+                return -ENODEV;
+
         clk_enable(obj->clk);
 
         err = arch_iommu->enable(obj);
@@ -780,25 +783,19 @@ static void iopgtable_clear_entry_all(struct iommu *obj)
  */
 static irqreturn_t iommu_fault_handler(int irq, void *data)
 {
-        u32 stat, da;
+        u32 da, errs;
         u32 *iopgd, *iopte;
-        int err = -EIO;
         struct iommu *obj = data;
 
         if (!obj->refcount)
                 return IRQ_NONE;
 
-        /* Dynamic loading TLB or PTE */
-        if (obj->isr)
-                err = obj->isr(obj);
-
-        if (!err)
-                return IRQ_HANDLED;
-
         clk_enable(obj->clk);
-        stat = iommu_report_fault(obj, &da);
+        errs = iommu_report_fault(obj, &da);
         clk_disable(obj->clk);
-        if (!stat)
+
+        /* Fault callback or TLB/PTE Dynamic loading */
+        if (obj->isr && !obj->isr(obj, da, errs, obj->isr_priv))
                 return IRQ_HANDLED;
 
         iommu_disable(obj);
@@ -806,15 +803,16 @@ static irqreturn_t iommu_fault_handler(int irq, void *data)
         iopgd = iopgd_offset(obj, da);
 
         if (!iopgd_is_table(*iopgd)) {
-                dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__,
-                        da, iopgd, *iopgd);
+                dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p "
+                        "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd);
                 return IRQ_NONE;
         }
 
         iopte = iopte_offset(iopgd, da);
 
-        dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
-                __func__, da, iopgd, *iopgd, iopte, *iopte);
+        dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x "
+                "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd,
+                iopte, *iopte);
 
         return IRQ_NONE;
 }
@@ -917,6 +915,33 @@ void iommu_put(struct iommu *obj)
 }
 EXPORT_SYMBOL_GPL(iommu_put);
 
+int iommu_set_isr(const char *name,
+                  int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs,
+                             void *priv),
+                  void *isr_priv)
+{
+        struct device *dev;
+        struct iommu *obj;
+
+        dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name,
+                                 device_match_by_alias);
+        if (!dev)
+                return -ENODEV;
+
+        obj = to_iommu(dev);
+        mutex_lock(&obj->iommu_lock);
+        if (obj->refcount != 0) {
+                mutex_unlock(&obj->iommu_lock);
+                return -EBUSY;
+        }
+        obj->isr = isr;
+        obj->isr_priv = isr_priv;
+        mutex_unlock(&obj->iommu_lock);
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(iommu_set_isr);
+
 /*
  *      OMAP Device MMU(IOMMU) detection
  */
@@ -957,11 +982,6 @@ static int __devinit omap_iommu_probe(struct platform_device *pdev)
                 err = -ENODEV;
                 goto err_mem;
         }
-        obj->regbase = ioremap(res->start, resource_size(res));
-        if (!obj->regbase) {
-                err = -ENOMEM;
-                goto err_mem;
-        }
 
         res = request_mem_region(res->start, resource_size(res),
                                  dev_name(&pdev->dev));
@@ -970,6 +990,12 @@ static int __devinit omap_iommu_probe(struct platform_device *pdev)
                 goto err_mem;
         }
 
+        obj->regbase = ioremap(res->start, resource_size(res));
+        if (!obj->regbase) {
+                err = -ENOMEM;
+                goto err_ioremap;
+        }
+
         irq = platform_get_irq(pdev, 0);
         if (irq < 0) {
                 err = -ENODEV;
@@ -998,8 +1024,9 @@ static int __devinit omap_iommu_probe(struct platform_device *pdev)
 err_pgd:
         free_irq(irq, obj);
 err_irq:
-        release_mem_region(res->start, resource_size(res));
         iounmap(obj->regbase);
+err_ioremap:
+        release_mem_region(res->start, resource_size(res));
 err_mem:
         clk_put(obj->clk);
 err_clk:
diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c
index 6dc1296c8c77..51ef43e8def6 100644
--- a/arch/arm/plat-omap/iovmm.c
+++ b/arch/arm/plat-omap/iovmm.c
@@ -271,20 +271,21 @@ static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da,
                                            size_t bytes, u32 flags)
 {
         struct iovm_struct *new, *tmp;
-        u32 start, prev_end, alignement;
+        u32 start, prev_end, alignment;
 
         if (!obj || !bytes)
                 return ERR_PTR(-EINVAL);
 
         start = da;
-        alignement = PAGE_SIZE;
+        alignment = PAGE_SIZE;
 
-        if (flags & IOVMF_DA_ANON) {
-                start = obj->da_start;
+        if (~flags & IOVMF_DA_FIXED) {
+                /* Don't map address 0 */
+                start = obj->da_start ? obj->da_start : alignment;
 
                 if (flags & IOVMF_LINEAR)
-                        alignement = iopgsz_max(bytes);
-                start = roundup(start, alignement);
+                        alignment = iopgsz_max(bytes);
+                start = roundup(start, alignment);
         } else if (start < obj->da_start || start > obj->da_end ||
                                         obj->da_end - start < bytes) {
                 return ERR_PTR(-EINVAL);
@@ -303,8 +304,8 @@ static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da,
                 if (tmp->da_start > start && (tmp->da_start - start) >= bytes)
                         goto found;
 
-                if (tmp->da_end >= start && flags & IOVMF_DA_ANON)
-                        start = roundup(tmp->da_end + 1, alignement);
+                if (tmp->da_end >= start && ~flags & IOVMF_DA_FIXED)
+                        start = roundup(tmp->da_end + 1, alignment);
 
                 prev_end = tmp->da_end;
         }
@@ -650,7 +651,6 @@ u32 iommu_vmap(struct iommu *obj, u32 da, const struct sg_table *sgt,
         flags &= IOVMF_HW_MASK;
         flags |= IOVMF_DISCONT;
         flags |= IOVMF_MMIO;
-        flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
 
         da = __iommu_vmap(obj, da, sgt, va, bytes, flags);
         if (IS_ERR_VALUE(da))
@@ -690,7 +690,7 @@ EXPORT_SYMBOL_GPL(iommu_vunmap);
  * @flags:      iovma and page property
  *
  * Allocate @bytes linearly and creates 1-n-1 mapping and returns
- * @da again, which might be adjusted if 'IOVMF_DA_ANON' is set.
+ * @da again, which might be adjusted if 'IOVMF_DA_FIXED' is not set.
  */
 u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags)
 {
@@ -709,7 +709,6 @@ u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags)
         flags &= IOVMF_HW_MASK;
         flags |= IOVMF_DISCONT;
         flags |= IOVMF_ALLOC;
-        flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
 
         sgt = sgtable_alloc(bytes, flags, da, 0);
         if (IS_ERR(sgt)) {
@@ -780,7 +779,7 @@ static u32 __iommu_kmap(struct iommu *obj, u32 da, u32 pa, void *va,
  * @flags:      iovma and page property
  *
  * Creates 1-1-1 mapping and returns @da again, which can be
- * adjusted if 'IOVMF_DA_ANON' is set.
+ * adjusted if 'IOVMF_DA_FIXED' is not set.
  */
 u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes,
                  u32 flags)
@@ -799,7 +798,6 @@ u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes,
         flags &= IOVMF_HW_MASK;
         flags |= IOVMF_LINEAR;
         flags |= IOVMF_MMIO;
-        flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
 
         da = __iommu_kmap(obj, da, pa, va, bytes, flags);
         if (IS_ERR_VALUE(da))
@@ -838,7 +836,7 @@ EXPORT_SYMBOL_GPL(iommu_kunmap);
  * @flags:      iovma and page property
  *
  * Allocate @bytes linearly and creates 1-1-1 mapping and returns
- * @da again, which might be adjusted if 'IOVMF_DA_ANON' is set.
+ * @da again, which might be adjusted if 'IOVMF_DA_FIXED' is not set.
  */
 u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags)
 {
@@ -858,7 +856,6 @@ u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags)
         flags &= IOVMF_HW_MASK;
         flags |= IOVMF_LINEAR;
         flags |= IOVMF_ALLOC;
-        flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
 
         da = __iommu_kmap(obj, da, pa, va, bytes, flags);
         if (IS_ERR_VALUE(da))
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 459b319a9fad..69ddc9f76c13 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -32,7 +32,6 @@
 
 #include <plat/mailbox.h>
 
-static struct workqueue_struct *mboxd;
 static struct omap_mbox **mboxes;
 
 static int mbox_configured;
@@ -197,7 +196,7 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox)
         /* no more messages in the fifo. clear IRQ source. */
         ack_mbox_irq(mbox, IRQ_RX);
 nomem:
-        queue_work(mboxd, &mbox->rxq->work);
+        schedule_work(&mbox->rxq->work);
 }
 
 static irqreturn_t mbox_interrupt(int irq, void *p)
@@ -307,7 +306,7 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
         if (!--mbox->use_count) {
                 free_irq(mbox->irq, mbox);
                 tasklet_kill(&mbox->txq->tasklet);
-                flush_work(&mbox->rxq->work);
+        flush_work_sync(&mbox->rxq->work);
                 mbox_queue_free(mbox->txq);
                 mbox_queue_free(mbox->rxq);
         }
@@ -322,15 +321,18 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
 
 struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb)
 {
-        struct omap_mbox *mbox;
-        int ret;
+        struct omap_mbox *_mbox, *mbox = NULL;
+        int i, ret;
 
         if (!mboxes)
                 return ERR_PTR(-EINVAL);
 
-        for (mbox = *mboxes; mbox; mbox++)
-                if (!strcmp(mbox->name, name))
+        for (i = 0; (_mbox = mboxes[i]); i++) {
+                if (!strcmp(_mbox->name, name)) {
+                        mbox = _mbox;
                         break;
+                }
+        }
 
         if (!mbox)
                 return ERR_PTR(-ENOENT);
@@ -406,10 +408,6 @@ static int __init omap_mbox_init(void)
         if (err)
                 return err;
 
-        mboxd = create_workqueue("mboxd");
-        if (!mboxd)
-                return -ENOMEM;
-
         /* kfifo size sanity check: alignment and minimal size */
         mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t));
         mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size,
@@ -421,7 +419,6 @@ subsys_initcall(omap_mbox_init);
 
 static void __exit omap_mbox_exit(void)
 {
-        destroy_workqueue(mboxd);
         class_unregister(&omap_mbox_class);
 }
 module_exit(omap_mbox_exit);
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index b5a6e178a7f9..d598d9fd65ac 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -27,6 +27,8 @@
 
 #include <plat/dma.h>
 #include <plat/mcbsp.h>
+#include <plat/omap_device.h>
+#include <linux/pm_runtime.h>
 
 /* XXX These "sideways" includes are a sign that something is wrong */
 #include "../mach-omap2/cm2xxx_3xxx.h"
@@ -227,10 +229,83 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 }
 EXPORT_SYMBOL(omap_mcbsp_config);
 
+/**
+ * omap_mcbsp_dma_params - returns the dma channel number
+ * @id - mcbsp id
+ * @stream - indicates the direction of data flow (rx or tx)
+ *
+ * Returns the dma channel number for the rx channel or tx channel
+ * based on the value of @stream for the requested mcbsp given by @id
+ */
+int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream)
+{
+        struct omap_mcbsp *mcbsp;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+
+        if (stream)
+                return mcbsp->dma_rx_sync;
+        else
+                return mcbsp->dma_tx_sync;
+}
+EXPORT_SYMBOL(omap_mcbsp_dma_ch_params);
+
+/**
+ * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
+ * @id - mcbsp id
+ * @stream - indicates the direction of data flow (rx or tx)
+ *
+ * Returns the address of mcbsp data transmit register or data receive register
+ * to be used by DMA for transferring/receiving data based on the value of
+ * @stream for the requested mcbsp given by @id
+ */
+int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
+{
+        struct omap_mcbsp *mcbsp;
+        int data_reg;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+
+        data_reg = mcbsp->phys_dma_base;
+
+        if (mcbsp->mcbsp_config_type < MCBSP_CONFIG_TYPE2) {
+                if (stream)
+                        data_reg += OMAP_MCBSP_REG_DRR1;
+                else
+                        data_reg += OMAP_MCBSP_REG_DXR1;
+        } else {
+                if (stream)
+                        data_reg += OMAP_MCBSP_REG_DRR;
+                else
+                        data_reg += OMAP_MCBSP_REG_DXR;
+        }
+
+        return data_reg;
+}
+EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
+
 #ifdef CONFIG_ARCH_OMAP3
+static struct omap_device *find_omap_device_by_dev(struct device *dev)
+{
+        struct platform_device *pdev = container_of(dev,
+                                        struct platform_device, dev);
+        return container_of(pdev, struct omap_device, pdev);
+}
+
 static void omap_st_on(struct omap_mcbsp *mcbsp)
 {
         unsigned int w;
+        struct omap_device *od;
+
+        od = find_omap_device_by_dev(mcbsp->dev);
 
         /*
          * Sidetone uses McBSP ICLK - which must not idle when sidetones
@@ -244,9 +319,6 @@ static void omap_st_on(struct omap_mcbsp *mcbsp)
         w = MCBSP_READ(mcbsp, SSELCR);
         MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
 
-        w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
-        MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
-
         /* Enable Sidetone from Sidetone Core */
         w = MCBSP_ST_READ(mcbsp, SSELCR);
         MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
@@ -255,13 +327,13 @@ static void omap_st_on(struct omap_mcbsp *mcbsp)
 static void omap_st_off(struct omap_mcbsp *mcbsp)
 {
         unsigned int w;
+        struct omap_device *od;
+
+        od = find_omap_device_by_dev(mcbsp->dev);
 
         w = MCBSP_ST_READ(mcbsp, SSELCR);
         MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
 
-        w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
-        MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
-
         w = MCBSP_READ(mcbsp, SSELCR);
         MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
 
@@ -273,9 +345,9 @@ static void omap_st_off(struct omap_mcbsp *mcbsp)
 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
 {
         u16 val, i;
+        struct omap_device *od;
 
-        val = MCBSP_ST_READ(mcbsp, SYSCONFIG);
-        MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE));
+        od = find_omap_device_by_dev(mcbsp->dev);
 
         val = MCBSP_ST_READ(mcbsp, SSELCR);
 
@@ -303,9 +375,9 @@ static void omap_st_chgain(struct omap_mcbsp *mcbsp)
 {
         u16 w;
         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
+        struct omap_device *od;
 
-        w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
-        MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
+        od = find_omap_device_by_dev(mcbsp->dev);
 
         w = MCBSP_ST_READ(mcbsp, SSELCR);
 
@@ -648,48 +720,33 @@ EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
 
 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
 {
+        struct omap_device *od;
+
+        od = find_omap_device_by_dev(mcbsp->dev);
         /*
          * Enable wakup behavior, smart idle and all wakeups
          * REVISIT: some wakeups may be unnecessary
          */
         if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                u16 syscon;
-
-                syscon = MCBSP_READ(mcbsp, SYSCON);
-                syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
-
-                if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
-                        syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
-                                        CLOCKACTIVITY(0x02));
-                        MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
-                } else {
-                        syscon |= SIDLEMODE(0x01);
-                }
-
-                MCBSP_WRITE(mcbsp, SYSCON, syscon);
+                MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
         }
 }
 
 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
 {
+        struct omap_device *od;
+
+        od = find_omap_device_by_dev(mcbsp->dev);
+
         /*
          * Disable wakup behavior, smart idle and all wakeups
          */
         if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                u16 syscon;
-
-                syscon = MCBSP_READ(mcbsp, SYSCON);
-                syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
                 /*
                  * HW bug workaround - If no_idle mode is taken, we need to
                  * go to smart_idle before going to always_idle, or the
                  * device will not hit retention anymore.
                  */
-                syscon |= SIDLEMODE(0x02);
-                MCBSP_WRITE(mcbsp, SYSCON, syscon);
-
-                syscon &= ~(SIDLEMODE(0x03));
-                MCBSP_WRITE(mcbsp, SYSCON, syscon);
 
                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
         }
@@ -764,8 +821,7 @@ int omap_mcbsp_request(unsigned int id)
         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
                 mcbsp->pdata->ops->request(id);
 
-        clk_enable(mcbsp->iclk);
-        clk_enable(mcbsp->fclk);
+        pm_runtime_get_sync(mcbsp->dev);
 
         /* Do procedure specific to omap34xx arch, if applicable */
         omap34xx_mcbsp_request(mcbsp);
@@ -813,8 +869,7 @@ err_clk_disable:
         /* Do procedure specific to omap34xx arch, if applicable */
         omap34xx_mcbsp_free(mcbsp);
 
-        clk_disable(mcbsp->fclk);
-        clk_disable(mcbsp->iclk);
+        pm_runtime_put_sync(mcbsp->dev);
 
         spin_lock(&mcbsp->lock);
         mcbsp->free = true;
@@ -844,8 +899,7 @@ void omap_mcbsp_free(unsigned int id)
         /* Do procedure specific to omap34xx arch, if applicable */
         omap34xx_mcbsp_free(mcbsp);
 
-        clk_disable(mcbsp->fclk);
-        clk_disable(mcbsp->iclk);
+        pm_runtime_put_sync(mcbsp->dev);
 
         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
                 /* Free IRQs */
@@ -1649,7 +1703,8 @@ static const struct attribute_group sidetone_attr_group = {
 
 static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
 {
-        struct omap_mcbsp_platform_data *pdata = mcbsp->pdata;
+        struct platform_device *pdev;
+        struct resource *res;
         struct omap_mcbsp_st_data *st_data;
         int err;
 
@@ -1659,7 +1714,10 @@ static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
                 goto err1;
         }
 
-        st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K);
+        pdev = container_of(mcbsp->dev, struct platform_device, dev);
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
+        st_data->io_base_st = ioremap(res->start, resource_size(res));
         if (!st_data->io_base_st) {
                 err = -ENOMEM;
                 goto err2;
@@ -1748,6 +1806,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
         struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
         struct omap_mcbsp *mcbsp;
         int id = pdev->id - 1;
+        struct resource *res;
         int ret = 0;
 
         if (!pdata) {
@@ -1777,47 +1836,78 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
         mcbsp->dma_tx_lch = -1;
         mcbsp->dma_rx_lch = -1;
 
-        mcbsp->phys_base = pdata->phys_base;
-        mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
+        if (!res) {
+                res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+                if (!res) {
+                        dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
+                                        "resource\n", __func__, pdev->id);
+                        ret = -ENOMEM;
+                        goto exit;
+                }
+        }
+        mcbsp->phys_base = res->start;
+        omap_mcbsp_cache_size = resource_size(res);
+        mcbsp->io_base = ioremap(res->start, resource_size(res));
         if (!mcbsp->io_base) {
                 ret = -ENOMEM;
                 goto err_ioremap;
         }
 
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
+        if (!res)
+                mcbsp->phys_dma_base = mcbsp->phys_base;
+        else
+                mcbsp->phys_dma_base = res->start;
+
         /* Default I/O is IRQ based */
         mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
-        mcbsp->tx_irq = pdata->tx_irq;
-        mcbsp->rx_irq = pdata->rx_irq;
-        mcbsp->dma_rx_sync = pdata->dma_rx_sync;
-        mcbsp->dma_tx_sync = pdata->dma_tx_sync;
 
-        mcbsp->iclk = clk_get(&pdev->dev, "ick");
-        if (IS_ERR(mcbsp->iclk)) {
-                ret = PTR_ERR(mcbsp->iclk);
-                dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
-                goto err_iclk;
+        mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
+        mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
+
+        /* From OMAP4 there will be a single irq line */
+        if (mcbsp->tx_irq == -ENXIO)
+                mcbsp->tx_irq = platform_get_irq(pdev, 0);
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
+        if (!res) {
+                dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
+                                        __func__, pdev->id);
+                ret = -ENODEV;
+                goto err_res;
+        }
+        mcbsp->dma_rx_sync = res->start;
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
+        if (!res) {
+                dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
+                                        __func__, pdev->id);
+                ret = -ENODEV;
+                goto err_res;
         }
+        mcbsp->dma_tx_sync = res->start;
 
         mcbsp->fclk = clk_get(&pdev->dev, "fck");
         if (IS_ERR(mcbsp->fclk)) {
                 ret = PTR_ERR(mcbsp->fclk);
                 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
-                goto err_fclk;
+                goto err_res;
         }
 
         mcbsp->pdata = pdata;
         mcbsp->dev = &pdev->dev;
         mcbsp_ptr[id] = mcbsp;
+        mcbsp->mcbsp_config_type = pdata->mcbsp_config_type;
         platform_set_drvdata(pdev, mcbsp);
+        pm_runtime_enable(mcbsp->dev);
 
         /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
         omap34xx_device_init(mcbsp);
 
         return 0;
 
-err_fclk:
-        clk_put(mcbsp->iclk);
-err_iclk:
+err_res:
         iounmap(mcbsp->io_base);
 err_ioremap:
         kfree(mcbsp);
@@ -1839,7 +1929,6 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
                 omap34xx_device_exit(mcbsp);
 
                 clk_put(mcbsp->fclk);
-                clk_put(mcbsp->iclk);
 
                 iounmap(mcbsp->io_base);
                 kfree(mcbsp);
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 57adb270767b..9bbda9acb73b 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -83,9 +83,11 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/clk.h>
+#include <linux/clkdev.h>
 
 #include <plat/omap_device.h>
 #include <plat/omap_hwmod.h>
+#include <plat/clock.h>
 
 /* These parameters are passed to _omap_device_{de,}activate() */
 #define USE_WAKEUP_LAT                  0
@@ -239,12 +241,12 @@ static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
 }
 
 /**
- * _add_optional_clock_alias - Add clock alias for hwmod optional clocks
+ * _add_optional_clock_clkdev - Add clkdev entry for hwmod optional clocks
  * @od: struct omap_device *od
  *
  * For every optional clock present per hwmod per omap_device, this function
- * adds an entry in the clocks list of the form <dev-id=dev_name, con-id=role>
- * if an entry is already present in it with the form <dev-id=NULL, con-id=role>
+ * adds an entry in the clkdev table of the form <dev-id=dev_name, con-id=role>
+ * if it does not exist already.
  *
  * The function is called from inside omap_device_build_ss(), after
  * omap_device_register.
@@ -254,25 +256,39 @@ static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
  *
  * No return value.
  */
-static void _add_optional_clock_alias(struct omap_device *od,
+static void _add_optional_clock_clkdev(struct omap_device *od,
                                       struct omap_hwmod *oh)
 {
         int i;
 
         for (i = 0; i < oh->opt_clks_cnt; i++) {
                 struct omap_hwmod_opt_clk *oc;
-                int r;
+                struct clk *r;
+                struct clk_lookup *l;
 
                 oc = &oh->opt_clks[i];
 
                 if (!oc->_clk)
                         continue;
 
-                r = clk_add_alias(oc->role, dev_name(&od->pdev.dev),
-                                  (char *)oc->clk, &od->pdev.dev);
-                if (r)
-                        pr_err("omap_device: %s: clk_add_alias for %s failed\n",
+                r = clk_get_sys(dev_name(&od->pdev.dev), oc->role);
+                if (!IS_ERR(r))
+                        continue; /* clkdev entry exists */
+
+                r = omap_clk_get_by_name((char *)oc->clk);
+                if (IS_ERR(r)) {
+                        pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n",
+                               dev_name(&od->pdev.dev), oc->clk);
+                        continue;
+                }
+
+                l = clkdev_alloc(r, oc->role, dev_name(&od->pdev.dev));
+                if (!l) {
+                        pr_err("omap_device: %s: clkdev_alloc for %s failed\n",
                                dev_name(&od->pdev.dev), oc->role);
+                        return;
+                }
+                clkdev_add(l);
         }
 }
 
@@ -480,7 +496,7 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
 
         for (i = 0; i < oh_cnt; i++) {
                 hwmods[i]->od = od;
-                _add_optional_clock_alias(od, hwmods[i]);
+                _add_optional_clock_clkdev(od, hwmods[i]);
         }
 
         if (ret)
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index e26e50487d60..a3f50b34a90d 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -242,7 +242,14 @@ static void __init omap_map_sram(void)
                omap_sram_size - SRAM_BOOTLOADER_SZ);
 }
 
-void * omap_sram_push(void * start, unsigned long size)
+/*
+ * Memory allocator for SRAM: calculates the new ceiling address
+ * for pushing a function using the fncpy API.
+ *
+ * Note that fncpy requires the returned address to be aligned
+ * to an 8-byte boundary.
+ */
+void *omap_sram_push_address(unsigned long size)
 {
         if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) {
                 printk(KERN_ERR "Not enough space in SRAM\n");
@@ -250,10 +257,7 @@ void * omap_sram_push(void * start, unsigned long size)
         }
 
         omap_sram_ceil -= size;
-        omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
-        memcpy((void *)omap_sram_ceil, start, size);
-        flush_icache_range((unsigned long)omap_sram_ceil,
-                (unsigned long)(omap_sram_ceil + size));
+        omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, FNCPY_ALIGN);
 
         return (void *)omap_sram_ceil;
 }
@@ -312,7 +316,7 @@ u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 }
 #endif
 
-#ifdef CONFIG_ARCH_OMAP2420
+#ifdef CONFIG_SOC_OMAP2420
 static int __init omap242x_sram_init(void)
 {
         _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
@@ -333,7 +337,7 @@ static inline int omap242x_sram_init(void)
 }
 #endif
 
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 static int __init omap243x_sram_init(void)
 {
         _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
@@ -405,20 +409,6 @@ static inline int omap34xx_sram_init(void)
 }
 #endif
 
-#ifdef CONFIG_ARCH_OMAP4
-static int __init omap44xx_sram_init(void)
-{
-        printk(KERN_ERR "FIXME: %s not implemented\n", __func__);
-
-        return -ENODEV;
-}
-#else
-static inline int omap44xx_sram_init(void)
-{
-        return 0;
-}
-#endif
-
 int __init omap_sram_init(void)
 {
         omap_detect_sram();
@@ -432,8 +422,6 @@ int __init omap_sram_init(void)
                 omap243x_sram_init();
         else if (cpu_is_omap34xx())
                 omap34xx_sram_init();
-        else if (cpu_is_omap44xx())
-                omap44xx_sram_init();
 
         return 0;
 }