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authorJarkko Nikula <jarkko.nikula@bitmer.com>2011-09-26 03:45:39 -0400
committerTony Lindgren <tony@atomide.com>2011-09-26 20:46:48 -0400
commitcdc71514a0f4f3e8c995f18d1119cef01a501dac (patch)
treeffc6ae60449339619d92dda064051052da7ededb /arch/arm/plat-omap
parent40246e0003f02160a116db249270129b0c600e95 (diff)
ARM: OMAP: mcbsp: Implement generic register access
Register access can be made more generic by calculating register address offsets runtime from common register definitions and by using reg_size and reg_step variables that are passed via platform data. Common register definitions are possible since McBSP registers are ordered similarly between OMAP versions. Remove also references to OMAP2+ specific config_type variable from generic McBSP code since other variables and feature flags are better to carry needed information from platform code. Signed-off-by: Jarkko Nikula <jarkko.nikula@bitmer.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Tested-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r--arch/arm/plat-omap/include/plat/mcbsp.h145
-rw-r--r--arch/arm/plat-omap/mcbsp.c45
2 files changed, 75 insertions, 115 deletions
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 7adfd92d6c1a..14bc1cbe43d9 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -51,93 +51,60 @@ static struct platform_device omap_mcbsp##port_nr = { \
51#define OMAP1610_MCBSP2_BASE 0xfffb1000 51#define OMAP1610_MCBSP2_BASE 0xfffb1000
52#define OMAP1610_MCBSP3_BASE 0xe1017000 52#define OMAP1610_MCBSP3_BASE 0xe1017000
53 53
54#ifdef CONFIG_ARCH_OMAP1 54/* McBSP register numbers. Register address offset = num * reg_step */
55 55enum {
56#define OMAP_MCBSP_REG_DRR2 0x00 56 /* Common registers */
57#define OMAP_MCBSP_REG_DRR1 0x02 57 OMAP_MCBSP_REG_SPCR2 = 4,
58#define OMAP_MCBSP_REG_DXR2 0x04 58 OMAP_MCBSP_REG_SPCR1,
59#define OMAP_MCBSP_REG_DXR1 0x06 59 OMAP_MCBSP_REG_RCR2,
60#define OMAP_MCBSP_REG_DRR 0x02 60 OMAP_MCBSP_REG_RCR1,
61#define OMAP_MCBSP_REG_DXR 0x06 61 OMAP_MCBSP_REG_XCR2,
62#define OMAP_MCBSP_REG_SPCR2 0x08 62 OMAP_MCBSP_REG_XCR1,
63#define OMAP_MCBSP_REG_SPCR1 0x0a 63 OMAP_MCBSP_REG_SRGR2,
64#define OMAP_MCBSP_REG_RCR2 0x0c 64 OMAP_MCBSP_REG_SRGR1,
65#define OMAP_MCBSP_REG_RCR1 0x0e 65 OMAP_MCBSP_REG_MCR2,
66#define OMAP_MCBSP_REG_XCR2 0x10 66 OMAP_MCBSP_REG_MCR1,
67#define OMAP_MCBSP_REG_XCR1 0x12 67 OMAP_MCBSP_REG_RCERA,
68#define OMAP_MCBSP_REG_SRGR2 0x14 68 OMAP_MCBSP_REG_RCERB,
69#define OMAP_MCBSP_REG_SRGR1 0x16 69 OMAP_MCBSP_REG_XCERA,
70#define OMAP_MCBSP_REG_MCR2 0x18 70 OMAP_MCBSP_REG_XCERB,
71#define OMAP_MCBSP_REG_MCR1 0x1a 71 OMAP_MCBSP_REG_PCR0,
72#define OMAP_MCBSP_REG_RCERA 0x1c 72 OMAP_MCBSP_REG_RCERC,
73#define OMAP_MCBSP_REG_RCERB 0x1e 73 OMAP_MCBSP_REG_RCERD,
74#define OMAP_MCBSP_REG_XCERA 0x20 74 OMAP_MCBSP_REG_XCERC,
75#define OMAP_MCBSP_REG_XCERB 0x22 75 OMAP_MCBSP_REG_XCERD,
76#define OMAP_MCBSP_REG_PCR0 0x24 76 OMAP_MCBSP_REG_RCERE,
77#define OMAP_MCBSP_REG_RCERC 0x26 77 OMAP_MCBSP_REG_RCERF,
78#define OMAP_MCBSP_REG_RCERD 0x28 78 OMAP_MCBSP_REG_XCERE,
79#define OMAP_MCBSP_REG_XCERC 0x2A 79 OMAP_MCBSP_REG_XCERF,
80#define OMAP_MCBSP_REG_XCERD 0x2C 80 OMAP_MCBSP_REG_RCERG,
81#define OMAP_MCBSP_REG_RCERE 0x2E 81 OMAP_MCBSP_REG_RCERH,
82#define OMAP_MCBSP_REG_RCERF 0x30 82 OMAP_MCBSP_REG_XCERG,
83#define OMAP_MCBSP_REG_XCERE 0x32 83 OMAP_MCBSP_REG_XCERH,
84#define OMAP_MCBSP_REG_XCERF 0x34 84
85#define OMAP_MCBSP_REG_RCERG 0x36 85 /* OMAP1-OMAP2420 registers */
86#define OMAP_MCBSP_REG_RCERH 0x38 86 OMAP_MCBSP_REG_DRR2 = 0,
87#define OMAP_MCBSP_REG_XCERG 0x3A 87 OMAP_MCBSP_REG_DRR1,
88#define OMAP_MCBSP_REG_XCERH 0x3C 88 OMAP_MCBSP_REG_DXR2,
89 89 OMAP_MCBSP_REG_DXR1,
90/* Dummy defines, these are not available on omap1 */ 90
91#define OMAP_MCBSP_REG_XCCR 0x00 91 /* OMAP2430 and onwards */
92#define OMAP_MCBSP_REG_RCCR 0x00 92 OMAP_MCBSP_REG_DRR = 0,
93 93 OMAP_MCBSP_REG_DXR = 2,
94#else 94 OMAP_MCBSP_REG_SYSCON = 35,
95 95 OMAP_MCBSP_REG_THRSH2,
96#define OMAP_MCBSP_REG_DRR2 0x00 96 OMAP_MCBSP_REG_THRSH1,
97#define OMAP_MCBSP_REG_DRR1 0x04 97 OMAP_MCBSP_REG_IRQST = 40,
98#define OMAP_MCBSP_REG_DXR2 0x08 98 OMAP_MCBSP_REG_IRQEN,
99#define OMAP_MCBSP_REG_DXR1 0x0C 99 OMAP_MCBSP_REG_WAKEUPEN,
100#define OMAP_MCBSP_REG_DRR 0x00 100 OMAP_MCBSP_REG_XCCR,
101#define OMAP_MCBSP_REG_DXR 0x08 101 OMAP_MCBSP_REG_RCCR,
102#define OMAP_MCBSP_REG_SPCR2 0x10 102 OMAP_MCBSP_REG_XBUFFSTAT,
103#define OMAP_MCBSP_REG_SPCR1 0x14 103 OMAP_MCBSP_REG_RBUFFSTAT,
104#define OMAP_MCBSP_REG_RCR2 0x18 104 OMAP_MCBSP_REG_SSELCR,
105#define OMAP_MCBSP_REG_RCR1 0x1C 105};
106#define OMAP_MCBSP_REG_XCR2 0x20
107#define OMAP_MCBSP_REG_XCR1 0x24
108#define OMAP_MCBSP_REG_SRGR2 0x28
109#define OMAP_MCBSP_REG_SRGR1 0x2C
110#define OMAP_MCBSP_REG_MCR2 0x30
111#define OMAP_MCBSP_REG_MCR1 0x34
112#define OMAP_MCBSP_REG_RCERA 0x38
113#define OMAP_MCBSP_REG_RCERB 0x3C
114#define OMAP_MCBSP_REG_XCERA 0x40
115#define OMAP_MCBSP_REG_XCERB 0x44
116#define OMAP_MCBSP_REG_PCR0 0x48
117#define OMAP_MCBSP_REG_RCERC 0x4C
118#define OMAP_MCBSP_REG_RCERD 0x50
119#define OMAP_MCBSP_REG_XCERC 0x54
120#define OMAP_MCBSP_REG_XCERD 0x58
121#define OMAP_MCBSP_REG_RCERE 0x5C
122#define OMAP_MCBSP_REG_RCERF 0x60
123#define OMAP_MCBSP_REG_XCERE 0x64
124#define OMAP_MCBSP_REG_XCERF 0x68
125#define OMAP_MCBSP_REG_RCERG 0x6C
126#define OMAP_MCBSP_REG_RCERH 0x70
127#define OMAP_MCBSP_REG_XCERG 0x74
128#define OMAP_MCBSP_REG_XCERH 0x78
129#define OMAP_MCBSP_REG_SYSCON 0x8C
130#define OMAP_MCBSP_REG_THRSH2 0x90
131#define OMAP_MCBSP_REG_THRSH1 0x94
132#define OMAP_MCBSP_REG_IRQST 0xA0
133#define OMAP_MCBSP_REG_IRQEN 0xA4
134#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
135#define OMAP_MCBSP_REG_XCCR 0xAC
136#define OMAP_MCBSP_REG_RCCR 0xB0
137#define OMAP_MCBSP_REG_XBUFFSTAT 0xB4
138#define OMAP_MCBSP_REG_RBUFFSTAT 0xB8
139#define OMAP_MCBSP_REG_SSELCR 0xBC
140 106
107/* OMAP3 sidetone control registers */
141#define OMAP_ST_REG_REV 0x00 108#define OMAP_ST_REG_REV 0x00
142#define OMAP_ST_REG_SYSCONFIG 0x10 109#define OMAP_ST_REG_SYSCONFIG 0x10
143#define OMAP_ST_REG_IRQSTATUS 0x18 110#define OMAP_ST_REG_IRQSTATUS 0x18
@@ -146,8 +113,6 @@ static struct platform_device omap_mcbsp##port_nr = { \
146#define OMAP_ST_REG_SFIRCR 0x28 113#define OMAP_ST_REG_SFIRCR 0x28
147#define OMAP_ST_REG_SSELCR 0x2C 114#define OMAP_ST_REG_SSELCR 0x2C
148 115
149#endif
150
151/************************** McBSP SPCR1 bit definitions ***********************/ 116/************************** McBSP SPCR1 bit definitions ***********************/
152#define RRST 0x0001 117#define RRST 0x0001
153#define RRDY 0x0002 118#define RRDY 0x0002
@@ -350,7 +315,8 @@ struct omap_mcbsp_ops {
350struct omap_mcbsp_platform_data { 315struct omap_mcbsp_platform_data {
351 struct omap_mcbsp_ops *ops; 316 struct omap_mcbsp_ops *ops;
352 u16 buffer_size; 317 u16 buffer_size;
353 unsigned int mcbsp_config_type; 318 u8 reg_size;
319 u8 reg_step;
354}; 320};
355 321
356struct omap_mcbsp_st_data { 322struct omap_mcbsp_st_data {
@@ -389,7 +355,6 @@ struct omap_mcbsp {
389 u16 max_rx_thres; 355 u16 max_rx_thres;
390#endif 356#endif
391 void *reg_cache; 357 void *reg_cache;
392 unsigned int mcbsp_config_type;
393}; 358};
394 359
395/** 360/**
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 4b233e8cf905..623f2c1e9d4a 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -35,29 +35,27 @@ int omap_mcbsp_count, omap_mcbsp_cache_size;
35 35
36static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) 36static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
37{ 37{
38 if (cpu_class_is_omap1()) { 38 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
39 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val; 39
40 __raw_writew((u16)val, mcbsp->io_base + reg); 40 if (mcbsp->pdata->reg_size == 2) {
41 } else if (cpu_is_omap2420()) { 41 ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
42 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val; 42 __raw_writew((u16)val, addr);
43 __raw_writew((u16)val, mcbsp->io_base + reg);
44 } else { 43 } else {
45 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val; 44 ((u32 *)mcbsp->reg_cache)[reg] = val;
46 __raw_writel(val, mcbsp->io_base + reg); 45 __raw_writel(val, addr);
47 } 46 }
48} 47}
49 48
50static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache) 49static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
51{ 50{
52 if (cpu_class_is_omap1()) { 51 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
53 return !from_cache ? __raw_readw(mcbsp->io_base + reg) : 52
54 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)]; 53 if (mcbsp->pdata->reg_size == 2) {
55 } else if (cpu_is_omap2420()) { 54 return !from_cache ? __raw_readw(addr) :
56 return !from_cache ? __raw_readw(mcbsp->io_base + reg) : 55 ((u16 *)mcbsp->reg_cache)[reg];
57 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
58 } else { 56 } else {
59 return !from_cache ? __raw_readl(mcbsp->io_base + reg) : 57 return !from_cache ? __raw_readl(addr) :
60 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)]; 58 ((u32 *)mcbsp->reg_cache)[reg];
61 } 59 }
62} 60}
63 61
@@ -238,21 +236,19 @@ int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
238 } 236 }
239 mcbsp = id_to_mcbsp_ptr(id); 237 mcbsp = id_to_mcbsp_ptr(id);
240 238
241 data_reg = mcbsp->phys_dma_base; 239 if (mcbsp->pdata->reg_size == 2) {
242
243 if (mcbsp->mcbsp_config_type < MCBSP_CONFIG_TYPE2) {
244 if (stream) 240 if (stream)
245 data_reg += OMAP_MCBSP_REG_DRR1; 241 data_reg = OMAP_MCBSP_REG_DRR1;
246 else 242 else
247 data_reg += OMAP_MCBSP_REG_DXR1; 243 data_reg = OMAP_MCBSP_REG_DXR1;
248 } else { 244 } else {
249 if (stream) 245 if (stream)
250 data_reg += OMAP_MCBSP_REG_DRR; 246 data_reg = OMAP_MCBSP_REG_DRR;
251 else 247 else
252 data_reg += OMAP_MCBSP_REG_DXR; 248 data_reg = OMAP_MCBSP_REG_DXR;
253 } 249 }
254 250
255 return data_reg; 251 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
256} 252}
257EXPORT_SYMBOL(omap_mcbsp_dma_reg_params); 253EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
258 254
@@ -1337,7 +1333,6 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1337 mcbsp->pdata = pdata; 1333 mcbsp->pdata = pdata;
1338 mcbsp->dev = &pdev->dev; 1334 mcbsp->dev = &pdev->dev;
1339 mcbsp_ptr[id] = mcbsp; 1335 mcbsp_ptr[id] = mcbsp;
1340 mcbsp->mcbsp_config_type = pdata->mcbsp_config_type;
1341 platform_set_drvdata(pdev, mcbsp); 1336 platform_set_drvdata(pdev, mcbsp);
1342 pm_runtime_enable(mcbsp->dev); 1337 pm_runtime_enable(mcbsp->dev);
1343 1338