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authorLinus Torvalds <torvalds@linux-foundation.org>2010-10-25 16:46:56 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-10-25 16:46:56 -0400
commit7b6181e06841f5ad15c4ff708b967b4db65a64de (patch)
treebdfcf5b74b692f76581156e452d268b64c795200 /arch/arm/plat-omap
parent72e58063d63c5f0a7bf65312f1e3a5ed9bb5c2ff (diff)
parentbc487fb341af05120bccb9f59ce76302391dcc77 (diff)
Merge branch 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
* 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (163 commits) omap: complete removal of machine_desc.io_pg_offst and .phys_io omap: UART: fix wakeup registers for OMAP24xx UART2 omap: Fix spotty MMC voltages ASoC: OMAP4: MCPDM: Remove unnecessary include of plat/control.h serial: omap-serial: fix signess error OMAP3: DMA: Errata i541: sDMA FIFO draining does not finish omap: dma: Fix buffering disable bit setting for omap24xx omap: serial: Fix the boot-up crash/reboot without CONFIG_PM OMAP3: PM: fix scratchpad memory accesses for off-mode omap4: pandaboard: enable the ehci port on pandaboard omap4: pandaboard: Fix the init if CONFIG_MMC_OMAP_HS is not set omap4: pandaboard: remove unused hsmmc definition OMAP: McBSP: Remove null omap44xx ops comment OMAP: McBSP: Swap CLKS source definition OMAP: McBSP: Fix CLKR and FSR signal muxing OMAP2+: clock: reduce the amount of standard debugging while disabling unused clocks OMAP: control: move plat-omap/control.h to mach-omap2/control.h OMAP: split plat-omap/common.c OMAP: McBSP: implement functional clock switching via clock framework OMAP: McBSP: implement McBSP CLKR and FSR signal muxing via mach-omap2/mcbsp.c ... Fixed up trivial conflicts in arch/arm/mach-omap2/ {board-zoom-peripherals.c,devices.c} as per Tony
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r--arch/arm/plat-omap/Kconfig2
-rw-r--r--arch/arm/plat-omap/Makefile4
-rw-r--r--arch/arm/plat-omap/clock.c5
-rw-r--r--arch/arm/plat-omap/common.c290
-rw-r--r--arch/arm/plat-omap/counter_32k.c183
-rw-r--r--arch/arm/plat-omap/cpu-omap.c4
-rw-r--r--arch/arm/plat-omap/devices.c42
-rw-r--r--arch/arm/plat-omap/dma.c50
-rw-r--r--arch/arm/plat-omap/dmtimer.c2
-rw-r--r--arch/arm/plat-omap/fb.c2
-rw-r--r--arch/arm/plat-omap/fb.h10
-rw-r--r--arch/arm/plat-omap/gpio.c10
-rw-r--r--arch/arm/plat-omap/include/plat/common.h5
-rw-r--r--arch/arm/plat-omap/include/plat/control.h381
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h41
-rw-r--r--arch/arm/plat-omap/include/plat/dma.h6
-rw-r--r--arch/arm/plat-omap/include/plat/dmtimer.h2
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc-smsc911x.h35
-rw-r--r--arch/arm/plat-omap/include/plat/i2c.h4
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h2
-rw-r--r--arch/arm/plat-omap/include/plat/mcbsp.h22
-rw-r--r--arch/arm/plat-omap/include/plat/mmc.h12
-rw-r--r--arch/arm/plat-omap/include/plat/omap-serial.h128
-rw-r--r--arch/arm/plat-omap/include/plat/omap24xx.h2
-rw-r--r--arch/arm/plat-omap/include/plat/omap_device.h4
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h62
-rw-r--r--arch/arm/plat-omap/include/plat/powerdomain.h2
-rw-r--r--arch/arm/plat-omap/include/plat/prcm.h2
-rw-r--r--arch/arm/plat-omap/include/plat/sdrc.h1
-rw-r--r--arch/arm/plat-omap/include/plat/sram.h1
-rw-r--r--arch/arm/plat-omap/include/plat/timer-gp.h17
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h5
-rw-r--r--arch/arm/plat-omap/include/plat/usb.h2
-rw-r--r--arch/arm/plat-omap/mcbsp.c26
-rw-r--r--arch/arm/plat-omap/omap_device.c110
-rw-r--r--arch/arm/plat-omap/sram.c37
-rw-r--r--arch/arm/plat-omap/sram.h6
37 files changed, 645 insertions, 874 deletions
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index a92cb499313f..92c5bb7909f5 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -19,7 +19,7 @@ config ARCH_OMAP2PLUS
19 bool "TI OMAP2/3/4" 19 bool "TI OMAP2/3/4"
20 select COMMON_CLKDEV 20 select COMMON_CLKDEV
21 help 21 help
22 "Systems based on omap24xx, omap34xx or omap44xx" 22 "Systems based on OMAP2, OMAP3 or OMAP4"
23 23
24endchoice 24endchoice
25 25
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 9405831b746a..a4a12859fdd5 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -4,7 +4,7 @@
4 4
5# Common support 5# Common support
6obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \ 6obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \
7 usb.o fb.o io.o 7 usb.o fb.o io.o counter_32k.o
8obj-m := 8obj-m :=
9obj-n := 9obj-n :=
10obj- := 10obj- :=
@@ -31,4 +31,4 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y)
31# OMAP mailbox framework 31# OMAP mailbox framework
32obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o 32obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o
33 33
34obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o \ No newline at end of file 34obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 7190cbd92620..fc62fb5fc20b 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -60,7 +60,7 @@ void clk_disable(struct clk *clk)
60 60
61 spin_lock_irqsave(&clockfw_lock, flags); 61 spin_lock_irqsave(&clockfw_lock, flags);
62 if (clk->usecount == 0) { 62 if (clk->usecount == 0) {
63 printk(KERN_ERR "Trying disable clock %s with 0 usecount\n", 63 pr_err("Trying disable clock %s with 0 usecount\n",
64 clk->name); 64 clk->name);
65 WARN_ON(1); 65 WARN_ON(1);
66 goto out; 66 goto out;
@@ -397,6 +397,7 @@ static int __init clk_disable_unused(void)
397 struct clk *ck; 397 struct clk *ck;
398 unsigned long flags; 398 unsigned long flags;
399 399
400 pr_info("clock: disabling unused clocks to save power\n");
400 list_for_each_entry(ck, &clocks, node) { 401 list_for_each_entry(ck, &clocks, node) {
401 if (ck->ops == &clkops_null) 402 if (ck->ops == &clkops_null)
402 continue; 403 continue;
@@ -418,7 +419,7 @@ late_initcall(clk_disable_unused);
418int __init clk_init(struct clk_functions * custom_clocks) 419int __init clk_init(struct clk_functions * custom_clocks)
419{ 420{
420 if (!custom_clocks) { 421 if (!custom_clocks) {
421 printk(KERN_ERR "No custom clock functions registered\n"); 422 pr_err("No custom clock functions registered\n");
422 BUG(); 423 BUG();
423 } 424 }
424 425
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 3008e7104487..221a675ebbae 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -11,38 +11,15 @@
11 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 */ 13 */
14#include <linux/module.h>
15#include <linux/kernel.h> 14#include <linux/kernel.h>
16#include <linux/init.h> 15#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/console.h>
19#include <linux/serial.h>
20#include <linux/tty.h>
21#include <linux/serial_8250.h>
22#include <linux/serial_reg.h>
23#include <linux/clk.h>
24#include <linux/io.h> 16#include <linux/io.h>
25#include <linux/omapfb.h> 17#include <linux/omapfb.h>
26 18
27#include <mach/hardware.h>
28#include <asm/system.h>
29#include <asm/pgtable.h>
30#include <asm/mach/map.h>
31#include <asm/setup.h>
32
33#include <plat/common.h> 19#include <plat/common.h>
34#include <plat/board.h> 20#include <plat/board.h>
35#include <plat/control.h>
36#include <plat/mux.h>
37#include <plat/fpga.h>
38#include <plat/serial.h>
39#include <plat/vram.h> 21#include <plat/vram.h>
40 22
41#include <plat/clock.h>
42
43#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
44# include "../mach-omap2/sdrc.h"
45#endif
46 23
47#define NO_LENGTH_CHECK 0xffffffff 24#define NO_LENGTH_CHECK 0xffffffff
48 25
@@ -88,270 +65,3 @@ void __init omap_reserve(void)
88 omapfb_reserve_sdram_memblock(); 65 omapfb_reserve_sdram_memblock();
89 omap_vram_reserve_sdram_memblock(); 66 omap_vram_reserve_sdram_memblock();
90} 67}
91
92/*
93 * 32KHz clocksource ... always available, on pretty most chips except
94 * OMAP 730 and 1510. Other timers could be used as clocksources, with
95 * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
96 * but systems won't necessarily want to spend resources that way.
97 */
98
99#define OMAP16XX_TIMER_32K_SYNCHRONIZED 0xfffbc410
100
101#if !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX))
102
103#include <linux/clocksource.h>
104
105/*
106 * offset_32k holds the init time counter value. It is then subtracted
107 * from every counter read to achieve a counter that counts time from the
108 * kernel boot (needed for sched_clock()).
109 */
110static u32 offset_32k __read_mostly;
111
112#ifdef CONFIG_ARCH_OMAP16XX
113static cycle_t omap16xx_32k_read(struct clocksource *cs)
114{
115 return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k;
116}
117#else
118#define omap16xx_32k_read NULL
119#endif
120
121#ifdef CONFIG_ARCH_OMAP2420
122static cycle_t omap2420_32k_read(struct clocksource *cs)
123{
124 return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k;
125}
126#else
127#define omap2420_32k_read NULL
128#endif
129
130#ifdef CONFIG_ARCH_OMAP2430
131static cycle_t omap2430_32k_read(struct clocksource *cs)
132{
133 return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k;
134}
135#else
136#define omap2430_32k_read NULL
137#endif
138
139#ifdef CONFIG_ARCH_OMAP3
140static cycle_t omap34xx_32k_read(struct clocksource *cs)
141{
142 return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k;
143}
144#else
145#define omap34xx_32k_read NULL
146#endif
147
148#ifdef CONFIG_ARCH_OMAP4
149static cycle_t omap44xx_32k_read(struct clocksource *cs)
150{
151 return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k;
152}
153#else
154#define omap44xx_32k_read NULL
155#endif
156
157/*
158 * Kernel assumes that sched_clock can be called early but may not have
159 * things ready yet.
160 */
161static cycle_t omap_32k_read_dummy(struct clocksource *cs)
162{
163 return 0;
164}
165
166static struct clocksource clocksource_32k = {
167 .name = "32k_counter",
168 .rating = 250,
169 .read = omap_32k_read_dummy,
170 .mask = CLOCKSOURCE_MASK(32),
171 .shift = 10,
172 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
173};
174
175/*
176 * Returns current time from boot in nsecs. It's OK for this to wrap
177 * around for now, as it's just a relative time stamp.
178 */
179unsigned long long sched_clock(void)
180{
181 return clocksource_cyc2ns(clocksource_32k.read(&clocksource_32k),
182 clocksource_32k.mult, clocksource_32k.shift);
183}
184
185/**
186 * read_persistent_clock - Return time from a persistent clock.
187 *
188 * Reads the time from a source which isn't disabled during PM, the
189 * 32k sync timer. Convert the cycles elapsed since last read into
190 * nsecs and adds to a monotonically increasing timespec.
191 */
192static struct timespec persistent_ts;
193static cycles_t cycles, last_cycles;
194void read_persistent_clock(struct timespec *ts)
195{
196 unsigned long long nsecs;
197 cycles_t delta;
198 struct timespec *tsp = &persistent_ts;
199
200 last_cycles = cycles;
201 cycles = clocksource_32k.read(&clocksource_32k);
202 delta = cycles - last_cycles;
203
204 nsecs = clocksource_cyc2ns(delta,
205 clocksource_32k.mult, clocksource_32k.shift);
206
207 timespec_add_ns(tsp, nsecs);
208 *ts = *tsp;
209}
210
211static int __init omap_init_clocksource_32k(void)
212{
213 static char err[] __initdata = KERN_ERR
214 "%s: can't register clocksource!\n";
215
216 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
217 struct clk *sync_32k_ick;
218
219 if (cpu_is_omap16xx())
220 clocksource_32k.read = omap16xx_32k_read;
221 else if (cpu_is_omap2420())
222 clocksource_32k.read = omap2420_32k_read;
223 else if (cpu_is_omap2430())
224 clocksource_32k.read = omap2430_32k_read;
225 else if (cpu_is_omap34xx())
226 clocksource_32k.read = omap34xx_32k_read;
227 else if (cpu_is_omap44xx())
228 clocksource_32k.read = omap44xx_32k_read;
229 else
230 return -ENODEV;
231
232 sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
233 if (sync_32k_ick)
234 clk_enable(sync_32k_ick);
235
236 clocksource_32k.mult = clocksource_hz2mult(32768,
237 clocksource_32k.shift);
238
239 offset_32k = clocksource_32k.read(&clocksource_32k);
240
241 if (clocksource_register(&clocksource_32k))
242 printk(err, clocksource_32k.name);
243 }
244 return 0;
245}
246arch_initcall(omap_init_clocksource_32k);
247
248#endif /* !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) */
249
250/* Global address base setup code */
251
252#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
253
254static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
255{
256 omap2_set_globals_tap(omap2_globals);
257 omap2_set_globals_sdrc(omap2_globals);
258 omap2_set_globals_control(omap2_globals);
259 omap2_set_globals_prcm(omap2_globals);
260 omap2_set_globals_uart(omap2_globals);
261}
262
263#endif
264
265#if defined(CONFIG_ARCH_OMAP2420)
266
267static struct omap_globals omap242x_globals = {
268 .class = OMAP242X_CLASS,
269 .tap = OMAP2_L4_IO_ADDRESS(0x48014000),
270 .sdrc = OMAP2420_SDRC_BASE,
271 .sms = OMAP2420_SMS_BASE,
272 .ctrl = OMAP2420_CTRL_BASE,
273 .prm = OMAP2420_PRM_BASE,
274 .cm = OMAP2420_CM_BASE,
275 .uart1_phys = OMAP2_UART1_BASE,
276 .uart2_phys = OMAP2_UART2_BASE,
277 .uart3_phys = OMAP2_UART3_BASE,
278};
279
280void __init omap2_set_globals_242x(void)
281{
282 __omap2_set_globals(&omap242x_globals);
283}
284#endif
285
286#if defined(CONFIG_ARCH_OMAP2430)
287
288static struct omap_globals omap243x_globals = {
289 .class = OMAP243X_CLASS,
290 .tap = OMAP2_L4_IO_ADDRESS(0x4900a000),
291 .sdrc = OMAP243X_SDRC_BASE,
292 .sms = OMAP243X_SMS_BASE,
293 .ctrl = OMAP243X_CTRL_BASE,
294 .prm = OMAP2430_PRM_BASE,
295 .cm = OMAP2430_CM_BASE,
296 .uart1_phys = OMAP2_UART1_BASE,
297 .uart2_phys = OMAP2_UART2_BASE,
298 .uart3_phys = OMAP2_UART3_BASE,
299};
300
301void __init omap2_set_globals_243x(void)
302{
303 __omap2_set_globals(&omap243x_globals);
304}
305#endif
306
307#if defined(CONFIG_ARCH_OMAP3)
308
309static struct omap_globals omap3_globals = {
310 .class = OMAP343X_CLASS,
311 .tap = OMAP2_L4_IO_ADDRESS(0x4830A000),
312 .sdrc = OMAP343X_SDRC_BASE,
313 .sms = OMAP343X_SMS_BASE,
314 .ctrl = OMAP343X_CTRL_BASE,
315 .prm = OMAP3430_PRM_BASE,
316 .cm = OMAP3430_CM_BASE,
317 .uart1_phys = OMAP3_UART1_BASE,
318 .uart2_phys = OMAP3_UART2_BASE,
319 .uart3_phys = OMAP3_UART3_BASE,
320 .uart4_phys = OMAP3_UART4_BASE, /* Only on 3630 */
321};
322
323void __init omap2_set_globals_3xxx(void)
324{
325 __omap2_set_globals(&omap3_globals);
326}
327
328void __init omap3_map_io(void)
329{
330 omap2_set_globals_3xxx();
331 omap34xx_map_common_io();
332}
333#endif
334
335#if defined(CONFIG_ARCH_OMAP4)
336static struct omap_globals omap4_globals = {
337 .class = OMAP443X_CLASS,
338 .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
339 .ctrl = OMAP443X_CTRL_BASE,
340 .prm = OMAP4430_PRM_BASE,
341 .cm = OMAP4430_CM_BASE,
342 .cm2 = OMAP4430_CM2_BASE,
343 .uart1_phys = OMAP4_UART1_BASE,
344 .uart2_phys = OMAP4_UART2_BASE,
345 .uart3_phys = OMAP4_UART3_BASE,
346 .uart4_phys = OMAP4_UART4_BASE,
347};
348
349void __init omap2_set_globals_443x(void)
350{
351 omap2_set_globals_tap(&omap4_globals);
352 omap2_set_globals_control(&omap4_globals);
353 omap2_set_globals_prcm(&omap4_globals);
354 omap2_set_globals_uart(&omap4_globals);
355}
356#endif
357
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
new file mode 100644
index 000000000000..155fe43a672b
--- /dev/null
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -0,0 +1,183 @@
1/*
2 * OMAP 32ksynctimer/counter_32k-related code
3 *
4 * Copyright (C) 2009 Texas Instruments
5 * Copyright (C) 2010 Nokia Corporation
6 * Tony Lindgren <tony@atomide.com>
7 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * NOTE: This timer is not the same timer as the old OMAP1 MPU timer.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/clk.h>
18#include <linux/io.h>
19
20#include <plat/common.h>
21#include <plat/board.h>
22
23#include <plat/clock.h>
24
25
26/*
27 * 32KHz clocksource ... always available, on pretty most chips except
28 * OMAP 730 and 1510. Other timers could be used as clocksources, with
29 * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
30 * but systems won't necessarily want to spend resources that way.
31 */
32
33#define OMAP16XX_TIMER_32K_SYNCHRONIZED 0xfffbc410
34
35#if !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX))
36
37#include <linux/clocksource.h>
38
39/*
40 * offset_32k holds the init time counter value. It is then subtracted
41 * from every counter read to achieve a counter that counts time from the
42 * kernel boot (needed for sched_clock()).
43 */
44static u32 offset_32k __read_mostly;
45
46#ifdef CONFIG_ARCH_OMAP16XX
47static cycle_t omap16xx_32k_read(struct clocksource *cs)
48{
49 return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k;
50}
51#else
52#define omap16xx_32k_read NULL
53#endif
54
55#ifdef CONFIG_ARCH_OMAP2420
56static cycle_t omap2420_32k_read(struct clocksource *cs)
57{
58 return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k;
59}
60#else
61#define omap2420_32k_read NULL
62#endif
63
64#ifdef CONFIG_ARCH_OMAP2430
65static cycle_t omap2430_32k_read(struct clocksource *cs)
66{
67 return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k;
68}
69#else
70#define omap2430_32k_read NULL
71#endif
72
73#ifdef CONFIG_ARCH_OMAP3
74static cycle_t omap34xx_32k_read(struct clocksource *cs)
75{
76 return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k;
77}
78#else
79#define omap34xx_32k_read NULL
80#endif
81
82#ifdef CONFIG_ARCH_OMAP4
83static cycle_t omap44xx_32k_read(struct clocksource *cs)
84{
85 return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k;
86}
87#else
88#define omap44xx_32k_read NULL
89#endif
90
91/*
92 * Kernel assumes that sched_clock can be called early but may not have
93 * things ready yet.
94 */
95static cycle_t omap_32k_read_dummy(struct clocksource *cs)
96{
97 return 0;
98}
99
100static struct clocksource clocksource_32k = {
101 .name = "32k_counter",
102 .rating = 250,
103 .read = omap_32k_read_dummy,
104 .mask = CLOCKSOURCE_MASK(32),
105 .shift = 10,
106 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
107};
108
109/*
110 * Returns current time from boot in nsecs. It's OK for this to wrap
111 * around for now, as it's just a relative time stamp.
112 */
113unsigned long long sched_clock(void)
114{
115 return clocksource_cyc2ns(clocksource_32k.read(&clocksource_32k),
116 clocksource_32k.mult, clocksource_32k.shift);
117}
118
119/**
120 * read_persistent_clock - Return time from a persistent clock.
121 *
122 * Reads the time from a source which isn't disabled during PM, the
123 * 32k sync timer. Convert the cycles elapsed since last read into
124 * nsecs and adds to a monotonically increasing timespec.
125 */
126static struct timespec persistent_ts;
127static cycles_t cycles, last_cycles;
128void read_persistent_clock(struct timespec *ts)
129{
130 unsigned long long nsecs;
131 cycles_t delta;
132 struct timespec *tsp = &persistent_ts;
133
134 last_cycles = cycles;
135 cycles = clocksource_32k.read(&clocksource_32k);
136 delta = cycles - last_cycles;
137
138 nsecs = clocksource_cyc2ns(delta,
139 clocksource_32k.mult, clocksource_32k.shift);
140
141 timespec_add_ns(tsp, nsecs);
142 *ts = *tsp;
143}
144
145static int __init omap_init_clocksource_32k(void)
146{
147 static char err[] __initdata = KERN_ERR
148 "%s: can't register clocksource!\n";
149
150 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
151 struct clk *sync_32k_ick;
152
153 if (cpu_is_omap16xx())
154 clocksource_32k.read = omap16xx_32k_read;
155 else if (cpu_is_omap2420())
156 clocksource_32k.read = omap2420_32k_read;
157 else if (cpu_is_omap2430())
158 clocksource_32k.read = omap2430_32k_read;
159 else if (cpu_is_omap34xx())
160 clocksource_32k.read = omap34xx_32k_read;
161 else if (cpu_is_omap44xx())
162 clocksource_32k.read = omap44xx_32k_read;
163 else
164 return -ENODEV;
165
166 sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
167 if (sync_32k_ick)
168 clk_enable(sync_32k_ick);
169
170 clocksource_32k.mult = clocksource_hz2mult(32768,
171 clocksource_32k.shift);
172
173 offset_32k = clocksource_32k.read(&clocksource_32k);
174
175 if (clocksource_register(&clocksource_32k))
176 printk(err, clocksource_32k.name);
177 }
178 return 0;
179}
180arch_initcall(omap_init_clocksource_32k);
181
182#endif /* !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) */
183
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
index 6d3d33360056..11c54ec8d47f 100644
--- a/arch/arm/plat-omap/cpu-omap.c
+++ b/arch/arm/plat-omap/cpu-omap.c
@@ -40,7 +40,7 @@ static struct clk *mpu_clk;
40 40
41/* TODO: Add support for SDRAM timing changes */ 41/* TODO: Add support for SDRAM timing changes */
42 42
43int omap_verify_speed(struct cpufreq_policy *policy) 43static int omap_verify_speed(struct cpufreq_policy *policy)
44{ 44{
45 if (freq_table) 45 if (freq_table)
46 return cpufreq_frequency_table_verify(policy, freq_table); 46 return cpufreq_frequency_table_verify(policy, freq_table);
@@ -58,7 +58,7 @@ int omap_verify_speed(struct cpufreq_policy *policy)
58 return 0; 58 return 0;
59} 59}
60 60
61unsigned int omap_getspeed(unsigned int cpu) 61static unsigned int omap_getspeed(unsigned int cpu)
62{ 62{
63 unsigned long rate; 63 unsigned long rate;
64 64
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index d1920be7833b..1e2383eae638 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -21,7 +21,6 @@
21#include <asm/mach/map.h> 21#include <asm/mach/map.h>
22 22
23#include <plat/tc.h> 23#include <plat/tc.h>
24#include <plat/control.h>
25#include <plat/board.h> 24#include <plat/board.h>
26#include <plat/mmc.h> 25#include <plat/mmc.h>
27#include <mach/gpio.h> 26#include <mach/gpio.h>
@@ -232,46 +231,6 @@ static void omap_init_uwire(void)
232static inline void omap_init_uwire(void) {} 231static inline void omap_init_uwire(void) {}
233#endif 232#endif
234 233
235/*-------------------------------------------------------------------------*/
236
237#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
238
239static struct resource wdt_resources[] = {
240 {
241 .flags = IORESOURCE_MEM,
242 },
243};
244
245static struct platform_device omap_wdt_device = {
246 .name = "omap_wdt",
247 .id = -1,
248 .num_resources = ARRAY_SIZE(wdt_resources),
249 .resource = wdt_resources,
250};
251
252static void omap_init_wdt(void)
253{
254 if (cpu_is_omap16xx())
255 wdt_resources[0].start = 0xfffeb000;
256 else if (cpu_is_omap2420())
257 wdt_resources[0].start = 0x48022000; /* WDT2 */
258 else if (cpu_is_omap2430())
259 wdt_resources[0].start = 0x49016000; /* WDT2 */
260 else if (cpu_is_omap343x())
261 wdt_resources[0].start = 0x48314000; /* WDT2 */
262 else if (cpu_is_omap44xx())
263 wdt_resources[0].start = 0x4a314000;
264 else
265 return;
266
267 wdt_resources[0].end = wdt_resources[0].start + 0x4f;
268
269 (void) platform_device_register(&omap_wdt_device);
270}
271#else
272static inline void omap_init_wdt(void) {}
273#endif
274
275/* 234/*
276 * This gets called after board-specific INIT_MACHINE, and initializes most 235 * This gets called after board-specific INIT_MACHINE, and initializes most
277 * on-chip peripherals accessible on this board (except for few like USB): 236 * on-chip peripherals accessible on this board (except for few like USB):
@@ -300,7 +259,6 @@ static int __init omap_init_devices(void)
300 omap_init_rng(); 259 omap_init_rng();
301 omap_init_mcpdm(); 260 omap_init_mcpdm();
302 omap_init_uwire(); 261 omap_init_uwire();
303 omap_init_wdt();
304 return 0; 262 return 0;
305} 263}
306arch_initcall(omap_init_devices); 264arch_initcall(omap_init_devices);
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index ec7eddf9e525..f5c5b8da9a87 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -30,6 +30,7 @@
30#include <linux/irq.h> 30#include <linux/irq.h>
31#include <linux/io.h> 31#include <linux/io.h>
32#include <linux/slab.h> 32#include <linux/slab.h>
33#include <linux/delay.h>
33 34
34#include <asm/system.h> 35#include <asm/system.h>
35#include <mach/hardware.h> 36#include <mach/hardware.h>
@@ -996,11 +997,17 @@ void omap_start_dma(int lch)
996 l = dma_read(CCR(lch)); 997 l = dma_read(CCR(lch));
997 998
998 /* 999 /*
999 * Errata: On ES2.0 BUFFERING disable must be set. 1000 * Errata: Inter Frame DMA buffering issue (All OMAP2420 and
1000 * This will always fail on ES1.0 1001 * OMAP2430ES1.0): DMA will wrongly buffer elements if packing and
1002 * bursting is enabled. This might result in data gets stalled in
1003 * FIFO at the end of the block.
1004 * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
1005 * guarantee no data will stay in the DMA FIFO in case inter frame
1006 * buffering occurs.
1001 */ 1007 */
1002 if (cpu_is_omap24xx()) 1008 if (cpu_is_omap2420() ||
1003 l |= OMAP_DMA_CCR_EN; 1009 (cpu_is_omap2430() && (omap_type() == OMAP2430_REV_ES1_0)))
1010 l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
1004 1011
1005 l |= OMAP_DMA_CCR_EN; 1012 l |= OMAP_DMA_CCR_EN;
1006 dma_write(l, CCR(lch)); 1013 dma_write(l, CCR(lch));
@@ -1018,8 +1025,39 @@ void omap_stop_dma(int lch)
1018 dma_write(0, CICR(lch)); 1025 dma_write(0, CICR(lch));
1019 1026
1020 l = dma_read(CCR(lch)); 1027 l = dma_read(CCR(lch));
1021 l &= ~OMAP_DMA_CCR_EN; 1028 /* OMAP3 Errata i541: sDMA FIFO draining does not finish */
1022 dma_write(l, CCR(lch)); 1029 if (cpu_is_omap34xx() && (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
1030 int i = 0;
1031 u32 sys_cf;
1032
1033 /* Configure No-Standby */
1034 l = dma_read(OCP_SYSCONFIG);
1035 sys_cf = l;
1036 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
1037 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
1038 dma_write(l , OCP_SYSCONFIG);
1039
1040 l = dma_read(CCR(lch));
1041 l &= ~OMAP_DMA_CCR_EN;
1042 dma_write(l, CCR(lch));
1043
1044 /* Wait for sDMA FIFO drain */
1045 l = dma_read(CCR(lch));
1046 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
1047 OMAP_DMA_CCR_WR_ACTIVE))) {
1048 udelay(5);
1049 i++;
1050 l = dma_read(CCR(lch));
1051 }
1052 if (i >= 100)
1053 printk(KERN_ERR "DMA drain did not complete on "
1054 "lch %d\n", lch);
1055 /* Restore OCP_SYSCONFIG */
1056 dma_write(sys_cf, OCP_SYSCONFIG);
1057 } else {
1058 l &= ~OMAP_DMA_CCR_EN;
1059 dma_write(l, CCR(lch));
1060 }
1023 1061
1024 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { 1062 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
1025 int next_lch, cur_lch = lch; 1063 int next_lch, cur_lch = lch;
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 44bafdab2dce..1d706cf63ca0 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -581,7 +581,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
581 * When the functional clock disappears, too quick writes seem 581 * When the functional clock disappears, too quick writes seem
582 * to cause an abort. XXX Is this still necessary? 582 * to cause an abort. XXX Is this still necessary?
583 */ 583 */
584 __delay(150000); 584 __delay(300000);
585 585
586 return ret; 586 return ret;
587} 587}
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index 71934817e172..bb78c1532fae 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -36,6 +36,8 @@
36#include <plat/board.h> 36#include <plat/board.h>
37#include <plat/sram.h> 37#include <plat/sram.h>
38 38
39#include "fb.h"
40
39#if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE) 41#if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
40 42
41static struct omapfb_platform_data omapfb_config; 43static struct omapfb_platform_data omapfb_config;
diff --git a/arch/arm/plat-omap/fb.h b/arch/arm/plat-omap/fb.h
new file mode 100644
index 000000000000..d765d0bd8520
--- /dev/null
+++ b/arch/arm/plat-omap/fb.h
@@ -0,0 +1,10 @@
1#ifndef __PLAT_OMAP_FB_H__
2#define __PLAT_OMAP_FB_H__
3
4extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
5 unsigned long sram_vstart,
6 unsigned long sram_size,
7 unsigned long pstart_avail,
8 unsigned long size_avail);
9
10#endif /* __PLAT_OMAP_FB_H__ */
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 7951eefe1a0e..c05c653d1674 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -2084,9 +2084,10 @@ void omap2_gpio_prepare_for_idle(int power_state)
2084 2084
2085 for (i = min; i < gpio_bank_count; i++) { 2085 for (i = min; i < gpio_bank_count; i++) {
2086 struct gpio_bank *bank = &gpio_bank[i]; 2086 struct gpio_bank *bank = &gpio_bank[i];
2087 u32 l1, l2; 2087 u32 l1 = 0, l2 = 0;
2088 int j;
2088 2089
2089 if (bank->dbck_enable_mask) 2090 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
2090 clk_disable(bank->dbck); 2091 clk_disable(bank->dbck);
2091 2092
2092 if (power_state > PWRDM_POWER_OFF) 2093 if (power_state > PWRDM_POWER_OFF)
@@ -2151,9 +2152,10 @@ void omap2_gpio_resume_after_idle(void)
2151 min = 1; 2152 min = 1;
2152 for (i = min; i < gpio_bank_count; i++) { 2153 for (i = min; i < gpio_bank_count; i++) {
2153 struct gpio_bank *bank = &gpio_bank[i]; 2154 struct gpio_bank *bank = &gpio_bank[i];
2154 u32 l, gen, gen0, gen1; 2155 u32 l = 0, gen, gen0, gen1;
2156 int j;
2155 2157
2156 if (bank->dbck_enable_mask) 2158 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
2157 clk_enable(bank->dbck); 2159 clk_enable(bank->dbck);
2158 2160
2159 if (!workaround_enabled) 2161 if (!workaround_enabled)
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 9776b41ad76f..a9d69a09920d 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -47,6 +47,7 @@ struct omap_globals {
47 unsigned long sdrc; /* SDRAM Controller */ 47 unsigned long sdrc; /* SDRAM Controller */
48 unsigned long sms; /* SDRAM Memory Scheduler */ 48 unsigned long sms; /* SDRAM Memory Scheduler */
49 unsigned long ctrl; /* System Control Module */ 49 unsigned long ctrl; /* System Control Module */
50 unsigned long ctrl_pad; /* PAD Control Module */
50 unsigned long prm; /* Power and Reset Management */ 51 unsigned long prm; /* Power and Reset Management */
51 unsigned long cm; /* Clock Management */ 52 unsigned long cm; /* Clock Management */
52 unsigned long cm2; 53 unsigned long cm2;
@@ -66,7 +67,6 @@ void omap2_set_globals_tap(struct omap_globals *);
66void omap2_set_globals_sdrc(struct omap_globals *); 67void omap2_set_globals_sdrc(struct omap_globals *);
67void omap2_set_globals_control(struct omap_globals *); 68void omap2_set_globals_control(struct omap_globals *);
68void omap2_set_globals_prcm(struct omap_globals *); 69void omap2_set_globals_prcm(struct omap_globals *);
69void omap2_set_globals_uart(struct omap_globals *);
70 70
71void omap3_map_io(void); 71void omap3_map_io(void);
72 72
@@ -91,7 +91,8 @@ void omap3_map_io(void);
91}) 91})
92 92
93extern struct device *omap2_get_mpuss_device(void); 93extern struct device *omap2_get_mpuss_device(void);
94extern struct device *omap2_get_dsp_device(void); 94extern struct device *omap2_get_iva_device(void);
95extern struct device *omap2_get_l3_device(void); 95extern struct device *omap2_get_l3_device(void);
96extern struct device *omap4_get_dsp_device(void);
96 97
97#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ 98#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
deleted file mode 100644
index 131bf405c2f6..000000000000
--- a/arch/arm/plat-omap/include/plat/control.h
+++ /dev/null
@@ -1,381 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/control.h
3 *
4 * OMAP2/3/4 System Control Module definitions
5 *
6 * Copyright (C) 2007-2009 Texas Instruments, Inc.
7 * Copyright (C) 2007-2008 Nokia Corporation
8 *
9 * Written by Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation.
14 */
15
16#ifndef __ASM_ARCH_CONTROL_H
17#define __ASM_ARCH_CONTROL_H
18
19#include <mach/io.h>
20
21#ifndef __ASSEMBLY__
22#define OMAP242X_CTRL_REGADDR(reg) \
23 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
24#define OMAP243X_CTRL_REGADDR(reg) \
25 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
26#define OMAP343X_CTRL_REGADDR(reg) \
27 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
28#else
29#define OMAP242X_CTRL_REGADDR(reg) \
30 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
31#define OMAP243X_CTRL_REGADDR(reg) \
32 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
33#define OMAP343X_CTRL_REGADDR(reg) \
34 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
35#endif /* __ASSEMBLY__ */
36
37/*
38 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
39 * OMAP24XX and OMAP34XX.
40 */
41
42/* Control submodule offsets */
43
44#define OMAP2_CONTROL_INTERFACE 0x000
45#define OMAP2_CONTROL_PADCONFS 0x030
46#define OMAP2_CONTROL_GENERAL 0x270
47#define OMAP343X_CONTROL_MEM_WKUP 0x600
48#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
49#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
50
51/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
52
53#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
54
55/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
56#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004)
57#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020)
58#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024)
59#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028)
60#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c)
61#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030)
62#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034)
63#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040)
64#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090)
65#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094)
66#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098)
67#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c)
68
69/* 242x-only CONTROL_GENERAL register offsets */
70#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */
71#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068)
72
73/* 243x-only CONTROL_GENERAL register offsets */
74/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
75#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078)
76#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c)
77#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
78#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
79#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198)
80#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230)
81
82/* 24xx-only CONTROL_GENERAL register offsets */
83#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000)
84#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008)
85#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044)
86#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048)
87#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c)
88#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050)
89#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060)
90#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
91#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
92#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
93#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074)
94#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
95#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
96#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)
97#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
98#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0)
99#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4)
100#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8)
101#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac)
102#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0)
103#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4)
104#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0)
105#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4)
106#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8)
107#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc)
108#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0)
109#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4)
110#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8)
111#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc)
112#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
113#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
114
115#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
116
117/* 34xx-only CONTROL_GENERAL register offsets */
118#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000)
119#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
120#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c)
121#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068)
122#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c)
123#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070)
124#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074)
125#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078)
126#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
127#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
128#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0)
129#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8)
130#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac)
131#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0)
132#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4)
133#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8)
134#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc)
135#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0)
136#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4)
137#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8)
138#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc)
139#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0)
140#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4)
141#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8)
142#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec)
143#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0)
144#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4)
145#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8)
146#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
147#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
148#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
149#define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \
150 + ((i) >> 1) * 4 + (!((i) & 1)) * 2)
151#define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4)
152#define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8)
153#define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0)
154#define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4)
155#define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8)
156#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
157#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0)
158#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4)
159#define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8)
160#define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0)
161#define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4)
162
163/* AM35XX only CONTROL_GENERAL register offsets */
164#define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038)
165#define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310)
166#define AM35XX_CONTROL_DEVCONF3 (OMAP2_CONTROL_GENERAL + 0x0314)
167#define AM35XX_CONTROL_CBA_PRIORITY (OMAP2_CONTROL_GENERAL + 0x0320)
168#define AM35XX_CONTROL_LVL_INTR_CLEAR (OMAP2_CONTROL_GENERAL + 0x0324)
169#define AM35XX_CONTROL_IP_SW_RESET (OMAP2_CONTROL_GENERAL + 0x0328)
170#define AM35XX_CONTROL_IPSS_CLK_CTRL (OMAP2_CONTROL_GENERAL + 0x032C)
171
172/* 34xx PADCONF register offsets */
173#define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
174 (i)*2)
175#define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0)
176#define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1)
177#define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2)
178#define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3)
179#define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4)
180#define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5)
181#define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6)
182#define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7)
183#define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8)
184#define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9)
185#define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10)
186#define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11)
187#define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12)
188#define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13)
189#define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14)
190#define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15)
191#define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16)
192#define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17)
193
194/* 34xx GENERAL_WKUP regist offsets */
195#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
196 0x008 + (i))
197#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
198#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
199#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
200#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
201#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
202
203/* 34xx D2D idle-related pins, handled by PM core */
204#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
205#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
206
207/* 44xx control status register offset */
208#define OMAP44XX_CONTROL_STATUS 0x2c4
209
210/* 44xx-only CONTROL_GENERAL register offsets */
211#define OMAP44XX_CONTROL_MMC1 0x628
212#define OMAP44XX_CONTROL_PBIAS_LITE 0x600
213/*
214 * REVISIT: This list of registers is not comprehensive - there are more
215 * that should be added.
216 */
217
218/*
219 * Control module register bit defines - these should eventually go into
220 * their own regbits file. Some of these will be complicated, depending
221 * on the device type (general-purpose, emulator, test, secure, bad, other)
222 * and the security mode (secure, non-secure, don't care)
223 */
224/* CONTROL_DEVCONF0 bits */
225#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */
226#define OMAP24XX_USBSTANDBYCTRL (1 << 15)
227#define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
228#define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
229
230/* CONTROL_DEVCONF1 bits */
231#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31)
232#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */
233#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
234#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
235#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */
236
237/* CONTROL_STATUS bits */
238#define OMAP2_DEVICETYPE_MASK (0x7 << 8)
239#define OMAP2_SYSBOOT_5_MASK (1 << 5)
240#define OMAP2_SYSBOOT_4_MASK (1 << 4)
241#define OMAP2_SYSBOOT_3_MASK (1 << 3)
242#define OMAP2_SYSBOOT_2_MASK (1 << 2)
243#define OMAP2_SYSBOOT_1_MASK (1 << 1)
244#define OMAP2_SYSBOOT_0_MASK (1 << 0)
245
246/* CONTROL_PBIAS_LITE bits */
247#define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15)
248#define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11)
249#define OMAP343X_PBIASSPEEDCTRL1 (1 << 10)
250#define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9)
251#define OMAP343X_PBIASLITEVMODE1 (1 << 8)
252#define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7)
253#define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3)
254#define OMAP2_PBIASSPEEDCTRL0 (1 << 2)
255#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
256#define OMAP2_PBIASLITEVMODE0 (1 << 0)
257
258/* CONTROL_PBIAS_LITE bits for OMAP4 */
259#define OMAP4_MMC1_PWRDNZ (1 << 26)
260#define OMAP4_MMC1_PBIASLITE_HIZ_MODE (1 << 25)
261#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT (1 << 24)
262#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR (1 << 23)
263#define OMAP4_MMC1_PBIASLITE_PWRDNZ (1 << 22)
264#define OMAP4_MMC1_PBIASLITE_VMODE (1 << 21)
265#define OMAP4_USBC1_ICUSB_PWRDNZ (1 << 20)
266
267#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 (1 << 31)
268#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1 (1 << 30)
269#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 (1 << 29)
270#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3 (1 << 28)
271#define OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL (1 << 27)
272#define OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL (1 << 26)
273#define OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL (1 << 25)
274
275/* CONTROL_PROG_IO1 bits */
276#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
277
278/* CONTROL_IVA2_BOOTMOD bits */
279#define OMAP3_IVA2_BOOTMOD_SHIFT 0
280#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)
281#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0)
282
283/* CONTROL_PADCONF_X bits */
284#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15)
285#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
286
287#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860)
288#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910)
289#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
290
291/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
292#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0
293#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1
294#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2
295#define AM35XX_HECC_VBUSP_CLK_SHIFT 3
296#define AM35XX_USBOTG_FCLK_SHIFT 8
297#define AM35XX_CPGMAC_FCLK_SHIFT 9
298#define AM35XX_VPFE_FCLK_SHIFT 10
299
300/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/
301#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
302#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1)
303#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2)
304#define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3)
305#define AM35XX_USBOTGSS_INT_CLR BIT(4)
306#define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5)
307#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6)
308#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7)
309
310/*AM35XX CONTROL_IP_SW_RESET bits*/
311#define AM35XX_USBOTGSS_SW_RST BIT(0)
312#define AM35XX_CPGMACSS_SW_RST BIT(1)
313#define AM35XX_VPFE_VBUSP_SW_RST BIT(2)
314#define AM35XX_HECC_SW_RST BIT(3)
315#define AM35XX_VPFE_PCLK_SW_RST BIT(4)
316
317/*
318 * CONTROL OMAP STATUS register to identify OMAP3 features
319 */
320#define OMAP3_CONTROL_OMAP_STATUS 0x044c
321
322#define OMAP3_SGX_SHIFT 13
323#define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT)
324#define FEAT_SGX_FULL 0
325#define FEAT_SGX_HALF 1
326#define FEAT_SGX_NONE 2
327
328#define OMAP3_IVA_SHIFT 12
329#define OMAP3_IVA_MASK (1 << OMAP3_SGX_SHIFT)
330#define FEAT_IVA 0
331#define FEAT_IVA_NONE 1
332
333#define OMAP3_L2CACHE_SHIFT 10
334#define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT)
335#define FEAT_L2CACHE_NONE 0
336#define FEAT_L2CACHE_64KB 1
337#define FEAT_L2CACHE_128KB 2
338#define FEAT_L2CACHE_256KB 3
339
340#define OMAP3_ISP_SHIFT 5
341#define OMAP3_ISP_MASK (1<< OMAP3_ISP_SHIFT)
342#define FEAT_ISP 0
343#define FEAT_ISP_NONE 1
344
345#define OMAP3_NEON_SHIFT 4
346#define OMAP3_NEON_MASK (1<< OMAP3_NEON_SHIFT)
347#define FEAT_NEON 0
348#define FEAT_NEON_NONE 1
349
350
351#ifndef __ASSEMBLY__
352#ifdef CONFIG_ARCH_OMAP2PLUS
353extern void __iomem *omap_ctrl_base_get(void);
354extern u8 omap_ctrl_readb(u16 offset);
355extern u16 omap_ctrl_readw(u16 offset);
356extern u32 omap_ctrl_readl(u16 offset);
357extern void omap_ctrl_writeb(u8 val, u16 offset);
358extern void omap_ctrl_writew(u16 val, u16 offset);
359extern void omap_ctrl_writel(u32 val, u16 offset);
360
361extern void omap3_save_scratchpad_contents(void);
362extern void omap3_clear_scratchpad_contents(void);
363extern u32 *get_restore_pointer(void);
364extern u32 *get_es3_restore_pointer(void);
365extern u32 omap3_arm_context[128];
366extern void omap3_control_save_context(void);
367extern void omap3_control_restore_context(void);
368
369#else
370#define omap_ctrl_base_get() 0
371#define omap_ctrl_readb(x) 0
372#define omap_ctrl_readw(x) 0
373#define omap_ctrl_readl(x) 0
374#define omap_ctrl_writeb(x, y) WARN_ON(1)
375#define omap_ctrl_writew(x, y) WARN_ON(1)
376#define omap_ctrl_writel(x, y) WARN_ON(1)
377#endif
378#endif /* __ASSEMBLY__ */
379
380#endif /* __ASM_ARCH_CONTROL_H */
381
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 2e2ae530fced..3fd8b4055727 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -68,10 +68,9 @@ unsigned int omap_rev(void);
68#define OMAP_REVBITS_00 0x00 68#define OMAP_REVBITS_00 0x00
69#define OMAP_REVBITS_01 0x01 69#define OMAP_REVBITS_01 0x01
70#define OMAP_REVBITS_02 0x02 70#define OMAP_REVBITS_02 0x02
71#define OMAP_REVBITS_10 0x10 71#define OMAP_REVBITS_03 0x03
72#define OMAP_REVBITS_20 0x20 72#define OMAP_REVBITS_04 0x04
73#define OMAP_REVBITS_30 0x30 73#define OMAP_REVBITS_05 0x05
74#define OMAP_REVBITS_40 0x40
75 74
76/* 75/*
77 * Get the CPU revision for OMAP devices 76 * Get the CPU revision for OMAP devices
@@ -363,23 +362,24 @@ IS_OMAP_TYPE(3517, 0x3517)
363 362
364/* Various silicon revisions for omap2 */ 363/* Various silicon revisions for omap2 */
365#define OMAP242X_CLASS 0x24200024 364#define OMAP242X_CLASS 0x24200024
366#define OMAP2420_REV_ES1_0 0x24200024 365#define OMAP2420_REV_ES1_0 OMAP242X_CLASS
367#define OMAP2420_REV_ES2_0 0x24201024 366#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (OMAP_REVBITS_01 << 8))
368 367
369#define OMAP243X_CLASS 0x24300024 368#define OMAP243X_CLASS 0x24300024
370#define OMAP2430_REV_ES1_0 0x24300024 369#define OMAP2430_REV_ES1_0 OMAP243X_CLASS
371 370
372#define OMAP343X_CLASS 0x34300034 371#define OMAP343X_CLASS 0x34300034
373#define OMAP3430_REV_ES1_0 0x34300034 372#define OMAP3430_REV_ES1_0 OMAP343X_CLASS
374#define OMAP3430_REV_ES2_0 0x34301034 373#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (OMAP_REVBITS_01 << 8))
375#define OMAP3430_REV_ES2_1 0x34302034 374#define OMAP3430_REV_ES2_1 (OMAP343X_CLASS | (OMAP_REVBITS_02 << 8))
376#define OMAP3430_REV_ES3_0 0x34303034 375#define OMAP3430_REV_ES3_0 (OMAP343X_CLASS | (OMAP_REVBITS_03 << 8))
377#define OMAP3430_REV_ES3_1 0x34304034 376#define OMAP3430_REV_ES3_1 (OMAP343X_CLASS | (OMAP_REVBITS_04 << 8))
378#define OMAP3430_REV_ES3_1_2 0x34305034 377#define OMAP3430_REV_ES3_1_2 (OMAP343X_CLASS | (OMAP_REVBITS_05 << 8))
379 378
380#define OMAP3630_REV_ES1_0 0x36300034 379#define OMAP363X_CLASS 0x36300034
381#define OMAP3630_REV_ES1_1 0x36300134 380#define OMAP3630_REV_ES1_0 OMAP363X_CLASS
382#define OMAP3630_REV_ES1_2 0x36300234 381#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (OMAP_REVBITS_01 << 8))
382#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (OMAP_REVBITS_02 << 8))
383 383
384#define OMAP35XX_CLASS 0x35000034 384#define OMAP35XX_CLASS 0x35000034
385#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8)) 385#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
@@ -390,7 +390,8 @@ IS_OMAP_TYPE(3517, 0x3517)
390#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8)) 390#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
391 391
392#define OMAP443X_CLASS 0x44300044 392#define OMAP443X_CLASS 0x44300044
393#define OMAP4430_REV_ES1_0 0x44300044 393#define OMAP4430_REV_ES1_0 OMAP443X_CLASS
394#define OMAP4430_REV_ES2_0 0x44301044
394 395
395/* 396/*
396 * omap_chip bits 397 * omap_chip bits
@@ -417,10 +418,12 @@ IS_OMAP_TYPE(3517, 0x3517)
417#define CHIP_IS_OMAP4430ES1 (1 << 8) 418#define CHIP_IS_OMAP4430ES1 (1 << 8)
418#define CHIP_IS_OMAP3630ES1_1 (1 << 9) 419#define CHIP_IS_OMAP3630ES1_1 (1 << 9)
419#define CHIP_IS_OMAP3630ES1_2 (1 << 10) 420#define CHIP_IS_OMAP3630ES1_2 (1 << 10)
421#define CHIP_IS_OMAP4430ES2 (1 << 11)
420 422
421#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) 423#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
422 424
423#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1) 425#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \
426 CHIP_IS_OMAP4430ES2)
424 427
425/* 428/*
426 * "GE" here represents "greater than or equal to" in terms of ES 429 * "GE" here represents "greater than or equal to" in terms of ES
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index af3a03941add..0cce4ca83aa0 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -319,6 +319,8 @@
319#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ 319#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
320#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ 320#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */
321 321
322#define OMAP36XX_DMA_UART4_TX 81 /* S_DMA_80 */
323#define OMAP36XX_DMA_UART4_RX 82 /* S_DMA_81 */
322/*----------------------------------------------------------------------------*/ 324/*----------------------------------------------------------------------------*/
323 325
324#define OMAP1_DMA_TOUT_IRQ (1 << 0) 326#define OMAP1_DMA_TOUT_IRQ (1 << 0)
@@ -335,6 +337,10 @@
335#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11) 337#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
336 338
337#define OMAP_DMA_CCR_EN (1 << 7) 339#define OMAP_DMA_CCR_EN (1 << 7)
340#define OMAP_DMA_CCR_RD_ACTIVE (1 << 9)
341#define OMAP_DMA_CCR_WR_ACTIVE (1 << 10)
342#define OMAP_DMA_CCR_SEL_SRC_DST_SYNC (1 << 24)
343#define OMAP_DMA_CCR_BUFFERING_DISABLE (1 << 25)
338 344
339#define OMAP_DMA_DATA_TYPE_S8 0x00 345#define OMAP_DMA_DATA_TYPE_S8 0x00
340#define OMAP_DMA_DATA_TYPE_S16 0x01 346#define OMAP_DMA_DATA_TYPE_S16 0x01
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 20f1054c0a80..dfa3aff9761b 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -45,6 +45,8 @@
45#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 45#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
46 46
47struct omap_dm_timer; 47struct omap_dm_timer;
48extern struct omap_dm_timer *gptimer_wakeup;
49extern struct sys_timer omap_timer;
48struct clk; 50struct clk;
49 51
50int omap_dm_timer_init(void); 52int omap_dm_timer_init(void);
diff --git a/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h b/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
new file mode 100644
index 000000000000..872de0bf1e6b
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
@@ -0,0 +1,35 @@
1/*
2 * arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
3 *
4 * Copyright (C) 2009 Li-Pro.Net
5 * Stephan Linz <linz@li-pro.net>
6 *
7 * Modified from arch/arm/plat-omap/include/plat/gpmc-smc91x.h
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __ASM_ARCH_OMAP_GPMC_SMSC911X_H__
15
16struct omap_smsc911x_platform_data {
17 int cs;
18 int gpio_irq;
19 int gpio_reset;
20 u32 flags;
21};
22
23#if defined(CONFIG_SMSC911X) || \
24 defined(CONFIG_SMSC911X_MODULE)
25
26extern void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d);
27
28#else
29
30static inline void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d)
31{
32}
33
34#endif
35#endif
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
index 87f6bf2ea4fa..36a0befd6168 100644
--- a/arch/arm/plat-omap/include/plat/i2c.h
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -18,6 +18,8 @@
18 * 02110-1301 USA 18 * 02110-1301 USA
19 * 19 *
20 */ 20 */
21#ifndef __ASM__ARCH_OMAP_I2C_H
22#define __ASM__ARCH_OMAP_I2C_H
21 23
22#include <linux/i2c.h> 24#include <linux/i2c.h>
23 25
@@ -36,3 +38,5 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
36 38
37void __init omap1_i2c_mux_pins(int bus_id); 39void __init omap1_i2c_mux_pins(int bus_id);
38void __init omap2_i2c_mux_pins(int bus_id); 40void __init omap2_i2c_mux_pins(int bus_id);
41
42#endif /* __ASM__ARCH_OMAP_I2C_H */
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index c01d9f08a198..65e20a686713 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -345,6 +345,8 @@
345#define INT_34XX_MMC3_IRQ 94 345#define INT_34XX_MMC3_IRQ 94
346#define INT_34XX_GPT12_IRQ 95 346#define INT_34XX_GPT12_IRQ 95
347 347
348#define INT_36XX_UART4_IRQ 80
349
348#define INT_35XX_HECC0_IRQ 24 350#define INT_35XX_HECC0_IRQ 24
349#define INT_35XX_HECC1_IRQ 28 351#define INT_35XX_HECC1_IRQ 28
350#define INT_35XX_EMAC_C0_RXTHRESH_IRQ 67 352#define INT_35XX_EMAC_C0_RXTHRESH_IRQ 67
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 5b20103e68eb..b87d83ccd545 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -319,6 +319,18 @@ static struct platform_device omap_mcbsp##port_nr = { \
319#define RFSREN 0x0002 319#define RFSREN 0x0002
320#define RSYNCERREN 0x0001 320#define RSYNCERREN 0x0001
321 321
322/* CLKR signal muxing options */
323#define CLKR_SRC_CLKR 0
324#define CLKR_SRC_CLKX 1
325
326/* FSR signal muxing options */
327#define FSR_SRC_FSR 0
328#define FSR_SRC_FSX 1
329
330/* McBSP functional clock sources */
331#define MCBSP_CLKS_PRCM_SRC 0
332#define MCBSP_CLKS_PAD_SRC 1
333
322/* we don't do multichannel for now */ 334/* we don't do multichannel for now */
323struct omap_mcbsp_reg_cfg { 335struct omap_mcbsp_reg_cfg {
324 u16 spcr2; 336 u16 spcr2;
@@ -405,6 +417,7 @@ struct omap_mcbsp_spi_cfg {
405struct omap_mcbsp_ops { 417struct omap_mcbsp_ops {
406 void (*request)(unsigned int); 418 void (*request)(unsigned int);
407 void (*free)(unsigned int); 419 void (*free)(unsigned int);
420 int (*set_clks_src)(u8, u8);
408}; 421};
409 422
410struct omap_mcbsp_platform_data { 423struct omap_mcbsp_platform_data {
@@ -471,6 +484,9 @@ struct omap_mcbsp {
471extern struct omap_mcbsp **mcbsp_ptr; 484extern struct omap_mcbsp **mcbsp_ptr;
472extern int omap_mcbsp_count, omap_mcbsp_cache_size; 485extern int omap_mcbsp_count, omap_mcbsp_cache_size;
473 486
487#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
488#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
489
474int omap_mcbsp_init(void); 490int omap_mcbsp_init(void);
475void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, 491void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
476 int size); 492 int size);
@@ -509,6 +525,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
509int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word); 525int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
510 526
511 527
528/* McBSP functional clock source changing function */
529extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
512/* SPI specific API */ 530/* SPI specific API */
513void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg); 531void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
514 532
@@ -517,6 +535,10 @@ int omap_mcbsp_pollread(unsigned int id, u16 * buf);
517int omap_mcbsp_pollwrite(unsigned int id, u16 buf); 535int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
518int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type); 536int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
519 537
538/* McBSP signal muxing API */
539void omap2_mcbsp1_mux_clkr_src(u8 mux);
540void omap2_mcbsp1_mux_fsr_src(u8 mux);
541
520#ifdef CONFIG_ARCH_OMAP3 542#ifdef CONFIG_ARCH_OMAP3
521/* Sidetone specific API */ 543/* Sidetone specific API */
522int omap_st_set_chgain(unsigned int id, int channel, s16 chgain); 544int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index 9b89ec601ee2..f57f36abb07e 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -71,12 +71,17 @@ struct omap_mmc_platform_data {
71 71
72 u64 dma_mask; 72 u64 dma_mask;
73 73
74 /* Register offset deviation */
75 u16 reg_offset;
76
74 struct omap_mmc_slot_data { 77 struct omap_mmc_slot_data {
75 78
76 /* 4 wire signaling is optional, and is used for SD/SDIO/HSMMC; 79 /*
77 * 8 wire signaling is also optional, and is used with HSMMC 80 * 4/8 wires and any additional host capabilities
81 * need to OR'd all capabilities (ref. linux/mmc/host.h)
78 */ 82 */
79 u8 wires; 83 u8 wires; /* Used for the MMC driver on omap1 and 2420 */
84 u32 caps; /* Used for the MMC driver on 2430 and later */
80 85
81 /* 86 /*
82 * nomux means "standard" muxing is wrong on this board, and 87 * nomux means "standard" muxing is wrong on this board, and
@@ -104,6 +109,7 @@ struct omap_mmc_platform_data {
104 109
105 /* we can put the features above into this variable */ 110 /* we can put the features above into this variable */
106#define HSMMC_HAS_PBIAS (1 << 0) 111#define HSMMC_HAS_PBIAS (1 << 0)
112#define HSMMC_HAS_UPDATED_RESET (1 << 1)
107 unsigned features; 113 unsigned features;
108 114
109 int switch_pin; /* gpio (card detect) */ 115 int switch_pin; /* gpio (card detect) */
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
new file mode 100644
index 000000000000..c8dae02f0704
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -0,0 +1,128 @@
1/*
2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Authors:
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef __OMAP_SERIAL_H__
18#define __OMAP_SERIAL_H__
19
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22
23#include <plat/mux.h>
24
25#define DRIVER_NAME "omap-hsuart"
26
27/*
28 * Use tty device name as ttyO, [O -> OMAP]
29 * in bootargs we specify as console=ttyO0 if uart1
30 * is used as console uart.
31 */
32#define OMAP_SERIAL_NAME "ttyO"
33
34#define OMAP_MDR1_DISABLE 0x07
35#define OMAP_MDR1_MODE13X 0x03
36#define OMAP_MDR1_MODE16X 0x00
37#define OMAP_MODE13X_SPEED 230400
38
39/*
40 * LCR = 0XBF: Switch to Configuration Mode B.
41 * In configuration mode b allow access
42 * to EFR,DLL,DLH.
43 * Reference OMAP TRM Chapter 17
44 * Section: 1.4.3 Mode Selection
45 */
46#define OMAP_UART_LCR_CONF_MDB 0XBF
47
48/* WER = 0x7F
49 * Enable module level wakeup in WER reg
50 */
51#define OMAP_UART_WER_MOD_WKUP 0X7F
52
53/* Enable XON/XOFF flow control on output */
54#define OMAP_UART_SW_TX 0x04
55
56/* Enable XON/XOFF flow control on input */
57#define OMAP_UART_SW_RX 0x04
58
59#define OMAP_UART_SYSC_RESET 0X07
60#define OMAP_UART_TCR_TRIG 0X0F
61#define OMAP_UART_SW_CLR 0XF0
62#define OMAP_UART_FIFO_CLR 0X06
63
64#define OMAP_UART_DMA_CH_FREE -1
65
66#define RX_TIMEOUT (3 * HZ)
67#define OMAP_MAX_HSUART_PORTS 4
68
69#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
70
71struct omap_uart_port_info {
72 bool dma_enabled; /* To specify DMA Mode */
73 unsigned int uartclk; /* UART clock rate */
74 void __iomem *membase; /* ioremap cookie or NULL */
75 resource_size_t mapbase; /* resource base */
76 unsigned long irqflags; /* request_irq flags */
77 upf_t flags; /* UPF_* flags */
78};
79
80struct uart_omap_dma {
81 u8 uart_dma_tx;
82 u8 uart_dma_rx;
83 int rx_dma_channel;
84 int tx_dma_channel;
85 dma_addr_t rx_buf_dma_phys;
86 dma_addr_t tx_buf_dma_phys;
87 unsigned int uart_base;
88 /*
89 * Buffer for rx dma.It is not required for tx because the buffer
90 * comes from port structure.
91 */
92 unsigned char *rx_buf;
93 unsigned int prev_rx_dma_pos;
94 int tx_buf_size;
95 int tx_dma_used;
96 int rx_dma_used;
97 spinlock_t tx_lock;
98 spinlock_t rx_lock;
99 /* timer to poll activity on rx dma */
100 struct timer_list rx_timer;
101 int rx_buf_size;
102 int rx_timeout;
103};
104
105struct uart_omap_port {
106 struct uart_port port;
107 struct uart_omap_dma uart_dma;
108 struct platform_device *pdev;
109
110 unsigned char ier;
111 unsigned char lcr;
112 unsigned char mcr;
113 unsigned char fcr;
114 unsigned char efr;
115
116 int use_dma;
117 /*
118 * Some bits in registers are cleared on a read, so they must
119 * be saved whenever the register is read but the bits will not
120 * be immediately processed.
121 */
122 unsigned int lsr_break_flag;
123 unsigned char msr_saved_flags;
124 char name[20];
125 unsigned long port_activity;
126};
127
128#endif /* __OMAP_SERIAL_H__ */
diff --git a/arch/arm/plat-omap/include/plat/omap24xx.h b/arch/arm/plat-omap/include/plat/omap24xx.h
index 7055672a8c68..92df9e27cc5c 100644
--- a/arch/arm/plat-omap/include/plat/omap24xx.h
+++ b/arch/arm/plat-omap/include/plat/omap24xx.h
@@ -40,7 +40,7 @@
40#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000) 40#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
41#define OMAP24XX_IVA_INTC_BASE 0x40000000 41#define OMAP24XX_IVA_INTC_BASE 0x40000000
42 42
43#define OMAP2420_CTRL_BASE L4_24XX_BASE 43#define OMAP242X_CTRL_BASE L4_24XX_BASE
44#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) 44#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
45#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000) 45#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
46#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000) 46#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 25cd9ac3b095..28e2d1a78433 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -36,6 +36,8 @@
36 36
37#include <plat/omap_hwmod.h> 37#include <plat/omap_hwmod.h>
38 38
39extern struct device omap_device_parent;
40
39/* omap_device._state values */ 41/* omap_device._state values */
40#define OMAP_DEVICE_STATE_UNKNOWN 0 42#define OMAP_DEVICE_STATE_UNKNOWN 0
41#define OMAP_DEVICE_STATE_ENABLED 1 43#define OMAP_DEVICE_STATE_ENABLED 1
@@ -62,7 +64,6 @@
62 * 64 *
63 */ 65 */
64struct omap_device { 66struct omap_device {
65 u32 magic;
66 struct platform_device pdev; 67 struct platform_device pdev;
67 struct omap_hwmod **hwmods; 68 struct omap_hwmod **hwmods;
68 struct omap_device_pm_latency *pm_lats; 69 struct omap_device_pm_latency *pm_lats;
@@ -82,7 +83,6 @@ int omap_device_shutdown(struct platform_device *pdev);
82 83
83/* Core code interface */ 84/* Core code interface */
84 85
85bool omap_device_is_valid(struct omap_device *od);
86int omap_device_count_resources(struct omap_device *od); 86int omap_device_count_resources(struct omap_device *od);
87int omap_device_fill_resources(struct omap_device *od, struct resource *res); 87int omap_device_fill_resources(struct omap_device *od, struct resource *res);
88 88
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index a4e508dfaba2..7eaa8edf3b14 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -14,19 +14,16 @@
14 * 14 *
15 * These headers and macros are used to define OMAP on-chip module 15 * These headers and macros are used to define OMAP on-chip module
16 * data and their integration with other OMAP modules and Linux. 16 * data and their integration with other OMAP modules and Linux.
17 * 17 * Copious documentation and references can also be found in the
18 * References: 18 * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this
19 * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) 19 * writing).
20 * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
21 * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
22 * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
23 * - Open Core Protocol Specification 2.2
24 * 20 *
25 * To do: 21 * To do:
26 * - add interconnect error log structures 22 * - add interconnect error log structures
27 * - add pinmuxing 23 * - add pinmuxing
28 * - init_conn_id_bit (CONNID_BIT_VECTOR) 24 * - init_conn_id_bit (CONNID_BIT_VECTOR)
29 * - implement default hwmod SMS/SDRC flags? 25 * - implement default hwmod SMS/SDRC flags?
26 * - remove unused fields
30 * 27 *
31 */ 28 */
32#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H 29#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
@@ -35,6 +32,7 @@
35#include <linux/kernel.h> 32#include <linux/kernel.h>
36#include <linux/list.h> 33#include <linux/list.h>
37#include <linux/ioport.h> 34#include <linux/ioport.h>
35#include <linux/mutex.h>
38#include <plat/cpu.h> 36#include <plat/cpu.h>
39 37
40struct omap_device; 38struct omap_device;
@@ -96,7 +94,7 @@ struct omap_hwmod_irq_info {
96/** 94/**
97 * struct omap_hwmod_dma_info - DMA channels used by the hwmod 95 * struct omap_hwmod_dma_info - DMA channels used by the hwmod
98 * @name: name of the DMA channel (module local name) 96 * @name: name of the DMA channel (module local name)
99 * @dma_ch: DMA channel ID 97 * @dma_req: DMA request ID
100 * 98 *
101 * @name should be something short, e.g., "tx" or "rx". It is for use 99 * @name should be something short, e.g., "tx" or "rx". It is for use
102 * by platform_get_resource_byname(). It is defined locally to the 100 * by platform_get_resource_byname(). It is defined locally to the
@@ -104,7 +102,20 @@ struct omap_hwmod_irq_info {
104 */ 102 */
105struct omap_hwmod_dma_info { 103struct omap_hwmod_dma_info {
106 const char *name; 104 const char *name;
107 u16 dma_ch; 105 u16 dma_req;
106};
107
108/**
109 * struct omap_hwmod_rst_info - IPs reset lines use by hwmod
110 * @name: name of the reset line (module local name)
111 * @rst_shift: Offset of the reset bit
112 *
113 * @name should be something short, e.g., "cpu0" or "rst". It is defined
114 * locally to the hwmod.
115 */
116struct omap_hwmod_rst_info {
117 const char *name;
118 u8 rst_shift;
108}; 119};
109 120
110/** 121/**
@@ -237,8 +248,9 @@ struct omap_hwmod_ocp_if {
237#define SYSC_HAS_CLOCKACTIVITY (1 << 4) 248#define SYSC_HAS_CLOCKACTIVITY (1 << 4)
238#define SYSC_HAS_SIDLEMODE (1 << 5) 249#define SYSC_HAS_SIDLEMODE (1 << 5)
239#define SYSC_HAS_MIDLEMODE (1 << 6) 250#define SYSC_HAS_MIDLEMODE (1 << 6)
240#define SYSS_MISSING (1 << 7) 251#define SYSS_HAS_RESET_STATUS (1 << 7)
241#define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */ 252#define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */
253#define SYSC_HAS_RESET_STATUS (1 << 9)
242 254
243/* omap_hwmod_sysconfig.clockact flags */ 255/* omap_hwmod_sysconfig.clockact flags */
244#define CLOCKACT_TEST_BOTH 0x0 256#define CLOCKACT_TEST_BOTH 0x0
@@ -327,10 +339,12 @@ struct omap_hwmod_omap2_prcm {
327/** 339/**
328 * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data 340 * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
329 * @clkctrl_reg: PRCM address of the clock control register 341 * @clkctrl_reg: PRCM address of the clock control register
342 * @rstctrl_reg: adress of the XXX_RSTCTRL register located in the PRM
330 * @submodule_wkdep_bit: bit shift of the WKDEP range 343 * @submodule_wkdep_bit: bit shift of the WKDEP range
331 */ 344 */
332struct omap_hwmod_omap4_prcm { 345struct omap_hwmod_omap4_prcm {
333 void __iomem *clkctrl_reg; 346 void __iomem *clkctrl_reg;
347 void __iomem *rstctrl_reg;
334 u8 submodule_wkdep_bit; 348 u8 submodule_wkdep_bit;
335}; 349};
336 350
@@ -352,6 +366,11 @@ struct omap_hwmod_omap4_prcm {
352 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup 366 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
353 * HWMOD_NO_IDLEST : this module does not have idle status - this is the case 367 * HWMOD_NO_IDLEST : this module does not have idle status - this is the case
354 * only for few initiator modules on OMAP2 & 3. 368 * only for few initiator modules on OMAP2 & 3.
369 * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset.
370 * This is needed for devices like DSS that require optional clocks enabled
371 * in order to complete the reset. Optional clocks will be disabled
372 * again after the reset.
373 * HWMOD_16BIT_REG: Module has 16bit registers
355 */ 374 */
356#define HWMOD_SWSUP_SIDLE (1 << 0) 375#define HWMOD_SWSUP_SIDLE (1 << 0)
357#define HWMOD_SWSUP_MSTANDBY (1 << 1) 376#define HWMOD_SWSUP_MSTANDBY (1 << 1)
@@ -360,6 +379,8 @@ struct omap_hwmod_omap4_prcm {
360#define HWMOD_NO_OCP_AUTOIDLE (1 << 4) 379#define HWMOD_NO_OCP_AUTOIDLE (1 << 4)
361#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5) 380#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5)
362#define HWMOD_NO_IDLEST (1 << 6) 381#define HWMOD_NO_IDLEST (1 << 6)
382#define HWMOD_CONTROL_OPT_CLKS_IN_RESET (1 << 7)
383#define HWMOD_16BIT_REG (1 << 8)
363 384
364/* 385/*
365 * omap_hwmod._int_flags definitions 386 * omap_hwmod._int_flags definitions
@@ -410,7 +431,7 @@ struct omap_hwmod_class {
410 * @class: struct omap_hwmod_class * to the class of this hwmod 431 * @class: struct omap_hwmod_class * to the class of this hwmod
411 * @od: struct omap_device currently associated with this hwmod (internal use) 432 * @od: struct omap_device currently associated with this hwmod (internal use)
412 * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt) 433 * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
413 * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt) 434 * @sdma_reqs: ptr to an array of System DMA request IDs (see sdma_reqs_cnt)
414 * @prcm: PRCM data pertaining to this hwmod 435 * @prcm: PRCM data pertaining to this hwmod
415 * @main_clk: main clock: OMAP clock name 436 * @main_clk: main clock: OMAP clock name
416 * @_clk: pointer to the main struct clk (filled in at runtime) 437 * @_clk: pointer to the main struct clk (filled in at runtime)
@@ -424,7 +445,7 @@ struct omap_hwmod_class {
424 * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6) 445 * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6)
425 * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift 446 * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift
426 * @mpu_irqs_cnt: number of @mpu_irqs 447 * @mpu_irqs_cnt: number of @mpu_irqs
427 * @sdma_chs_cnt: number of @sdma_chs 448 * @sdma_reqs_cnt: number of @sdma_reqs
428 * @opt_clks_cnt: number of @opt_clks 449 * @opt_clks_cnt: number of @opt_clks
429 * @master_cnt: number of @master entries 450 * @master_cnt: number of @master entries
430 * @slaves_cnt: number of @slave entries 451 * @slaves_cnt: number of @slave entries
@@ -433,6 +454,7 @@ struct omap_hwmod_class {
433 * @_state: internal-use hwmod state 454 * @_state: internal-use hwmod state
434 * @flags: hwmod flags (documented below) 455 * @flags: hwmod flags (documented below)
435 * @omap_chip: OMAP chips this hwmod is present on 456 * @omap_chip: OMAP chips this hwmod is present on
457 * @_mutex: mutex serializing operations on this hwmod
436 * @node: list node for hwmod list (internal use) 458 * @node: list node for hwmod list (internal use)
437 * 459 *
438 * @main_clk refers to this module's "main clock," which for our 460 * @main_clk refers to this module's "main clock," which for our
@@ -448,7 +470,8 @@ struct omap_hwmod {
448 struct omap_hwmod_class *class; 470 struct omap_hwmod_class *class;
449 struct omap_device *od; 471 struct omap_device *od;
450 struct omap_hwmod_irq_info *mpu_irqs; 472 struct omap_hwmod_irq_info *mpu_irqs;
451 struct omap_hwmod_dma_info *sdma_chs; 473 struct omap_hwmod_dma_info *sdma_reqs;
474 struct omap_hwmod_rst_info *rst_lines;
452 union { 475 union {
453 struct omap_hwmod_omap2_prcm omap2; 476 struct omap_hwmod_omap2_prcm omap2;
454 struct omap_hwmod_omap4_prcm omap4; 477 struct omap_hwmod_omap4_prcm omap4;
@@ -461,6 +484,7 @@ struct omap_hwmod {
461 void *dev_attr; 484 void *dev_attr;
462 u32 _sysc_cache; 485 u32 _sysc_cache;
463 void __iomem *_mpu_rt_va; 486 void __iomem *_mpu_rt_va;
487 struct mutex _mutex;
464 struct list_head node; 488 struct list_head node;
465 u16 flags; 489 u16 flags;
466 u8 _mpu_port_index; 490 u8 _mpu_port_index;
@@ -468,7 +492,8 @@ struct omap_hwmod {
468 u8 msuspendmux_shift; 492 u8 msuspendmux_shift;
469 u8 response_lat; 493 u8 response_lat;
470 u8 mpu_irqs_cnt; 494 u8 mpu_irqs_cnt;
471 u8 sdma_chs_cnt; 495 u8 sdma_reqs_cnt;
496 u8 rst_lines_cnt;
472 u8 opt_clks_cnt; 497 u8 opt_clks_cnt;
473 u8 masters_cnt; 498 u8 masters_cnt;
474 u8 slaves_cnt; 499 u8 slaves_cnt;
@@ -492,6 +517,10 @@ int omap_hwmod_idle(struct omap_hwmod *oh);
492int _omap_hwmod_idle(struct omap_hwmod *oh); 517int _omap_hwmod_idle(struct omap_hwmod *oh);
493int omap_hwmod_shutdown(struct omap_hwmod *oh); 518int omap_hwmod_shutdown(struct omap_hwmod *oh);
494 519
520int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name);
521int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name);
522int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name);
523
495int omap_hwmod_enable_clocks(struct omap_hwmod *oh); 524int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
496int omap_hwmod_disable_clocks(struct omap_hwmod *oh); 525int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
497 526
@@ -500,8 +529,8 @@ int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode);
500int omap_hwmod_reset(struct omap_hwmod *oh); 529int omap_hwmod_reset(struct omap_hwmod *oh);
501void omap_hwmod_ocp_barrier(struct omap_hwmod *oh); 530void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
502 531
503void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs); 532void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
504u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs); 533u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
505 534
506int omap_hwmod_count_resources(struct omap_hwmod *oh); 535int omap_hwmod_count_resources(struct omap_hwmod *oh);
507int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); 536int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
@@ -534,5 +563,6 @@ int omap_hwmod_for_each_by_class(const char *classname,
534extern int omap2420_hwmod_init(void); 563extern int omap2420_hwmod_init(void);
535extern int omap2430_hwmod_init(void); 564extern int omap2430_hwmod_init(void);
536extern int omap3xxx_hwmod_init(void); 565extern int omap3xxx_hwmod_init(void);
566extern int omap44xx_hwmod_init(void);
537 567
538#endif 568#endif
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index fb6ec74fe39e..9ca420dcd2f8 100644
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -32,6 +32,7 @@
32 32
33/* Powerdomain allowable state bitfields */ 33/* Powerdomain allowable state bitfields */
34#define PWRSTS_ON (1 << PWRDM_POWER_ON) 34#define PWRSTS_ON (1 << PWRDM_POWER_ON)
35#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
35#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ 36#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
36 (1 << PWRDM_POWER_ON)) 37 (1 << PWRDM_POWER_ON))
37 38
@@ -161,5 +162,6 @@ int pwrdm_state_switch(struct powerdomain *pwrdm);
161int pwrdm_clkdm_state_switch(struct clockdomain *clkdm); 162int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
162int pwrdm_pre_transition(void); 163int pwrdm_pre_transition(void);
163int pwrdm_post_transition(void); 164int pwrdm_post_transition(void);
165int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
164 166
165#endif 167#endif
diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h
index 9fbd91419cd1..ab77442e42ab 100644
--- a/arch/arm/plat-omap/include/plat/prcm.h
+++ b/arch/arm/plat-omap/include/plat/prcm.h
@@ -38,6 +38,8 @@ u32 prm_read_mod_reg(s16 module, u16 idx);
38void prm_write_mod_reg(u32 val, s16 module, u16 idx); 38void prm_write_mod_reg(u32 val, s16 module, u16 idx);
39u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); 39u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
40u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); 40u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
41u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask);
42u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg);
41u32 cm_read_mod_reg(s16 module, u16 idx); 43u32 cm_read_mod_reg(s16 module, u16 idx);
42void cm_write_mod_reg(u32 val, s16 module, u16 idx); 44void cm_write_mod_reg(u32 val, s16 module, u16 idx);
43u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); 45u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
index 7b76f50564ba..efd87c8dda69 100644
--- a/arch/arm/plat-omap/include/plat/sdrc.h
+++ b/arch/arm/plat-omap/include/plat/sdrc.h
@@ -147,6 +147,7 @@ struct memory_timings {
147}; 147};
148 148
149extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode); 149extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
150struct omap_sdrc_params *rx51_get_sdram_timings(void);
150 151
151u32 omap2xxx_sdrc_dll_is_unlocked(void); 152u32 omap2xxx_sdrc_dll_is_unlocked(void);
152u32 omap2xxx_sdrc_reprogram(u32 level, u32 force); 153u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 16a1b458d53c..5905100b29a1 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -11,7 +11,6 @@
11#ifndef __ARCH_ARM_OMAP_SRAM_H 11#ifndef __ARCH_ARM_OMAP_SRAM_H
12#define __ARCH_ARM_OMAP_SRAM_H 12#define __ARCH_ARM_OMAP_SRAM_H
13 13
14extern int __init omap_sram_init(void);
15extern void * omap_sram_push(void * start, unsigned long size); 14extern void * omap_sram_push(void * start, unsigned long size);
16extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); 15extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
17 16
diff --git a/arch/arm/plat-omap/include/plat/timer-gp.h b/arch/arm/plat-omap/include/plat/timer-gp.h
deleted file mode 100644
index c88d346b59d9..000000000000
--- a/arch/arm/plat-omap/include/plat/timer-gp.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * OMAP2/3 GPTIMER support.headers
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
12#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
13
14int __init omap2_gp_clockevent_set_gptimer(u8 id);
15
16#endif
17
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index ddf723be48dc..9036e374e0ac 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -139,10 +139,14 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
139 DEBUG_LL_OMAP2(1, omap3evm); 139 DEBUG_LL_OMAP2(1, omap3evm);
140 DEBUG_LL_OMAP3(1, omap_3430sdp); 140 DEBUG_LL_OMAP3(1, omap_3430sdp);
141 DEBUG_LL_OMAP3(1, omap_3630sdp); 141 DEBUG_LL_OMAP3(1, omap_3630sdp);
142 DEBUG_LL_OMAP3(1, omap3530_lv_som);
143 DEBUG_LL_OMAP3(1, omap3_torpedo);
142 144
143 /* omap3 based boards using UART3 */ 145 /* omap3 based boards using UART3 */
144 DEBUG_LL_OMAP3(3, cm_t35); 146 DEBUG_LL_OMAP3(3, cm_t35);
147 DEBUG_LL_OMAP3(3, cm_t3517);
145 DEBUG_LL_OMAP3(3, igep0020); 148 DEBUG_LL_OMAP3(3, igep0020);
149 DEBUG_LL_OMAP3(3, igep0030);
146 DEBUG_LL_OMAP3(3, nokia_rx51); 150 DEBUG_LL_OMAP3(3, nokia_rx51);
147 DEBUG_LL_OMAP3(3, omap3517evm); 151 DEBUG_LL_OMAP3(3, omap3517evm);
148 DEBUG_LL_OMAP3(3, omap3_beagle); 152 DEBUG_LL_OMAP3(3, omap3_beagle);
@@ -153,6 +157,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
153 157
154 /* omap4 based boards using UART3 */ 158 /* omap4 based boards using UART3 */
155 DEBUG_LL_OMAP4(3, omap_4430sdp); 159 DEBUG_LL_OMAP4(3, omap_4430sdp);
160 DEBUG_LL_OMAP4(3, omap4_panda);
156 161
157 /* zoom2/3 external uart */ 162 /* zoom2/3 external uart */
158 DEBUG_LL_ZOOM(omap_zoom2); 163 DEBUG_LL_ZOOM(omap_zoom2);
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 9feddacfe850..59c7fe731f28 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -105,7 +105,7 @@ static inline void omap1_usb_init(struct omap_usb_config *pdata)
105#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE) 105#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
106void omap2_usbfs_init(struct omap_usb_config *pdata); 106void omap2_usbfs_init(struct omap_usb_config *pdata);
107#else 107#else
108static inline omap2_usbfs_init(struct omap_usb_config *pdata) 108static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
109{ 109{
110} 110}
111#endif 111#endif
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 0c8612fd8312..eac4b978e9fd 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -33,7 +33,7 @@
33struct omap_mcbsp **mcbsp_ptr; 33struct omap_mcbsp **mcbsp_ptr;
34int omap_mcbsp_count, omap_mcbsp_cache_size; 34int omap_mcbsp_count, omap_mcbsp_cache_size;
35 35
36void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) 36static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
37{ 37{
38 if (cpu_class_is_omap1()) { 38 if (cpu_class_is_omap1()) {
39 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val; 39 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
@@ -47,7 +47,7 @@ void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
47 } 47 }
48} 48}
49 49
50int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache) 50static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
51{ 51{
52 if (cpu_class_is_omap1()) { 52 if (cpu_class_is_omap1()) {
53 return !from_cache ? __raw_readw(mcbsp->io_base + reg) : 53 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
@@ -62,12 +62,12 @@ int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
62} 62}
63 63
64#ifdef CONFIG_ARCH_OMAP3 64#ifdef CONFIG_ARCH_OMAP3
65void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) 65static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
66{ 66{
67 __raw_writel(val, mcbsp->st_data->io_base_st + reg); 67 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
68} 68}
69 69
70int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg) 70static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
71{ 71{
72 return __raw_readl(mcbsp->st_data->io_base_st + reg); 72 return __raw_readl(mcbsp->st_data->io_base_st + reg);
73} 73}
@@ -80,9 +80,6 @@ int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
80#define MCBSP_READ_CACHE(mcbsp, reg) \ 80#define MCBSP_READ_CACHE(mcbsp, reg) \
81 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1) 81 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
82 82
83#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
84#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
85
86#define MCBSP_ST_READ(mcbsp, reg) \ 83#define MCBSP_ST_READ(mcbsp, reg) \
87 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg) 84 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
88#define MCBSP_ST_WRITE(mcbsp, reg, val) \ 85#define MCBSP_ST_WRITE(mcbsp, reg, val) \
@@ -878,7 +875,7 @@ EXPORT_SYMBOL(omap_mcbsp_free);
878void omap_mcbsp_start(unsigned int id, int tx, int rx) 875void omap_mcbsp_start(unsigned int id, int tx, int rx)
879{ 876{
880 struct omap_mcbsp *mcbsp; 877 struct omap_mcbsp *mcbsp;
881 int idle; 878 int enable_srg = 0;
882 u16 w; 879 u16 w;
883 880
884 if (!omap_mcbsp_check_valid_id(id)) { 881 if (!omap_mcbsp_check_valid_id(id)) {
@@ -893,10 +890,13 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
893 mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7; 890 mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
894 mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7; 891 mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
895 892
896 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | 893 /* Only enable SRG, if McBSP is master */
897 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); 894 w = MCBSP_READ_CACHE(mcbsp, PCR0);
895 if (w & (FSXM | FSRM | CLKXM | CLKRM))
896 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
897 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
898 898
899 if (idle) { 899 if (enable_srg) {
900 /* Start the sample generator */ 900 /* Start the sample generator */
901 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 901 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
902 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6)); 902 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
@@ -919,7 +919,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
919 */ 919 */
920 udelay(500); 920 udelay(500);
921 921
922 if (idle) { 922 if (enable_srg) {
923 /* Start frame sync */ 923 /* Start frame sync */
924 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 924 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
925 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); 925 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
@@ -1645,7 +1645,7 @@ static const struct attribute_group sidetone_attr_group = {
1645 .attrs = (struct attribute **)sidetone_attrs, 1645 .attrs = (struct attribute **)sidetone_attrs,
1646}; 1646};
1647 1647
1648int __devinit omap_st_add(struct omap_mcbsp *mcbsp) 1648static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1649{ 1649{
1650 struct omap_mcbsp_platform_data *pdata = mcbsp->pdata; 1650 struct omap_mcbsp_platform_data *pdata = mcbsp->pdata;
1651 struct omap_mcbsp_st_data *st_data; 1651 struct omap_mcbsp_st_data *st_data;
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index d2b160942ccc..abe933cd8f09 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -82,6 +82,7 @@
82#include <linux/slab.h> 82#include <linux/slab.h>
83#include <linux/err.h> 83#include <linux/err.h>
84#include <linux/io.h> 84#include <linux/io.h>
85#include <linux/clk.h>
85 86
86#include <plat/omap_device.h> 87#include <plat/omap_device.h>
87#include <plat/omap_hwmod.h> 88#include <plat/omap_hwmod.h>
@@ -90,12 +91,6 @@
90#define USE_WAKEUP_LAT 0 91#define USE_WAKEUP_LAT 0
91#define IGNORE_WAKEUP_LAT 1 92#define IGNORE_WAKEUP_LAT 1
92 93
93/*
94 * OMAP_DEVICE_MAGIC: used to determine whether a struct omap_device
95 * obtained via container_of() is in fact a struct omap_device
96 */
97#define OMAP_DEVICE_MAGIC 0xf00dcafe
98
99/* Private functions */ 94/* Private functions */
100 95
101/** 96/**
@@ -243,6 +238,44 @@ static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
243 return container_of(pdev, struct omap_device, pdev); 238 return container_of(pdev, struct omap_device, pdev);
244} 239}
245 240
241/**
242 * _add_optional_clock_alias - Add clock alias for hwmod optional clocks
243 * @od: struct omap_device *od
244 *
245 * For every optional clock present per hwmod per omap_device, this function
246 * adds an entry in the clocks list of the form <dev-id=dev_name, con-id=role>
247 * if an entry is already present in it with the form <dev-id=NULL, con-id=role>
248 *
249 * The function is called from inside omap_device_build_ss(), after
250 * omap_device_register.
251 *
252 * This allows drivers to get a pointer to its optional clocks based on its role
253 * by calling clk_get(<dev*>, <role>).
254 *
255 * No return value.
256 */
257static void _add_optional_clock_alias(struct omap_device *od,
258 struct omap_hwmod *oh)
259{
260 int i;
261
262 for (i = 0; i < oh->opt_clks_cnt; i++) {
263 struct omap_hwmod_opt_clk *oc;
264 int r;
265
266 oc = &oh->opt_clks[i];
267
268 if (!oc->_clk)
269 continue;
270
271 r = clk_add_alias(oc->role, dev_name(&od->pdev.dev),
272 (char *)oc->clk, &od->pdev.dev);
273 if (r)
274 pr_err("omap_device: %s: clk_add_alias for %s failed\n",
275 dev_name(&od->pdev.dev), oc->role);
276 }
277}
278
246 279
247/* Public functions for use by core code */ 280/* Public functions for use by core code */
248 281
@@ -257,12 +290,11 @@ static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
257 */ 290 */
258int omap_device_count_resources(struct omap_device *od) 291int omap_device_count_resources(struct omap_device *od)
259{ 292{
260 struct omap_hwmod *oh;
261 int c = 0; 293 int c = 0;
262 int i; 294 int i;
263 295
264 for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) 296 for (i = 0; i < od->hwmods_cnt; i++)
265 c += omap_hwmod_count_resources(oh); 297 c += omap_hwmod_count_resources(od->hwmods[i]);
266 298
267 pr_debug("omap_device: %s: counted %d total resources across %d " 299 pr_debug("omap_device: %s: counted %d total resources across %d "
268 "hwmods\n", od->pdev.name, c, od->hwmods_cnt); 300 "hwmods\n", od->pdev.name, c, od->hwmods_cnt);
@@ -289,12 +321,11 @@ int omap_device_count_resources(struct omap_device *od)
289 */ 321 */
290int omap_device_fill_resources(struct omap_device *od, struct resource *res) 322int omap_device_fill_resources(struct omap_device *od, struct resource *res)
291{ 323{
292 struct omap_hwmod *oh;
293 int c = 0; 324 int c = 0;
294 int i, r; 325 int i, r;
295 326
296 for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) { 327 for (i = 0; i < od->hwmods_cnt; i++) {
297 r = omap_hwmod_fill_resources(oh, res); 328 r = omap_hwmod_fill_resources(od->hwmods[i], res);
298 res += r; 329 res += r;
299 c += r; 330 c += r;
300 } 331 }
@@ -414,15 +445,15 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
414 od->pm_lats = pm_lats; 445 od->pm_lats = pm_lats;
415 od->pm_lats_cnt = pm_lats_cnt; 446 od->pm_lats_cnt = pm_lats_cnt;
416 447
417 od->magic = OMAP_DEVICE_MAGIC;
418
419 if (is_early_device) 448 if (is_early_device)
420 ret = omap_early_device_register(od); 449 ret = omap_early_device_register(od);
421 else 450 else
422 ret = omap_device_register(od); 451 ret = omap_device_register(od);
423 452
424 for (i = 0; i < oh_cnt; i++) 453 for (i = 0; i < oh_cnt; i++) {
425 hwmods[i]->od = od; 454 hwmods[i]->od = od;
455 _add_optional_clock_alias(od, hwmods[i]);
456 }
426 457
427 if (ret) 458 if (ret)
428 goto odbs_exit4; 459 goto odbs_exit4;
@@ -473,6 +504,7 @@ int omap_device_register(struct omap_device *od)
473{ 504{
474 pr_debug("omap_device: %s: registering\n", od->pdev.name); 505 pr_debug("omap_device: %s: registering\n", od->pdev.name);
475 506
507 od->pdev.dev.parent = &omap_device_parent;
476 return platform_device_register(&od->pdev); 508 return platform_device_register(&od->pdev);
477} 509}
478 510
@@ -566,7 +598,6 @@ int omap_device_shutdown(struct platform_device *pdev)
566{ 598{
567 int ret, i; 599 int ret, i;
568 struct omap_device *od; 600 struct omap_device *od;
569 struct omap_hwmod *oh;
570 601
571 od = _find_by_pdev(pdev); 602 od = _find_by_pdev(pdev);
572 603
@@ -579,8 +610,8 @@ int omap_device_shutdown(struct platform_device *pdev)
579 610
580 ret = _omap_device_deactivate(od, IGNORE_WAKEUP_LAT); 611 ret = _omap_device_deactivate(od, IGNORE_WAKEUP_LAT);
581 612
582 for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) 613 for (i = 0; i < od->hwmods_cnt; i++)
583 omap_hwmod_shutdown(oh); 614 omap_hwmod_shutdown(od->hwmods[i]);
584 615
585 od->_state = OMAP_DEVICE_STATE_SHUTDOWN; 616 od->_state = OMAP_DEVICE_STATE_SHUTDOWN;
586 617
@@ -627,18 +658,6 @@ int omap_device_align_pm_lat(struct platform_device *pdev,
627} 658}
628 659
629/** 660/**
630 * omap_device_is_valid - Check if pointer is a valid omap_device
631 * @od: struct omap_device *
632 *
633 * Return whether struct omap_device pointer @od points to a valid
634 * omap_device.
635 */
636bool omap_device_is_valid(struct omap_device *od)
637{
638 return (od && od->magic == OMAP_DEVICE_MAGIC);
639}
640
641/**
642 * omap_device_get_pwrdm - return the powerdomain * associated with @od 661 * omap_device_get_pwrdm - return the powerdomain * associated with @od
643 * @od: struct omap_device * 662 * @od: struct omap_device *
644 * 663 *
@@ -692,11 +711,10 @@ void __iomem *omap_device_get_rt_va(struct omap_device *od)
692 */ 711 */
693int omap_device_enable_hwmods(struct omap_device *od) 712int omap_device_enable_hwmods(struct omap_device *od)
694{ 713{
695 struct omap_hwmod *oh;
696 int i; 714 int i;
697 715
698 for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) 716 for (i = 0; i < od->hwmods_cnt; i++)
699 omap_hwmod_enable(oh); 717 omap_hwmod_enable(od->hwmods[i]);
700 718
701 /* XXX pass along return value here? */ 719 /* XXX pass along return value here? */
702 return 0; 720 return 0;
@@ -710,11 +728,10 @@ int omap_device_enable_hwmods(struct omap_device *od)
710 */ 728 */
711int omap_device_idle_hwmods(struct omap_device *od) 729int omap_device_idle_hwmods(struct omap_device *od)
712{ 730{
713 struct omap_hwmod *oh;
714 int i; 731 int i;
715 732
716 for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) 733 for (i = 0; i < od->hwmods_cnt; i++)
717 omap_hwmod_idle(oh); 734 omap_hwmod_idle(od->hwmods[i]);
718 735
719 /* XXX pass along return value here? */ 736 /* XXX pass along return value here? */
720 return 0; 737 return 0;
@@ -729,11 +746,10 @@ int omap_device_idle_hwmods(struct omap_device *od)
729 */ 746 */
730int omap_device_disable_clocks(struct omap_device *od) 747int omap_device_disable_clocks(struct omap_device *od)
731{ 748{
732 struct omap_hwmod *oh;
733 int i; 749 int i;
734 750
735 for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) 751 for (i = 0; i < od->hwmods_cnt; i++)
736 omap_hwmod_disable_clocks(oh); 752 omap_hwmod_disable_clocks(od->hwmods[i]);
737 753
738 /* XXX pass along return value here? */ 754 /* XXX pass along return value here? */
739 return 0; 755 return 0;
@@ -748,12 +764,22 @@ int omap_device_disable_clocks(struct omap_device *od)
748 */ 764 */
749int omap_device_enable_clocks(struct omap_device *od) 765int omap_device_enable_clocks(struct omap_device *od)
750{ 766{
751 struct omap_hwmod *oh;
752 int i; 767 int i;
753 768
754 for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) 769 for (i = 0; i < od->hwmods_cnt; i++)
755 omap_hwmod_enable_clocks(oh); 770 omap_hwmod_enable_clocks(od->hwmods[i]);
756 771
757 /* XXX pass along return value here? */ 772 /* XXX pass along return value here? */
758 return 0; 773 return 0;
759} 774}
775
776struct device omap_device_parent = {
777 .init_name = "omap",
778 .parent = &platform_bus,
779};
780
781static int __init omap_device_init(void)
782{
783 return device_register(&omap_device_parent);
784}
785core_initcall(omap_device_init);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 10b3b4c63372..e2c8eebe6b3a 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -19,6 +19,7 @@
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/omapfb.h>
22 23
23#include <asm/tlb.h> 24#include <asm/tlb.h>
24#include <asm/cacheflush.h> 25#include <asm/cacheflush.h>
@@ -30,8 +31,8 @@
30#include <plat/cpu.h> 31#include <plat/cpu.h>
31#include <plat/vram.h> 32#include <plat/vram.h>
32 33
33#include <plat/control.h> 34#include "sram.h"
34 35#include "fb.h"
35#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 36#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
36# include "../mach-omap2/prm.h" 37# include "../mach-omap2/prm.h"
37# include "../mach-omap2/cm.h" 38# include "../mach-omap2/cm.h"
@@ -53,7 +54,7 @@
53#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) 54#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
54#define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000) 55#define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000)
55 56
56#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 57#if defined(CONFIG_ARCH_OMAP2PLUS)
57#define SRAM_BOOTLOADER_SZ 0x00 58#define SRAM_BOOTLOADER_SZ 0x00
58#else 59#else
59#define SRAM_BOOTLOADER_SZ 0x80 60#define SRAM_BOOTLOADER_SZ 0x80
@@ -68,7 +69,6 @@
68#define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858) 69#define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
69#define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880) 70#define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880)
70#define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048) 71#define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048)
71#define OMAP34XX_VA_CONTROL_STAT OMAP2_L4_IO_ADDRESS(0x480022F0)
72 72
73#define GP_DEVICE 0x300 73#define GP_DEVICE 0x300
74 74
@@ -79,12 +79,6 @@ static unsigned long omap_sram_base;
79static unsigned long omap_sram_size; 79static unsigned long omap_sram_size;
80static unsigned long omap_sram_ceil; 80static unsigned long omap_sram_ceil;
81 81
82extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
83 unsigned long sram_vstart,
84 unsigned long sram_size,
85 unsigned long pstart_avail,
86 unsigned long size_avail);
87
88/* 82/*
89 * Depending on the target RAMFS firewall setup, the public usable amount of 83 * Depending on the target RAMFS firewall setup, the public usable amount of
90 * SRAM varies. The default accessible size for all device types is 2k. A GP 84 * SRAM varies. The default accessible size for all device types is 2k. A GP
@@ -93,16 +87,7 @@ extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
93 */ 87 */
94static int is_sram_locked(void) 88static int is_sram_locked(void)
95{ 89{
96 int type = 0; 90 if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
97
98 if (cpu_is_omap44xx())
99 /* Not yet supported */
100 return 0;
101
102 if (cpu_is_omap242x())
103 type = omap_rev() & OMAP2_DEVICETYPE_MASK;
104
105 if (type == GP_DEVICE) {
106 /* RAMFW: R/W access to all initiators for all qualifier sets */ 91 /* RAMFW: R/W access to all initiators for all qualifier sets */
107 if (cpu_is_omap242x()) { 92 if (cpu_is_omap242x()) {
108 __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */ 93 __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
@@ -127,7 +112,7 @@ static int is_sram_locked(void)
127 * to secure SRAM will hang the system. Also the SRAM is not 112 * to secure SRAM will hang the system. Also the SRAM is not
128 * yet mapped at this point. 113 * yet mapped at this point.
129 */ 114 */
130void __init omap_detect_sram(void) 115static void __init omap_detect_sram(void)
131{ 116{
132 unsigned long reserved; 117 unsigned long reserved;
133 118
@@ -213,7 +198,7 @@ static struct map_desc omap_sram_io_desc[] __initdata = {
213/* 198/*
214 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early. 199 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
215 */ 200 */
216void __init omap_map_sram(void) 201static void __init omap_map_sram(void)
217{ 202{
218 unsigned long base; 203 unsigned long base;
219 204
@@ -330,7 +315,7 @@ u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
330#endif 315#endif
331 316
332#ifdef CONFIG_ARCH_OMAP2420 317#ifdef CONFIG_ARCH_OMAP2420
333int __init omap242x_sram_init(void) 318static int __init omap242x_sram_init(void)
334{ 319{
335 _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init, 320 _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
336 omap242x_sram_ddr_init_sz); 321 omap242x_sram_ddr_init_sz);
@@ -351,7 +336,7 @@ static inline int omap242x_sram_init(void)
351#endif 336#endif
352 337
353#ifdef CONFIG_ARCH_OMAP2430 338#ifdef CONFIG_ARCH_OMAP2430
354int __init omap243x_sram_init(void) 339static int __init omap243x_sram_init(void)
355{ 340{
356 _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init, 341 _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
357 omap243x_sram_ddr_init_sz); 342 omap243x_sram_ddr_init_sz);
@@ -407,7 +392,7 @@ void omap3_sram_restore_context(void)
407} 392}
408#endif /* CONFIG_PM */ 393#endif /* CONFIG_PM */
409 394
410int __init omap34xx_sram_init(void) 395static int __init omap34xx_sram_init(void)
411{ 396{
412 _omap3_sram_configure_core_dpll = 397 _omap3_sram_configure_core_dpll =
413 omap_sram_push(omap3_sram_configure_core_dpll, 398 omap_sram_push(omap3_sram_configure_core_dpll,
@@ -423,7 +408,7 @@ static inline int omap34xx_sram_init(void)
423#endif 408#endif
424 409
425#ifdef CONFIG_ARCH_OMAP4 410#ifdef CONFIG_ARCH_OMAP4
426int __init omap44xx_sram_init(void) 411static int __init omap44xx_sram_init(void)
427{ 412{
428 printk(KERN_ERR "FIXME: %s not implemented\n", __func__); 413 printk(KERN_ERR "FIXME: %s not implemented\n", __func__);
429 414
diff --git a/arch/arm/plat-omap/sram.h b/arch/arm/plat-omap/sram.h
new file mode 100644
index 000000000000..29b43ef97f20
--- /dev/null
+++ b/arch/arm/plat-omap/sram.h
@@ -0,0 +1,6 @@
1#ifndef __PLAT_OMAP_SRAM_H__
2#define __PLAT_OMAP_SRAM_H__
3
4extern int __init omap_sram_init(void);
5
6#endif /* __PLAT_OMAP_SRAM_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 01:26:06 -0500